August 4, 2006 Freescale MRF6P3300H RF Power Field Effect Transistor Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
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Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 MOSFET Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Passivation and Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 RF-LDMOS Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 Critical Dimensions 5 References A Apendix A: TEM and EELS Gate Oxide Analysis A.1 Addendum: Gate Oxide Analysis A.2 Transistor Dimensions Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Package Side 2.1.4 Package X-Ray Side-View 2.1.5 MRF6P3300H Package Cavity 2.1.6 MOSFET Die 2.1.7 MRF6P3300H MOSFET Die 2.1.8 MOSFET Die Markings 1 2.1.9 MOSFET Die Markings 2 2.1.10 Capacitor Die 2.1.11 Capacitor Die Markings 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 MOSFET Die Tilt-View 2.2.6 MOSFET Die Die Corner and ESD Protection 2.2.7 Detail ESD Protection 3 Process Analysis 3.1.1 General View of MRF6P3300H 3.1.2 Die Thickness 3.1.3 Die Edge 3.1.4 Edge Seal 3.2.1 Bond Pad 3.2.2 Bond Pad Edge 3.3.1 Passivation 3.3.2 IMD 3.3.3 PMD 3.4.1 Minimum Width Metal 2 3.4.2 Minimum Pitch Metal 1 3.4.3 Tungsten Silicide Gate Shield 3.5.1 Via 3.5.2 Contact to Polycide 3.5.3 Contact to Diffusion 3.5.4 Contact to Diffusion Interface 3.6.1 Minimum Pitch Poly 3.6.2 Transistor Array Section Map 3.6.3 RF-LDMOS Transistor Overview 3.6.4 RF-LDMOS Transistor Overview SCM 3.6.5 RF-LDMOS Transistor Drain and Source 3.6.6 Detail of Gate SCM
Overview 1-2 3.6.7 Detail of Gate 3.6.8 RF-LDMOS Transistor Overview Source Contacts 3.6.9 Gate Contact (Parallel to Gate) 3.6.10 Source Contact (Parallel to Gate) 3.6.11 Drain Contact (Parallel to Gate) 3.6.12 ESD Protection Structure Overview 3.6.13 Detail of Gate from ESD Protection Structure 3.7.1 Recessed LOCOS Isolation Width 3.7.2 Recessed LOCOS Isolation Thickness and Bird s Beak 3.8.1 SCM of Wells and Substrate 3.8.2 SRP Analysis Site 3.8.3 SRP P-Well A Apendix A: TEM and EELS Gate Oxide Analysis A.1.1 TEM CMOS Gate A.1.2 TEM Gate Oxide Thickness A.1.3 STEM Image of Gate Oxide A.1.4 EELS Line Plot Gate Oxide A.1.5 STEM Image of Interface Line Profile A.1.6 EELS Line Plot Interface A.1.7 EELS Spectrum
Overview 1-3 1.2 List of Tables 1 Overview 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package and Die Dimensions 3 Process Analysis 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Polycide Dimensions 4 Critical Dimensions 4.0.1 Package and Die Dimensions 4.0.2 Dielectric Thicknesses 4.0.3 Metallization Vertical Dimensions 4.0.4 Metallization Horizontal Dimensions 4.0.5 Via and Contact Dimensions 4.0.6 Transistor and Polycide Dimensions A Apendix A: TEM and EELS Gate Oxide Analysis A.2.1 Transistor Dimensions
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