THE present trends in the development of integrated circuits

On-chip Prmetric Test of -2 Ldder Digitl-to-Anlog Converter nd Its Efficiency Dniel Arbet, Vier Stopjková, Jurj Brenkuš, nd Gábor Gyepes Abstrct This pper dels with the investigtion of the fult detection in seprted prts of mixed-signl integrted circuit exmple by implementing prmetric test methods. The experimentl Circuit Under Test (CUT) consisting of n 8-bit binryweighted -2 ldder digitl-to-nlog converter nd dditionl on-chip test hrdwre ws designed in stndrd 0.35μm CMOS technology. For detection of ctstrophic nd prmetric fults considered in different prts of the CUT, two dedicted prmetric test methods: oscilltion-bsed test technique nd I DDQ monitoring were used. For the opertionl mplifier, onchip nd off-chip pproches hve been used to compre the efficiency of both pproches in covering ctstrophic fults tht re hrd to detect. For respective converter prts, the excelent fult coverge of 94.21% of hrd-detectble fults by the proposed prmetric tests ws chieved. Index Terms Fult detection, ctstrophic fults, prmetric fults, on-chip prmetric test, mixed-signl test I. INTODUCTION THE present trends in the development of integrted circuits nd new dvnced technologies enble integrtion of complex digitl nd mixed-signl systems on single chip. These complex systems, know s Systems-on-Chip (SoC), cn include digitl, nlog, nd F circuits s well s MEMS structures, microsensors nd nother different cores. No doubt, testbility of the respective prts in such systems is gretly decresed [1]. Stndrd test methods cnnot be strightforwrdly used to test complex mixed-signl systems. Therefore, severl utomtic test equipments (ATE), ech dedicted to prticulr core integrted in the system, would be needed. Such pproch increses costs of IC production uncceptbly, since it requires the expensive nd dvnced ATE. Due to this reson, test methodology for complex systems becomes the upmost importnt. Test engineers hve been looking for new test methods nd pproches, which cn ssure better testbility, higher fult coverge nd high qulity of integrted system production. Prmetric test methods re most commonly used for testing nlog nd mixed-signl integrted circuits (IC). These methods re bsed on the monitoring of specific circuit s prmeter such s voltge, supply current, frequency, etc. Evlution of the specific prmeter in complex system is This work ws supported in prt by the Ministry of Eduction, Science, eserch nd Sport of the Slovk epublic under grnts VEGA 1/0285/09, VEGA 1/1008/12, VMSP-II-0042-09 APVV nd the Centre of Excellence for Smrt Technology, Systems nd Services II, ITMS Code 26240120005. All uthors re with Institute of Electronics nd Photonics, Fculty of Electricl Engineering nd Informtion Technology, Slovk University of Technology, Ilkovicov 3, Brtislv 812 19, Slovki (corresponding uthor: D. Arbet, phone: +421260291163; fx: ++421265423480; e-mil: dniel.rbet@stub.sk). difficult becuse it requires sophisticted sensing nd nlyses of the selected prmeter in terms of dditionl hrdwre needed, setting the Pss/Fil limit, robustness, etc. (in comprison to the simple logic test). On the other hnd, prmetric test, performed for prt of the complex system, my be the only proper nd/or implementble test pproch in some pplictions [2]. Such pproch is bsed on dividing the complex system into smller prts tht could be esily tested seprtely, ech prt by dedicted test method. In this pper, n 8-bit -2 ldder digitl-to-nlog converter (DAC) ws used s the test vehicle. Considering the structure of this circuit, it ws split into two prts, which hve been tested seprtely using two different prmetric test methods. Thus, the control logic, used for selecting the test method nd switching the circuit mode (test/functionl), hs been designed. In Section 2, the preliminry work done in the respective re is described. Experimentl CUT is presented in more detils in Section 3. In Section 4, the proposed test strtegies employed in test of the respective prt of the DAC re described. In Section 5, influence of dditionl test hrdwre on the DAC preformnce is ddressed. Simultion results nd chieved fult coverge re summrized in Section 6. In the lst section, the efficiency of the proposed test method through the obtined experimentl results is discussed. II. PELIMINA WOK Digitl-to-nlog converters nd nlog-to-digitl converters (ADC) re very often used circuits in the mixed-signl integrted systems. However, to test such systems by conventionl externl pproches, ccurte mesurement instruments s well s dvnced nd costly ATE [3] re necessry. Therefore, Built-In Self Test (BIST) pproches represent the best solution or sometimes, even the only possible wy of testing mixed-signl circuits like converters re. Thus, BIST cn significntly reduce test time nd overll cost since the most difficult tsks re performed directly on chip. In the lst yers, mny BIST structures hve been published, nd severl different modifictions of BIST pproch pplicble to DAC nd ADC hve been proposed [4] [6]. The IEEE stndrd for terminology nd test methods of digitlto-nlog converters is described in [7]. In [8] [10], different on-chip test hrdwre hs been proposed nd used for testing the dt converters. BIST metodologies using different onchip input stimuli genertors were described in [11] nd [12]. A BIST scheme for DAC testing, bsed on the undersmpling technique presented in [13], ws proposed in [14]. The oscilltion-bsed test for nlog-to-digitl nd digitl-tonlog converters hs been ddressed in [6], [15] nd [16].

OUTPUT Another BIST structures for very populr -2 ldder DAC were ddressed in [9], [17]. However, the efficiency of the existing on-chip test pproches in covering rel hrd-detctble fults hs still some limittions, nd it shoud be improved in order to ssure the necessry relibility. Moreover, most of the prmetric test methods re not mture enough to be implemented s fully on-chip test pproch, since they suffer either from complexity of the hrdwre or from test stimuli gerertion. In this pper, on-chip prmetric test of 8-bit -2 ldder DAC is presented. The converter is split into two prts: the opertionl mplifier nd -2 resistor network, which re tested seprtely by oscilltion test method [18] [21] nd I DDQ monitoring [22] [25], respectively. This pproch is esy to implement nd offers rther high fult coverge of hrd-detectble fults. Furthermore, input test stimuli re esy to generte on-chip, nd the proposed pproch is ble to identify defective prt of the CUT. III. EXPEIMENTAL CICUIT UNDE TEST Fig. 1 shows the block digrm of the experimentl mixedsignl circuit designed in 0.35μm CMOS technology, which consists of the selected converter nd the necessry on-chip test hrdwre, including the control logic used for switching the circuit into the test mode. As mixed-signl CUT, n 8- bit binry-weighted -2 ldder DAC hve been designed nd used in our experiment. In the test mode, the DAC circuit is split into two seprted prts: 2-stge opertionl mplifier (OPAMP) nd the -2 resistor network. Using two dditionl inputs TEST nd MODE, the circuit cn be switched in one of two test modes in order to test the respective prt of the converter seprtely, ech by employing dedicted prmetric test method. Fig. 1. CL LOAD / MODE TEST VEF Additionl test hrdwre nd control logic -2 resistor network VDD Dt inputs GND 2-stge opertionl mplifier D7 D6 D5 D4 D3 D2 D1 D0 Block digrm of the mixed-signl CUT used IV. POPOSED TEST STATEG A. Off-chip test of opertionl mplifier For the fult detection in the opertionl mplifier (OPAMP), the oscilltion test method trnsforming the mplifier into n oscilltor by inserting feedbck C network ws used. Using this method, different fults present in the mplifier nd cusing devition either in the oscilltion frequency or OUTPUT I EF1 I EF2 2 D0 D1 OPAMP F C buffer 1 On-chip OPAMP Fig. 2. Circuit digrm of the OPAMP circuit trnsformed into n oscilltor (without control logic) in the mplitude of oscilltions (exceeding the nominl fultfree tolernce rnge) cn be detected [20]. Components in the feedbck network were connected externlly (by T-gtes) using two dditionl input pins (DO nd D1) nd the output pin OUTPUT (Fig. 2). In this configurtion, smller devition in the oscilltion frequency nd the mplitude of oscilltions were reched. The feedbck resistor F, which is prt of the DAC, is clmped to ground using two MOS trnsistors. A buffer is defult prt of the converter but in this topology, it ws lso used to seprte the OPAMP from possible externl influences. The OPAMP cn be tested by pplying logic 1 nd logic 0 to pins TEST nd MODE, respectively (Fig. 1). Then the common control logic (not depicted in Fig. 2) genertes the control signls () for T- gtes tht for test purposes, disconnect the OPAMP from the -2 resistor network nd connect the feedbck network. T-gtes were used for insertion of the feedbck. However, they my cuse the CUT performnce degrdtion nd therefore, their ON- nd OFF- resistnces must be s low s possible nd s high s possible, respectively. Hence, the ON-resistnce of T-gtes, which re ppering in the signl pth, must be minimized to prevent the undesired performnce degrdtion [26]. The fult-free tolernce bnds (representing process vritions nd temperture influence) for the oscilltion frequency nd the mplitude of the oscilltion frequency were obtined by Monte Crlo nlysis, nd re depicted in Fig. 3 nd Fig. 4, respectively. Devitions (obtined by 50 runs) of ±13% in the oscilltion frequency nd of ±2.85% in the oscilltion mplitude were observed. B. On-chip test of opertionl mplifier Previously, the feedbck network nd pssive components were relized externlly using discrete devices in order to chieve higher ccurcy nd smller devition in the oscilltion

Number of bins 9 8 7 6 5 4 3 mu = 1.03162M sd = 61.118K N = 50 devition = +/- 13% IN NON_INV IN INV TEST C OPAMP OUT TEST TEST f OSC 2 1 0 900.0k 950.0k 1.0M 1.1M 1.1M 1.1M frequency 2 F Fig. 3. Nominl devition in the oscilltion frequency Fig. 5. Circuit digrm of the OPAMP circuit trnsformed into n oscilltor (without control logic) Number of bins 10 8 6 4 mu = 1.17012 sd = 11.2154m N = 50 devition = +/- 2.35% obtined for externl reference oscilltor (Fig. 6). 35 Off-chip FB with externl oscilltor 30 On-chip FB with Schmitt oscilltor 25 2 0 1.14 1.15 1.16 1.17 1.18 1.19 mplitude Frequency 20 15 Fig. 4. Fult-free devition in the mplitude of oscilltions 10 5 frequency nd the mplitude of oscilltions. Tking into ccount SoC testing requirements, where sort of BIST strtegy to test the mixed-signl cores (e.g. DACs) is demnded, n on-chip test should be performed. Therefore, in such cse, the OPAMP feedbck network must be connected internlly, using devices with bout 20% devition in technology prmeters. In [21], such OBIST strtegy for testing OPAMP s prt of complex nlog nd mixed-signl systems is described. To evlute the efficiency of this test strtegy, the circuit oscilltion frequency is then compred to the reference frequency given by Schmitt trigger oscilltor, which ws used s the onchip frequence reference to compenste technology vritions. Fig. 5 shows the circuit digrm of the on-chip oscilltor using n on-chip feedbck network for trnsforming the OPAMP into the oscilltor. The oscilltion frequency ws evluted by countering number of oscilltion pulses exhibited by the CUT during time intervl generted by the reference oscilltor. Influence of technology vritions on the oscilltion frequency for fultfree CUT ws obtined from Monte Crlo nlysis. MC nlysis of technology vritions of ±3σ ws performed for ll devices used in the CUT nd dditionl test hrdwre. To demonstrte the efficiency of the on-chip oscilltion test pproch, the fult-free tolernce bnds obtined for the onchip feedbck network reliztion ws compred to the one 0 0.90 0.95 1.00 1.05 1.10 f mes / f nom Fig. 6. Comprison of the oscilltion frequency tolernce bnds for on-chip nd off-chip reference oscilltor solutions From Fig. 6, one cn observe tht devition in the oscilltion frequency for the on-chip feedbck network nd the on-chip reference oscilltor is pretty much the sme s the oscilltion frequency devition obtined by off-chip feedbck network nd the externl oscilltor. This result proves tht the oscilltion test strtegy offers the on-chip test of the opertionl mplifier s seprted prt of the experimentl DAC. With the on-chip test, stndrd mixed-signl SoC test requirements could be fulfilled. A more detiled description of the proposed on-chip test strtegy, including the oscilltion frequency evlution nd the PASS/FAIL threshold selection, is presented in [21]. C. Test of -2 resistor network The -2 ldder is resistor network tht uses cscded structure of current dividers, which generte binry-weighted currents in the respective brnches, s shown in Fig. 7. In idel

V EF S8 S8 I 8 I 7 I 1 I 0 S8 S7 S7 S1 S1 S8 S7 S7 S1 S1 I EF1 This procedure goes on till the lst two current brnches re processed. The current difference t ech step of the proposed test procedure cn be expressed s follows: ( N ) I diff N = I N I N 1 i=0 (1) Fig. 7. V VSS_EF Circuit digrm of the -2 ldder I EF2 cse, the dividing rtio should be 2:1 but becuse of resistors mismtch, in relity, the divisions will be imperfect. The most probble fult in the resistor ldder is tht the vlue of resistor exceeds its tolernce bnd (prmetric fult). These fults cn be detected by the mesurement nd evlution of current vlue in the respective current brnches. The described technique hs been used for prmetric test of the -2 ldder, which represent substntil prt of the whole DAC circuit. Modifiction of this method, used in digitl IC test, is known s I DDQ testing. Principle of current testing of the -2 ldder is s follows: in the first step, current I8 is compred to the sum of currents I7 to I0, then in the second step, the control logic turnsoff switches S8 nd S8, nd current I7 is compred to the sum of currents I6 to I0. Consequently, control logic turns-off switches S7 nd S7, nd nother two currents re compred. where N = 1, 2, 3,... 8 nd IN is current in the respective brnch being sensed. Circuit digrm of -2 ldder with the dditionl test hrdwre is depicted in Fig. 8. In every brnch of the resistive network, two T-gtes were included to switch-off the corresponding brnch. Control signls for T-gtes (, nd lso 1-8 ) were generted by the common control logic. Circuitry performing the current difference consists of three cscode current mirrors, s shown in Fig. 8 (right side). This circuit lso ensures tht the differentil current (difference of I EF 1 nd I EF 2 ) will flow out to the circuit s output. This pproch cn test the resistor ldder in totl eight steps, by shifting the logic 1 from MBS to LSB. The min problem of this method is tht current in the lst brnch is in order of na, which is difficult to sense nd mesure with necessry precision. Therefore, this test technique might be limited to ldders tht use resistors with the resistnce vlue smller thn 10kΩ. A fult-free tolernce bnd of the differentil current I diff ws obtined by Monte Crlo nlysis nd chieved results will be presented in the following section. V EF I 8 I 7 I 1 I 0 M11 M12 V VSS_EF 8 8 7 7 1 1 I EF1 I EF2 M3 M9 M4 M7 M10 M8 I DIFF M1 M2 M5 M6 LATCH LATCH LATCH CL LOAD D_IN CL LOAD D_IN CL LOAD D_IN CUENT DIFFEENTIAL CICUIT CL LOAD -2 LADDE D7 D6 D0 Fig. 8. Circuit digrm of -2 ldder with dditionl test hrdwre (without control logic)

V. INFLUENCE OF ADDITIONAL TEST HADWAE Insertion of the necessry on-chip test hrdwre might undesirbly ffect the DAC performnce. The min reson is probbly the use of T-gtes (disconnecting the individul prts), which hve some resistnce in switch-on stte. The most criticl re T-gtes tht re connected in the pth leding to the circuit output. Fig. 9 shows how the integrl nd the differentil nonlinerity (INL nd DNL ) of the DAC (with the test hrdwre) depend on the ON resistnce of T-gtes connected in the pth leding to the converter output. 12.0 9.0 INL' DNL' 15.0 12.0 SN [db] 50 45 40 35 Fig. 11. Signl to Noise tio Efective Number of Bits 30 5.0 10 100 1k 10k ON_T-gte [Ω] SN nd ENOB versus ON of T-gte 8.5 8.0 7.5 7.0 6.5 6.0 5.5 ENOB 9.0 INL' Fig. 9. 6.0 3.0 50 100 150 200 on_t-gte [Ω] INL nd DNL versus ON of T-gte It cn be observed tht in order to mintin the originl prmeters of DAC, ON of T-gtes should be order of tens of Ohms. If the T-gtes with ON of bout 10 Ω re used, the vlue of integrl nd differentil nonlinerity will be incresed by 18% nd 27%, respectively. In such cse, the dditionl test hrdwre will require the re of 0.002 mm 2, which mens tht the totl re will be enlrged by 13%. From the spect of testing it is therefore, necessry to find good compromise between the CUT performnce nd the test hrdwre re overhed. Fig. 10 nd Fig. 11 show how the other min prmeters of the digitl-to-nlog converter (with the dditionl test hrd- OE, FSE, GE [V] Fig. 10. 160.0m 140.0m 120.0m 100.0m 80.0m offset error (OE) full scle error (FSE) gin error (GE) 60.0m 40.0m 20.0m 0.0-20.0m -40.0m -60.0m -80.0m -100.0m -120.0m -140.0m -160.0m 10 100 1k 10k ON_T-gte [Ω] OE, FSE nd GE versus ON of T-gte 6.0 3.0 DNL' wre) depend on the switch-on resistnce of T-gtes connected in pth leding to the converter output. It cn be observed tht to mintin the originl vlue of the full scle error (FSE), signl-to-noise rtion (SN) nd effective number of bits (ENOB) prmeters, it would be sufficient to use T-gte with ON of bout 100 Ω. However, chieve the originl vlues of INL, DNL, offset error (OE) nd gin error (GE), ON should be bout of tens of Ohms. Thus, it cn be concluded tht to mintin the originl vlue of ll prmeters of the converter, ON of T-gtes should be kept in the rnge from 10 to 100 Ohms. In this cse, the totl re overhed would be enlrged from 6.5% to 13%. VI. ACHIEVED ESULTS For verifiction of the efficiency of the proposed test methods in testing prts of DACs, four types of ctstrophic fults in the OPAMP, nd two prmetric fults in the - 2 ldder were considered. Ctstrophic fults such s shorts, opens, gte-oxide shorts (GOS) nd floting gtes (FG) were inserted. Short nd open fults were injected in ll connection pths, while GOS nd FG fults were pplied in ll trnsistors forming the OPAMP. Prmetric fults, which most commonly rise on pssive devices, were modeled nd injected in the - 2 resistor network. A. esults of the opertionl mplifier test In the opertionl mplifier, severl ctstrophic fults such s opens nd shorts s well s floting gtes nd gte-oxideshorts, were considered. For their detection, the oscilltionbsed test method of the OPAMP circuit ws employed. Opens were modeled using prllel combintion of resistor nd cpcitor. esistors nd cpcitors vlues depend on the defect loction nd size. We hve considered nine different open fults injected in 24 different loctions. From ll considered 216 opens, 209 fults were detected, which mens tht the fult coverge of 94% ws chieved. However, opens modeled with the resistnce vlue of 1 MΩ represent so cll hrd-detectble fults. Thus, opens hving higher resistnce would probbly not be covered by other test technique either.

Short fults were modeled nd simulted using seril short resistor. Vlues of resistors considered s short fults re s follows: 500 Ω, 1kΩ, 10k Ω, 100 kω nd 1 MΩ. The chieved fult coverge, presented for different rnges of the short resistnce vlue, is presented in Tble I. TABLE I FAULT COVEAGE OF SHOT FAULTS short [Ω] 500 10k 500 100k 500 1M Fult Coverge 100% 95.58% 84.7% It cn be observed tht shorts with lower resistnce re esier to detect becuse, in most cses, such shorts led to loss of the oscilltions or significnt devition in the mplitude of oscilltions. Shorts with the resistnce higher thn 100 kω usully cuse only slight devition in the oscilltion frequency tht mkes them more difficult to detect. For floting gtes (FG) we used n extended electricl model described in [27], considering lso cpcity of the brek. Hence, the FG fult model includes cpcitors C mp, C pb nd C brek, which vlues were set to 2.82 ff, 3.02 ff nd 0.07 ff, respectively. All considered FG fults were esily detected through either loss of the oscilltion or chnge in the oscilltion frequency (single fult). The worst cse of the overll fult coverge of ll ctstrophic fults, using the externl oscilltor feedbck network, is summrized in Tble II. TABLE II WOST CASE OF OFF-CHIP TOTAL FAULT COVEAGE Fults Fult coverge Shorts 84.7% Opens 94% FGs 100% Totl 92.9% The totl fult coverge chieved for on-chip reliztion of the proposed prmetric test of the OPAMP block is summrized in Tble III. TABLE III TOTAL FAULT COVEAGE FO ON-CHIP TEST OF OPAMP different ctstrophic fults (including hrd-detectble ones) in nlog sub-circuits. We lso nlyzed the possible dependence of the fult coverge in the OPAMP on the vlue of the oscilltion frequency. To test the mplifier by oscilltion-bsed strtegy t different oscilltion frequencies, the vlue of pssive devices used in the positive feedbck loop ws vried. The fult coverge dependence on the vlue of the oscilltion frequency for different shorts nd floting gtes is shown in Fig. 12 nd Fig. 13, respectively. FC [%] 110 100 90 80 70 60 50 40 30 20 10 Short resistnce 500Ohm 1kOhm 10kOhm 100kOhm 1MOhm 0 0.0 2.0M 4.0M 6.0M 8.0M f osc [Hz] Fig. 12. Fult coverge versus the vlue of the oscilltion frequency for different shorts One cn observe tht the best fult coverge cn be chieved t the oscilltion frequency of bout 2 MHz. Shorts with lower resistnce re esy to detect since they usully cuse loss of oscilltions. Shorts with higher resistnce (e.g. of 100 kω, 1 MΩ) cuse devition from the oscillting frequency, which 100 Fults inserted detected Fult coverge Shorts 68 54 79.41% Opens 216 180 83.33% FGs 9 7 77.77% Totl 293 241 82.25% FC [%] 95 90 85 The off-chip pproch offers slightly higher totl fult coverge thn the one chieved in cse of on-chip test reliztion. On the other hnd, on-chip pproch enbles BIST tht is typicl for SoC testing. However, some of the undetected fults hve been mnifested by certin devition in the mplitude of oscilltions (not evluted in our experiment). Therefore, the totl fult coverge might be incresed further by evlution of this prmeter. The obtined results prove tht the oscilltionbsed test pproch cn be reltively very efficient in detecting 80 FC for floting gte fults 75 0,0 2,0M 4,0M 6,0M 8,0M f OSC [Hz] Fig. 13. Fult coverge versus the oscilltion frequency vlue for floting gte fults

mkes them more difficult to detect. Generlly, the shorts with lower short resistnce re esily detectble t lower oscilltion frequencies, while the shorts with higher resistnce (in order of 100 kω) re better covered t the higher frequency (bout 4.5 MHz). Finlly, shorts with resistnce of 1 MΩ hve lowest fult coverge in whole frequency rnge but those fults hve low probbility of presence. Secondly, the fult coverge dependence on the vlue of the oscilltion frequency for floting gte fults ws investigted (Fig. 13). It cn be observed tht 100% fult coverge cn be chieved for the vlue of the oscilltion frequency of 3 MHz nd lso for vlues higher thn 8 MHz. Unfortuntely, for the frequency higher thn 8.5 MHz the CUT does not fulfill the conditions needed for the ppernce of sustined oscilltions. B. esults of -2 ldder test In contrst to the OPAMP test, prmetric fults were considered in the resistor network (-2 ldder), nd the fult coverge by the proposed current test method ws investigted. Possible prmetric fults in the resistor network were simulted using resistor with vrying its resistnce vlue. It ws considered tht the vlue devites by 5% or 10% from the tolernce rnge. Fig. 14 shows the tolernce bnd nd simulted vlues of the output differentil current depending on the test vector being pplied. I diff [ua] 6.0 4.0 2.0 0.0-2.0-4.0-6.0 TOLEANCE BAND 10000000 01000000 00100000 00010000 00001000 00000100 00000010 Test vector -5% +5% -10% +10% I_min I_mx 00000001 Fig. 14. Tolernce bnd nd simulted vlues of the differentil current in -2 ldder The simultion results show tht lmost ll prmetric fults in the resistor network re detectble. However, prmetric fult considered in the lst brnch is difficult to detect becuse the current is too smll to be sensed precisely. Tble IV shows the fult coverge chieved by current monitoring pproch for prmetric fults considered in the resistor network. It cn be observed tht 10% devition in resistors vlue is fully detectble nd 100% fult coverge is reched. When the resistors vlue devites from its tolernce bnd by 5%, the fult coverge is slightly lowered to 96% tht is still very good result. Finlly, we cn stte tht the proposed current test method is esy to implement nd provides very high efficiency in TABLE IV FAULT COVEAGE OF SHOT FAULTS Prmetric fult ±5% devition ±10% devition Fult Coverge 96% 100% covering prmetric fults. However, the method might be limited by resistnce vlues of resistors used in the ldder, since high vlues led to less current flowing through the respective brnches, which is rther difficult to be mesured nd processed. VII. DISCUSSION &CONCLUSION Two different prmetric test methods hve been used for on-chip fult detection in the -2 ldder digitl-to-nlog converter. For this purpose, n experimentl circuit, consisting of the DAC, the dditionl test hrdwre, nd the control logic for switching the DAC between functionl nd test modes, hs been designed in selected CMOS technology. The control logic ws used to split the circuit into two prts, ech tested seprtely by dedicted method. An opertionl mplifier ws tested by the oscilltion-bsed test strtegy, while current monitoring ws used to test the resistor ldder. The crucil point of the used test strtegy is tht the insertion of the necessry dditionl test hrdwre might ffect the CUT performnce. However, with pproprite setting of ON of the inserted T-gtes, this influence cn be minimized. T-gtes with ON of bout 10 Ω cuse re overhed of 13%, nd increse of 18% nd 27% in INL nd DNL prmeters, respectively. Ctstrophic nd prmetric fults were considered in the CUT. In the worst cse, the totl fult coverge of 92.42% nd 96% for the OPAMP nd the resistor network ws chieved, respectively. This is n excellent result especilly, if tking into ccount tht the fult coverge up to 94.21% of hrddetectble fults by prmetric test of single prts of the DAC hs been chieved. The on-chip totl fult coverge might be incresed by mesuring the mplitude of oscilltion. However, for evlution of the mplitude of oscilltion, the dditionl test hrdwre will be necessry, which would increse the re overhed. On-chip prmetric test of seprted prts is promising strtegy to test complex mixed-signl systems. This pproch offers the possibility to identify defective prt nd mkes test of such systems esier or, in some pplictions, even possible t ll. However, it is necessry to mintin the circuit s originl functionlity nd specific prmeters. Further reserch in this field will be focused on reliztion of BIST structures, bsed on the oscilltion test strtegy, which would be generlly pplicble for digitl-to-nlog converters s cores used in complex SoCs. ACKNOWLEDGMENT This work ws supported in prt by the Ministry of Eduction, Science, eserch nd Sport of the Slovk epublic under grnts VEGA 1/0285/09, VEGA 1/1008/12, VMSP-II-0042-09 APVV nd the Centre of Excellence for Smrt Technology, Systems nd Services II, ITMS Code 26240120005. Authors lso thnk -DAS, s.r.o for reserch support.

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Kminsk, Oscilltion-test strtegy for nlog nd mixed-signl integrted circuits, in VLSI Test Symposium, 1996., Proceedings of 14th, pr-1 my 1996, pp. 476 482. [21] D. Arbet, J. Brenkus, G. Gyepes, nd V. Stopjkov, Incresing the efficiency of nlog OBIST using on-chip compenstion of technology vritions, in Design nd Dignostics of Electronic Circuits Systems (DDE), 2011 IEEE 14th Interntionl Symposium on, pril 2011, pp. 71 74. [22]. jsumn, Iddq testing for CMOS VLSI, Proceedings of the IEEE, vol. 88, no. 4, pp. 544 568, pril 2000. [23] S. Bhuni, H. Li, nd K. oy, A high performnce IDDQ testble cche for scled CMOS technologies, in Test Symposium, 2002. (ATS 02). Proceedings of the 11th Asin, nov. 2002, pp. 157 162. [24]. jsumn, Design-for-iddq-testing for embedded cores bsed system-on--chip, in IDDQ Testing, 1998. Proceedings. 1998 IEEE Interntionl Workshop on, nov 1998, pp. 69 73. [25] V. Stopjkov nd H. Mnheve, CCII+ current conveyor bsed BIC monitor for IDDQ testing of complex CMOS circuits, in Europen Design nd Test Conference, 1997. ED TC 97. Proceedings, mr 1997, pp. 266 270. [26] K. Arbi nd B. Kminsk, Oscilltion built-in self test (OBIST) scheme for functionl nd structurl testing of nlog nd mixed-signl integrted circuits, in Test Conference, 1997. Proceedings., Interntionl, nov 1997, pp. 786 795. [27] A. M. Bros nd J. Figuers, Chrcteriztion of floting gte defects in nlog cells, Journl of Electronic Testing, vol. 14, pp. 23 31, 1999, 10.1023/A:1008388903741. [Online]. Avilble: http://dx.doi.org/10.1023/a:1008388903741 Dniel Arbet received the M.S. degree in Electronics from Slovk University of Technology in Brtislv, Slovki in 2009. Since October 2009 he hs been PhD student t the Institute of Electronics nd Photonics of Slovk University of Technology. He hs published more thn 10 ppers. His min reserch interests re low-voltge low-power nlog design, on-chip prmetric testing, nlog BIST nd test implementtion. Vier Stopjková received the M.S. degree nd the PhD degree in Electronics from Slovk University of Technology in Brtislv, Slovki, in 1992, nd 1997, respectively. From October 1997 to September 2003 nd from October 2003 to June 2009 she ws n ssistnt professor nd n ssocited professor t Microelectronics Deprtment, Fculty of Electricl Engineering nd Informtion Technology of Slovk University of Technology in Brtislv, respectively. Currently, she is full professor t the Institute of Electronics nd Photonics of the sme university. She hs been involved in severl EU funded reserch projects under different funding schemes such s TEMPUS, ESPIT, Copernicus, FP, ENIAC-JU, nd lso in ntionl reserch grnts. She hs published over 90 ppers in vrious journls nd conference proceedings; nd she is co-inventor of two US ptents in the field of on-chip supply current testing. Her min reserch interests include IC design, VLSI & SoC testing, on-chip testing, design nd test of mixed-signl circuits, biomedicl monitoring, nd neurl network implementtions nd pplictions. Jurj Brenkuš received the M.S. degree in Electronics from Slovk University of Technology in Brtislv, Slovki in 2000. Since Mrch 2010 he hs been resercher t Institute of Electronics nd Photonics of Slovk University of Technology. He is the uthor or co-uthor of more thn 20 ppers presented t interntionl conferences. His min reserch interests re IC design nd test, mixedsignl systems design, SoC design, on-chip testing nd test development utomtion. Gábor Gyepes received the M.S. degree in Electronics from Slovk University of Technology in Brtislv, Slovki in 2009. Since October 2009 he hs been PhD student t the Institute of Electronics nd Photonics of Slovk University of Technology. His min reserch interests include nlog IC design, memory test nd on-chip current testing. He hs published more thn 10 ppers in these res.