LSI/CSI UL 00 LSI Computer Systems, Inc. Walt Whitman Road, Melville, NY (6) -000 FX (6) -00 PROGRMMLE DIGITL DELY TIMER FETURES: Programmable delay from microseconds to days Programmable delay controlled by binary-weighted delay inputs that can be latched from a shared -bit bus On chip oscillator (RC or Crystal) or external clock time base Selectable prescaler for real time delay generation based on 0Hz/60Hz time base or,6hz watch crystal Four operating modes Reset input for delay abort Low quiescent and operating current Direct relay drive to +V operation ( - VSS), LS6 (DIP); -S, LS6-S (SOIC) - See Figure - DESCRIPTION: The and LS6 are CMOS integrated circuits for generating digitally programmable delays. The delay is controlled by binary weighted inputs, W0 - W, in conjunction with an applied clock or oscillator frequency. The programmed time delay manifests itself in the Delay Output () as a function of the Operating Mode selected by the Mode Select inputs and : One-Shot, Delayed Operate, Delayed Release or Dual Delay. The time delay is initiated by a transition at the Trigger Input (). I/O DESCRIPTION: MODE SELECT Inputs & (Pins & ) The operating modes are selected by Inputs and according to Table TLE. MODE SELECTION MODE 0 0 One-Shot (OS) 0 Delayed Operate (DO) 0 Delayed Release (DR) Dual Delay (DD) LS6 V DD () RC/ RCS/CLKS PSCLS VSS (-V) OD July 09 9 () XTLI/ XTLO PSCLS V SS (-V) OD PIN SSIGNMENT - TOP VIEW 6 LSI 6 9 0 6 LSI LS6 9 6 9 0 W0 W W W W W W6 W W0 W W W W W W6 W Each input has an internal pull-up resistor of about 00kΩ. One-Shot Mode (OS) positive transition at the input causes to switch low without delay and starts the delay timer. t the end of the programmed delay timeout, switches high. If a delay timeout is in progress when a positive transition occurs at the input, the delay timer will be restarted. negative transition at the input has no effect. Delayed Operate Mode (DO) positive transition at the input starts the delay timer. t the end of the delay timeout, switches low. negative transition at the input causes to switch high without delay. is high when is low. FIGURE Delayed Release Mode (DR) negative transition at the input starts the delay timer. t the end of the delay timeout, switches high. postive transition at the input causes to switch low without delay. is low when is high. Dual Delay Mode (DD) positive or negative transition at the input starts the delay timer. t the end of the delay timeout, switches to the logic state which is the inverse of the input. If a delay timeout is in progress when a transition occurs at the input, the delay timer is restarted. -009-
GER Input (, Pin ) transition at the input causes to switch with or without delay, depending on the selected mode. The input to transition relation is always opposite in polarity, with the exception of One-Shot mode. (See Mode definitions above.) input has an internal pulldown resistor of about 00kΩ and is buffered by a Schmitt trigger to provide input hysteresis. TIME SE Input (RC/, Pin ) For, the basic timing signal is applied at the RC/ input. The clock can be provided from either an external source or generated by an internal oscillator by connecting an R-C network to this input. The frequency of oscillation is given by ƒ /RC. Chip-to-chip oscillation tolerance is ± % for a fixed value of RC. The minimum resistance, R MIN =,000Ω, = + V =,0Ω, = +0V =,000Ω, = +V The external clock mode is selected by applying a logic low to the RCS/ CLKS input (Pin ); the internal oscillator mode is selected by applying a high level to the RCS/CLKS input. LS6 TIME SE Input (XTLI/, Pin ) For LS6, the basic timing clock is applied to the XLTI/ input from either an external clock source or generated by an internal crystal oscillator by connecting a crystal between XTLI/ input and the XTLO output (Pin ). TIME SE SELECT Input (RCS/CLKS, Pin ) For, the external clock operation at Pin is selected by applying a logic low to the RCS/CLKS input. The internal oscillator option with RC timer at Pin is selected by applying a logic high at the RCS/ CLKS input. RCS/CLKS input has an internal pull-down resistor of about 00kΩ. LS6 TIME SE Output (XTLO, Pin ) For LS6, when a crystal is used for generating the time base oscillation, the crystal is connected between XTLI/ and XTLO pins. PRESCLER SELECT Input (PSCLS, Pin 6) The PSCLS input is a -state input, which selects one of three prescale factors according to Table. TLE. PRESCLE FCTOR SELECTION PSCLS Input S (Prescale Factor) Logic Level LS6 Float VSS 000 6 600 6 x 60 Using prescale factors of 000 and 600, delays in units of minutes can be produced from 0Hz and 60Hz line sources. Prescale factors of,6 and,6 x 60 can be used to generate accurate delays in units of seconds and minutes, respectively, from a khz watch crystal. TIMER Input (, Pin ) When input switches high, any timeout in progress is aborted and switches high without delay. With high, remains high. When switches low with low in any mode, remains high. When switches low with high in Delayed Operate and Dual Delay modes, the delay timer is started and switches low at the end of the delay timeout. When switches low with high in Delayed Release mode, switches low without delay. When switches low with high in One-Shot mode, remains high. input has an internal pull-down resistor of about 00kΩ and is buffered by a Schmitt Trigger to provide input hysteresis. VSS (-V, Pin ) Supply voltage negative terminal or GND. DELY Output (, Pin 9) Except in One-Shot mode, switches with or without delay (depending on mode) in inverse relation to the logic level of the input. In One-Shot mode, a timed low level is produced at, in response to a positive transition of the input. Input (, Pin ) The input allows the weighting bits, W0 - W, to be latched from a shared bus, such as a MCU IO port. When the is low, the internal weighting bits dynamically follow the data presented at the W0 - W inputs. When the is switched high, the W0 - W data become latched, freeing up the bus to service other peripheral devices. input has an internal pull-down resistor to VSS. OPEN DRIN DELY Output (OD, Pin 0) The OD is the open drain version of the delay output which enables the chip to directly drive a relay, operating at a voltage higher than the chip supply voltage through a single NPN transistor (see Figure 0). Functionally, the OD is identical to the other delay output,. WEIGHTING IT Inputs (W to W0, Pins - ) Inputs W0 through W are binary weighted delay bits used to program the delay according to the following relations: One-Shot Mode: Pulse width = SW ƒ ll other Modes: Delay = SW + 0. ƒ Where: S = Prescale factor (See Table ) ƒ = Time base frequency at Pin W = W0 + W +... W The weighting factor, W, is calculated by substituting in the equation above for W, the weighted values for all the W inputs that are at logic high. The weighted values for the W inputs are shown in Table. Each W input has an internal pull-down resistor of about 00kΩ. (, Pin ) Supply voltage positive terminal. TLE. IT WEIGHTS ITS VLUE W0 W W W W 6 W W6 6 W The information included herein is believed to be accurate and reliable. LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. -009-
SOLUTE MXIMUM RTINGS: (ll voltages referenced to VSS) SYMOL VLUE UNIT DC Supply Voltage +9 V Voltage (ny Pin) VIN VSS - 0. to + 0. V Operating Temperature T - to + C Storage Temperature TSTG -6 to +0 C ELECTRICL CHRCTERISTICS (Voltages referenced to Vss) Characteristic SYMOL - C + C + C Unit Condition Min Max Min Max Min Max Supply Voltage -.0.0.0.0.0.0 V -.0-66 - - µ Supply Current IDD 0.0 - - 0-6 µ with the clock off and.0-0 - 0-60 µ all inputs floating. Input Voltages:.0-0. - 0. - 0. V Reset, Trigger Low VTL 0.0 -. -. -. V -.0 -.9 -. -. V.0. -. -.0 - V Reset, Trigger High VTH 0.0 6. - 6.0 -.9 - V -.0 9. - 0. -.0 - V.0 0. - 0. - 0. - V Reset, Trigger Hysteresis 0.0. -. -. - V -.0.9 -.9 -.9 - V.0 -. -. -. V ll other inputs, Low VIL 0.0 -. -. -. V -.0-0.6-0.6-0.6 V.0.9 -.9 -.9 - V ll other inputs, High VIH 0.0 6. - 6. - 6. - V -.0. -. -. - V Input Currents:.0 -. -. -.9 µ PSCLS Low IPL 0.0 - - - µ Input at VSS.0 - - 6-9 µ.0-9. -. -. µ PSCLS High IPH 0.0 - - -. µ Input at.0 - - 6-9 µ.0-6.0 -.0 -.0 µ, Low IML 0.0-9 - - µ Input at VSS.0 - - - 9 µ, High IMH - - 00-00 - 0 n Input at ll other inputs, Low IIL - - 00-00 - 0 n Input at VSS.0 - - - µ ll other inputs, High IIH 0.0 - - 0 - µ Input at.0 - - 0 - µ Output Current:.0. - 0. - - m, OD Sink IOSNK 0.0 6-9. - - m Vo = +0.V.0 0. -.6 - - m.0. -. -. - m Source IOSRC 0.0. -. -. - m Vo = - 0.V.0. - 6. -.6 - m OD Source - 0-0 - 0 - m In all conditions -069-
ELECTRICL CHRCTERISTICS (Voltages referenced to Vss) (Con t) Characteristic SYMOL Unit Condition Min Max Min Max Min Max Switching Characteristics (See Fig. ).0 -. -. -.0 MHz RC Oscillator Frequency fosc 0.0 -. -. -.6 MHz -.0 -.0 -.0 -.0 MHz.0 -.6 -.0 -. MHz For prescale External Clock or fext 0.0 -. -.0 -.0 MHz factor S = or 000 Crystal Oscillator.0 -.9 -.6 -. MHz or 600 Frequency.0 -. -. -. MHz S = 6 fext 0.0-6.0 -. - 9. MHz or.0 -.9 - - 9. MHz 6 x 60 Set-Up Time t - - 0-66 - ns -, Set-Up Time t - 0-0 - 0 - ns -.0 - - - 9 ns Clock to Out Delay t 0.0-9 - 0 - ns CL = 0pF.0 - - - ns 0 OD 00k MODE REG CONTROL LOGIC UF 9 00k 9 00k LTCH EDGE DETECT - 00k () W-W0 /RC/XTLI 00k LTCH/TIMER LTCH OSC MUX XTLO (LS6) PRESCLER RCS/CLKS () 00k M PSCLS 6 -STTE DECODER M -V VSS -069-
t0 Clock t t, Delayed Operate Mode W0-W W0-W (Internal) Data Latched t Programmed Delay Immediate Release Note. input is clocked in by the negative edge of external clock. Note. Inputs, are sampled only at a input transition and ignored at all other times. Note. is switched by the positive edge of the external clock. FIGURE. INPUT/PUT TIMING (OS) C F (DO) (DR) D (DD) E G H. Turn-on delay in DO and DD modes; Pulse-width in OS mode.. Turn-off delay in DR and DD modes. C. Pulse-width extended by re-trigger in OS mode. No effect in DO and DD modes because switches back low before turn-on delay has timed out. D. Turn-off delay in DR mode. E. Turn-on delay in DO and DD modes; pulse-width in OS mode. F. No effect in DO, DR and DD modes because of s switching back to opposite levels. G. Time-outs aborted and forces high by. H. fter the removal of, switches to the inverse polarity of immediately (DR) or after the timeout (DO, DD). No effect in OS. FIGURE. MODE ILLUSTRTION WITH, ND -000-
0k ƒ 0.µF V DD RCS/CLKS RC pf pf 0k CRYSTL 0M XTLO LS6 XTLI LS6 FIGURE 6. MULTI-TIMER WITH SINGLE CRYSTL TIME-SE V SS V DD ƒ = -6 0 x 0 x 0. x 0 = khz VC M 0pF FIGURE. RC- Oscillator Connection V SS FIGURE. DRIVING INPUT FROM THE C LINE W W - - W0-W W0-W,,,, * * * * GER ƒ 9 9 9 9 VSS VSS * Connect for desired delay and mode FIGURE. DELY EXTENSION Y CSCDING -069-6
GER IN pf ƒ pf 0k S 9 0M 6 XTLI XTLO PSCLS V DD W0 W W W W W W6 W 6 s/m s/m s/m s/m 6s/6m s/m 6s/6m s/m Vss LS6 s = seconds m = minutes PUT 9 NOTE : Crystal Frequency, ƒ =,6Hz Switch: S low: Delay increment = s; Maximum Delay = s S high: Delay increment = m; Maximum Delay = m FIGURE 9. PROGRMMLE CCURTE REL-TIME DELY GENERTION +9V - W0-W IO /6 IO IO OD V SS 0 +V MCU - W0-W VSS /6 OD 0 FIGURE 0. LTCHING WEIGHTING ITS FROM MCU (Example showing separate relay and logic supplies) V SS -009-
V DD W0 W ƒi LS6 W W W W 6 ƒo 9 9 Vss W6 W CSE. MODE = DO or DR; PRESCLE FCTOR, S = In this setup a frequency division of the input clock, ƒi by a factor of to, in increments of can be obtained according to the equation: ƒo = ƒi W + where W (weighting factor) = 0 to The ƒo pulse width is non-symmetrical (non-0% duty -cycle) CSE. MODE = DD; PRESCLE FCTOR, S = In this setup a frequency division of the input clock, ƒi by a factor of to, in increments of can be obtained according to the equation: ƒi ƒo = where W (weighting factor) = 0 to (W + ) The ƒo pulse widths are symmetrical with 0% duty -cycle EXMPLES OF CSE and CSE FREQUENCY DIVISIONS WITH W = ƒi ƒo Case, Mode = DO; ƒo Case, Mode = DD; 6 FIGURE. PROGRMMLE FREQUENCY DIVIDER -006-