EE247 Lecture 27 Administrative EE247 Final exam: Date: Wed. Dec. 19 th Time: 12:30pm-3:30pm Location: 70 Evans Hall Extra office hours: Thurs. Dec. 13 th, 10:am2pm Closed course notes/books No calculators/cell phones/pdas/computers Bring two 8x11 paper with your own notes Final exam covers the entire course material unless specified otherwise EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 1 Administrative Project submission: EE247 Lecture 27 Deadline postponed to Thurs. Dec. 13 th If you have chosen to do the project, please make an appointment with the instructor: Thurs. Dec. 13 th, After 12:30 for 15mins each project report to present the results EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 2
EE247 Lecture 27 Oversampled ADCs (continued) 2 nd order ΣΔ modulator Practical implementation Effect of various building block nonidealities on the ΣΔ performance Integrator maximum signal handling capability (last lecture) Integrator finite DC gain (last lecture) Comparator hysteresis (last lecture) Integrator non-linearity (last lecture) Effect of KT/C noise Finite opamp bandwidth Opamp slew limited settling Implementation example Higher order ΣΔ modulators Cascaded modulators (multi-stage) Single-loop single-quantizer modulators with multi-order filtering in the forward path EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 3 2 nd Order ΣΔ Effect of Integrator KT/C noise V i φ 1 φ 2 Cs - + CI V o 2 2KT vn = Cs 2 kt 1 kt vn / f = 2 = 4 Cs fs /2 Cs fs Total in-band noise: 2 n input referred v 2kT = Cs M kt = 4 f Cs fs B For the example of digital audio with 16-bit (96dB) & M=256 (110dB SQNR) Cs=1pF 7μVrms noise If FS=2V p-p-d then thermal noise @ 01dB degrades overall SNR by ~10dB Cs=1pF, CI=2pF much smaller capacitor area (~1/M) compared to Nyquist ADC Since thermal noise provides some level of dithering better not choose much larger capacitors! EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 4
2 nd Order ΣΔ Effect of Finite Opamp Bandwidth Vi+ Vi- s φ1 φ 2 C I C - + Vo Unity-gain-freq. Input/Output z-transform = f u =1/τ V o φ 2 settling error T=1/f s time Assumptions: Opamp does not slew Opamp has only one pole exponential settling EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 5 2 nd Order ΣΔ Effect of Finite Opamp Bandwidth ΣΔ does not require high opamp bandwidth T/τ >2 or f u > 2f s adequate Note: Bandwidth requirements significantly more relaxed compared to Nyquist rate ADCs Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec. 1988. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 6
2 nd Order ΣΔ Effect of Slew Limited Settling Clock φ 1 φ 2 Vo-ideal Vo-real Slewing Slewing EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 7 2 nd Order ΣΔ Effect of Slew Limited Settling Input Signal = -5dB T/τ =2 Assumption: Opamp settling includes a single-pole setting of τ =1/2f s + slewing Low slew rate degrades SNR rapidly- increases quantization noise and also causes signal distortion Minimum slew rate of S min R ~1.2 (Δ x f s ) required Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec. 1988. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 8
2 nd Order ΣΔ Implementation Example: Digital Audio Application In Ref.: 5V supply, Δ = 4Vp-p-d, f s =12.8MHz M=256 theoretical quantization noise @10dB Minimum capacitor values computed based on 04dB noise wrt maximum signal Max. inband KT/C noise = 7μVrms ( thermal noise dominates provide dithering & reduce limit cycle oscillations) C1=(2kT)/(M v 2 n )=1pF C2=2C1 Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 9 2 nd Order ΣΔ Implementation Example: Integrator Opamp Class A/B type opamp High slew-rate S.C. common-mode feedback Input referred noise (both thermal and 1/f) important for high resolution performance Minimum required DC gain> M=256, usually DC gain designed to be much higher to suppress nonlinearities (particularly, for class A/B amps) Minimum required slew rate of 1.2(Δ.f s ) 65V/usec Minimum opamp settling time constant 1/2fs~30nsec Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 10
2 nd Order ΣΔ Implementation Example: Comparator Comparator simple design Minimum acceptable hysteresis or offset (based on analysis) Δ/25 160mV Since offset requirement not stringent No preamp needed, basically a latch with reset Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 11 2 nd Order ΣΔ Implementation Example: Subcircuit Performance Our computed Over-Design Factor minimum required DC Gain 48dB x8 (compensates non-linear open-loop gain) Unity-gain freq =2fs=25MHz x2 Slew rate = 65V/usec x5 Output range 1.7Δ=6.8V! X0.9 Settling time constant= 30nsec x4 Comparator offset 160mV x12 Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 12
2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured SNDR M=256, 0dB=4V p-p-d f sampling : 12.8MHz Signal Frequency: 2.8kHz Note: The Nyquist ADC tests such as INL and DNL test do not apply to ΣΔ modulator type ADCS Maximum SNR @ -3dB wrt to Δ Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 13 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured Performance Summary (Does Not Include Decimator) Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 14
2 nd Order ΣΔ Implementation Example: Digital Audio Applications Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 15 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured & simulated spurious tones performance as a function of DC input signal Sampling rate=12.8mhz, M=256 Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 16
2 nd Order ΣΔ Implementation Example: Digital Audio Applications Sampling rate=12.8mhz, M=256 Measured & simulated noise tone performance for near zero DC worst case input 0.00088Δ Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 17 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured & simulated worst-case noise tone @ DC input of 0.00088Δ Both indicate maximum tone @ 22.5kHz around 00dB level Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618-627, April 1991. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 18
Higher Order ΣΔ Modulator Dynamic Range ( L + ) 2L 2π ( ) 1 1 L Y( z) = z X( z) + 1 z E( z), L ΣΔ order S S S S X Q X Q 2 Δ 2L 2 1 = sinusoidal input, STF = 1 2 2 π 1 Δ = 2L + 1 2L+ 1 M 12 32 1 2L+ 1 = M ( L + ) 2L 2π 32 1 DR = 10log M DR 2L+ 1 32 ( L + 1) = 10log 2 2L +( L ) 2π + 1 10 logm 2X increase in M (6L+3)dB or (L+0.5)-bit increase in DR EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 19 ΣΔ Modulator Dynamic Range As a Function of Modulator Order L=3 L=2 L=1 Potential stability issues for L >2 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 20
Higher Order ΣΔ Modulators Extending ΣΔ Modulators to higher orders by adding integrators in the forward path (similar to 2 nd order) Issues with stability Two different architectural approaches used to implement ΣΔ modulators of order >2 1. Cascade of lower order modulators (multi-stage) 2. Single-loop single-quantizer modulators with multi-order filtering in the forward path EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 21 Higher Order ΣΔ Modulators (1) Cascade of 2-Stages ΣΔ Modulators Main ΣΔ quantizes the signal The 1 st stage quantization error is then quantized by the 2 nd quantizer The quantized error is then subtracted from the results in the digital domain EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 22
2 nd Order (1) Cascaded ΣΔ Modulators 2 nd order noise shaping EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 23 3 rd Order Cascaded ΣΔ Modulators (a) Cascade of 1 ΣΔs Can implement 3 rd order noise shaping with 1 This is also called MASH (multi-stage noise shaping) EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 24
3rd Order Cascaded ΣΔ Modulators (b) Cascade of 2 ΣΔs Advantages of 2 cascade: Low sensitivity to precision matching of analog/digital paths Low spurious limit cycle tone levels No potential instability 3rd order noise shaping EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 25 Sensitivity of Cascade of (1) ΣΔ Modulators to Matching of Analog & Digital Paths Matching of ~ 1% 28dB loss in DR Matching of ~ 0.1% 2dB loss in DR EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 26
Sensitivity of Cascade of (2) ΣΔ Modulators to Matching Error Accuracy of < + 3% 2dB loss in DR Main advantage of 2 cascade compared to 1 topology: Low sensitivity to matching of analog/digital paths (in excess of one order of magnitude less sensitive compared to (1)!) EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 27 2 Cascaded ΣΔ Modulators Accuracy of < + 3% 2dB loss in DR Ref: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp. 193-202, March 1994. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 28
2 Cascaded ΣΔ Modulators Effect of gain parameters on signal-to-noise ratio EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 29 Comparison of 2 nd order & Cascaded (2) ΣΔ Modulator Reference Architecture Dynamic Range Peak SNDR Oversampling rate Differential input range Power Dissipation Active Area Digital Audio Application, f N =50kHz (Does not include Decimator) Brandt,JSSC 4/91 2 nd order 98dB (16-bits) 94dB 256 (theoretical SNR=109dB) 4Vppd 5V supply 13.8mW 0.39mm 2 ( 1μ tech.) Williams, JSSC 3/94 (2+1) Order 104dB (17-bits) 98dB 128 (theoretical SNR=128dB) 8Vppd 5V supply 47.2mW 5.2mm 2 ( 1μ tech.) EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 30
2 Cascaded ΣΔ Modulators Measured Dynamic Range Versus Oversampling Ratio Theoretical 21dB/Octave 3dB/Octave Ref: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp. 193-202, March 1994. EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 31 Higher Order ΣΔ Modulators (1) Cascaded Modulators Summary Cascade two or more stable ΣΔ stages Quantization error of each stage is quantized by the succeeding stage and subtracted digitally Order of noise shaping equals sum of the orders of the stages Quantization noise cancellation depends on the precision of analog/digital signal paths Quantization noise further randomized less limit cycle oscillation problems Typically, no potential instability EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 32
Higher Order ΣΔ Modulators (2) Multi-Order Filter E(z) X(z) Σ H() z Σ Y(z) H( z) 1 Y( z) = X( z) + E( z) 1 + H( z) 1 + H( z) Y( z) 1 NTF = = E( z ) 1 + H( z ) Zeros of NTF (poles of H(z)) can be strategically positioned to suppress in-band noise spectrum Approach: Design NTF first and solve for H(z) EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 33 Example: Modulator Specification Example: Audio ADC Dynamic range DR 18 Bits Signal bandwidth B 20 khz Nyquist frequency f N 44.1 khz Modulator order L 5 Oversampling ratio M = f s /f N 64 Sampling frequency f s 2.822 MHz The order L and oversampling ratio M are chosen based on SQNR > 120dB EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 34
Noise Transfer Function, NTF(z) % stop-band attenuation Rstop=80dB, L=5... L=5; Rstop = 80; B=20000; [b,a] = cheby2(l, Rstop, B, 'high'); % normalize b = b/b(1); NTF = filt(b, a,...); Chebychev 2 filter chosen zeros in stop-band NTF [db] 20 0-20 -40-60 -80 00 10 4 10 6 Frequency [Hz] EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 35 Loop-Filter Characteristics H(z) Y( z) 1 NTF = = Ez ( ) 1 + Hz ( ) 1 H( z) = 1 NFT Loopfilter H [db] 100 80 60 40 20 0-20 10 4 10 6 Frequency [Hz] EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 36
Modulator Topology Simulation Model Filter b1 b2 X I1 K1 z 1 - z I2 K2 z 1 - z I3 K3 z 1 - z I4 I5 K4 z K5 z 1 - z 1 - z a1 I_1 a2 I_2 a3 I_3 a4 I_4 a5 I_5 Q DAC Gain g Comparator Y +1 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 37 Filter Coefficients a1=1; a2=1/2; a3=1/4; a4=1/8; a5=1/8; k1=1; k2=1; k3=1/2; k4=1/4; k5=1/8; b1=1/1024; b2=1/16/64; g =1; Ref: Nav Sooch, Don Kerth, Eric Swanson, and Tetsuro Sugimoto, Phase Equalization System for a Digital-to-Analog Converter Using Separate Digital and Analog Sections, U.S. Patent 5061925, 1990, figure 3 and table 1 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 38
5 th Order Noise Shaping Simulation Results Output Spectrum [dbwn] / Int. Noise [dbfs] 40 20 0-20 -40-60 -80 00 Signal Notice tones around f s /2 20 40 Output Spectrum 60 Integrated Noise (20 averages) 0 0.1 0.2 0.3 0.4 0.5 Frequency [ f / f s ] Mostly quantization noise, except at low frequencies Let s zoom into the baseband portion EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 39 5 th Order Noise Shaping Output Spectrum [dbwn] / Int. Noise [dbfs] 40 20 0-20 -40-60 -80 00 Output Spectrum Integrated Noise (20 averaged) 20 Quantization noise 30dBFS 40 Signal @ band edge! 60 Band-Edge 0 0.2 0.4 0.6 0.8 1 Frequency [ f / f N ] SQNR > 120dB Sigma-delta modulators are usually designed for negligible quantization noise Other error sources dominate, e.g. thermal noise are allowed to dominate & thus provide dithering to eliminate limit cycle oscillations EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 40
In-Band Noise Shaping Magnitude [db] Output Phase Spectrum [degrees] 140 120 100 80 60 Loop Filter 40 0 0.2 0.4 0.6 0.8 1 400 40 300 0 200 100-40 -800 H(z) maxima align up with noise minima Output Spectrum Integrated Noise (20 averages) 00 200 0.2 0.4 0.6 0.8 1 Frequency [f/fn] 60 0 0.2 0.4 0.6 Frequency [f/f N ] 0.8 1 Lot s of gain in the loop filter pass-band Forward path filter not necessarily stable! Remember that: NTF ~ 1/H small within passband since H is large STF=H/(1+H) ~1 within passband EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 41 Internal Node Voltages Loop filter peak voltages [V] 10 5 0-5 0 5-20 i1 i2 i3 i4 i5 q Integrator outputs Quantizer input -40-35 -30-25 -20 5 0-5 0 Input [dbv] Internal signal amplitudes are weak function of input level (except near overload) Maximum peak-topeak voltage swing approach +0V! Exceed supply voltage! Solutions: Reduce V ref?? Node scaling EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 42
Node Scaling Example: 3 rd Integrator Output Voltage Scaled by α K3 * α, b1 /α, a3 / α, K4 / α, b2 * α b1 V new =V old * α b2 X K1 z 1 - z I1 I_1 K2 z 1 - z I2 K3 z 1 - z I3 I_2 I_3 K4 z K5 z 1 - z 1 - z I4 I5 I_4 I_5 a1 a2 a3 a4 a5 Q DAC Gain g Comparator Y EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 43 Node Voltage Scaling Loop filter peak voltages [V] 1.5 1 0.5 0-0.5.5-40 -35-30 -25-20 5 0-5 0 Input [dbv] Integrator output range reasonable for new parameters But: maximum input signal limited to -5dB (-7dB with safety) fix? α=1/10 k1=1/10; k2=1; k3=1/4; k4=1/4; k5=1/8; a1= 1; a2=1/2; a3=1/2; a4=1/4; a5=1/4; b1=1/512; b2=1/16/64; g =1; EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 44
Input Range Scaling Increasing the DAC levels by using higher value for g reduces the analog to digital conversion gain: D V IN ( z) H ( z) = ( z) 1+ gh ( z) g OUT 1 v IN Σ Loop Filter H(z) Comparator d OUT +1 or g Increasing v IN & g by the same factor leaves 1-Bit data unchanged EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 45 Scaled Stage 1 Model Loop filter peak voltages [V] 1.5 1 0.5 0-0.5 g modified: From 1 to 2.5; Overload input shifted up by 8dB.5-40 -35-30 -25-20 5 0-5 0 Input [dbv] EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 46
Stability Analysis e(kt) x(kt) Σ H(z) q(kt) G eff Σ y(kt) Quantizer Model Approach: linearize quantizer and use linear system theory! One way of performing stability analysis use RLocus in Matlab with H(z) as argument and Geff as variable Effective quantizer gain 2 G 2 = y eff q 2 Can obtain G eff from simulation Ref: R. W. Adams and R. Schreier, Stability Theory for ΔΣ Modulators, in Delta-Sigma Data Converters- S. Norsworthy et al. (eds), IEEE Press, 1997 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 47 G H( z) STF = 1 + G H( z) ( ) ( ) N z H z = D( z) G N( z) STF = D ( z ) + G N ( z ) Stability Analysis Zeros of STF same as zeros of H(z) Poles of STF vary with G For G=0 (no feedback) poles of the STF same as poles of H(z) For G=large, poles of STF move towards zeros of H(z) Ref: R. W. Adams and R. Schreier, Stability Theory for ΔΣ Modulators, in Delta-Sigma Data Converters- S. Norsworthy et al. (eds), IEEE Press, 1997 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 48
Modulator z-plane Root-Locus z-plane Root Locus 0.4 Increasing G eff 0.3 0.2 0.1 G eff = 4.5 As G eff increases, poles of STF move from poles of H(z) (G eff = 0) to zeros of H(z) (G eff = ) 0-0.1-0.2-0.3-0.4 Unit Circle 0.6 0.7 0.8 0.9 1 1.1 Pole-locations inside unit-circle correspond to stable STF and NTF Need G eff > 4.5 for stability EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 49 Effective Quantizer Gain, Geff Effective Quantizer Gain 8 7 6 5 4 3 2 1 G eff =4.5 stable 0-40 -35-30 -25-20 5 0-5 0 5 Input [dbv] Large inputs comparator input grows Output is fixed (±1) G eff drops modulator unstable for large inputs unstable Solution: Limit input amplitude Detect instability (long sequence of +1 or ) and reset integrators Note that signals grow slowly for nearly stable systems use long simulations EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 50
5 th Order Modulator Final Parameter Values 1/512 1/16/64 b1 b2 X Stable input range ~ ±1V 1/10 1 1/4 1/4 1/8 K1 z K2 z K3 z K4 z K5 z 1 - z 1 - z 1 - z 1 - z 1 - z I1 I2 I3 I4 I5 I_1 I_2 I_3 I_4 I_5 a11 1 a2 12 a3 1/2 a4 1/4 a5 1/4 ±2.5V DAC Gain Comparator g Stable input range ~ ±1V Q Y EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 51 Summary Oversampled ADCs decouple SQNR from circuit complexity and accuracy If a 1-Bit DAC is used, the converter is to 1st order, inherently linear independent of component matching Typically, used for high resolution & low frequency applications e.g. digital audio 2nd order ΣΔ used extensively due to lower levels of limit cycle related spurious tones compared to 1st order ΣΔ modulators of order greater than 2: Cascaded (multi-stage) modulators Single-loop, single-quantizer modulators with multi-order filtering in the forward path EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 52
Bandpass ΔΣ Modulator v IN + _ Resonator dout DAC Replace the integrator in 1 st order lowpass ΣΔ with a resonator 2 nd order bandpass ΣΔ EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 53 Bandpass ΔΣ Modulator Example: 6 th Order Measured output for a bandpass ΣΔ (prior to digital filtering) Quantization Noise Input Sinusoid Key Point: NTF notch type shape STF bandpass shape Ref: Paolo Cusinato, et. al, A 3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dB Dynamic Range, ΙΕΕΕ JSSCC, VOL. 36, NO. 4, APRIL 2001 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 54
Bandpass ΣΔ Characteristics Oversampling ratio defined as f s /2B where B = signal bandwidth Typically, sampling frequency is chosen to be f s =4xf center where f center bandpass filter center frequency STF has a bandpass shape while NTF has a notch shape To achieve same resolution as lowpass, need twice as many integrators EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 55 Bandpass ΣΔ Modulator Dynamic Range As a Function of Modulator Order (K) K=6 21dB/Octave K=4 15dB/Octave K=2 9dB/Octave Bandpass ΣΔ resolution for order K is the same as lowpass ΣΔ resolution with order L= K/2 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 56
Example: Sixth-Order Bandpass ΣΔ Modulator Simulated noise transfer function Simulated signal transfer function Ref: Paolo Cusinato, et. al, A 3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dB Dynamic Range, ΙΕΕΕ JSSCC, VOL. 36, NO. 4, APRIL 2001 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 57 Example: Sixth-Order Bandpass ΣΔ Modulator Features & Measured Performance Summary f s =4xf center B OSR=f s /2B Ref: Paolo Cusinato, et. al, A 3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dB Dynamic Range, ΙΕΕΕ JSSCC, VOL. 36, NO. 4, APRIL 2001 EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 58
Summary Oversampled ADCs Noise shaping utilized to reduce baseband quantization noise power Reduced precision requirement for analog building blocks compared to Nyquist rate converters Relaxed transition band requirements for analog anti-aliasing filters Utilizes low cost, low power digital filtering Speed is traded for resolution Typically used for lower frequency applications compared to Nyquist rate ADCs EECS 247 Lecture 27: Oversampling Data Converters 2007 H. K. Page 59