PD-9735 RADIATION HARDENED LOGIC LEVEL POWER MOSFET THRU-HOLE (4-LEAD FLAT PACK) Product Summary Part Number Radiation Level RDS(on) ID IRHLA77Z4 K Rads (Si).6Ω.8A IRHLA73Z4 3K Rads (Si).6Ω.8A 2N762M2 IRHLA77Z4 6V, Quad N-CHANNEL TECHNOLOGY 4-Lead Flat Pack International Rectifier s R7 TM Logic Level Power MOSFETs provide simple solution to interfacing CMOS and TTL control circuits to power devices in space and other radiation environments. The threshold voltage remains within acceptable operating limits over the full operating temperature and post radiation. This is achieved while maintaining single event gate rupture and single event burnout immunity. These devices are used in applications such as current boost low signal source in PWM, voltage comparator and operational amplifiers. Features: n 5V CMOS and TTL Compatible n Low RDS(on) n Fast Switching n Single Event Effect (SEE) Hardened n Low Total Gate Charge n Simple Drive Requirements n Ease of Paralleling n Hermetically Sealed n Light Weight n Complimentary P-Channel Available - IRHLA797Z4 Absolute Maximum Ratings (Per Die) Parameter Units ID @ VGS = 4.5V, TC = 25 C Continuous Drain Current.8 ID @ VGS = 4.5V, TC = C Continuous Drain Current.5 IDM Pulsed Drain Current À 3.2 PD @ TC = 25 C Max. Power Dissipation.6 W Linear Derating Factor.5 W/ C VGS Gate-to-Source Voltage ± V EAS Single Pulse Avalanche Energy Á 6 mj IAR Avalanche Current À.8 A EAR Repetitive Avalanche Energy À.6 mj dv/dt Peak Diode Recovery dv/dt Â.2 V/ns TJ Operating Junction -55 to 5 TSTG Storage Temperature Range Lead Temperature 3 (.63 in./.6 mm from case for s) C Weight.52 (Typical) g A For footnotes refer to the last page www.irf.com 3/7/8
IRHLA77Z4, 2N762M2 Electrical Characteristics For Each N-Channel Device @Tj = 25 C (Unless Otherwise specified) Parameter Min Typ Max Units Test Conditions BVDSS Drain-to-Source Breakdown Voltage 6 V VGS = V, ID = 25µA BVDSS/ TJ Temperature Coefficient of Breakdown.67 V/ C Reference to 25 C, ID =.ma Voltage RDS(on) Static Drain-to-Source On-State.6 Ω VGS = 4.5V, ID =.5A Resistance à VGS(th) Gate Threshold Voltage. 2. V VDS = VGS, ID = 25µA VGS(th)/ TJ Gate Threshold Voltage Coefficient -4.7 mv/ C gfs Forward Transconductance.23 S VDS = V, IDS =.5A à IDSS Zero Gate Voltage Drain Current. VDS= 48V,VGS= V µa VDS = 48V, VGS = V, TJ =25 C IGSS Gate-to-Source Leakage Forward VGS = V na IGSS Gate-to-Source Leakage Reverse - VGS = -V Qg Total Gate Charge 2.8 VGS = 4.5V, ID =.8A Qgs Gate-to-Source Charge.6 nc VDS = 3V Qgd Gate-to-Drain ( Miller ) Charge.6 td(on) Turn-On Delay Time 6.5 VDD = 3V, ID =.8A, tr Rise Time 2.5 ns VGS = 5.V, RG = 24Ω td(off) Turn-Off Delay Time 35 tf Fall Time 3 LS + LD Total Inductance 2 Measured from Drain lead (6mm /.25in nh from pack.) to Source lead (6mm/.25in from pack.)with Source wire internally bonded from Source pin to Drain pad Ciss Input Capacitance 4 VGS = V, VDS = 25V Coss Output Capacitance 38 pf f =.MHz Crss Reverse Transfer Capacitance.4 Rg Gate Resistance 8. Ω f =.MHz, open drain Source-Drain Diode Ratings and Characteristics (Per Die) Parameter Min Typ Max Units Test Conditions IS Continuous Source Current (Body Diode).8 ISM Pulse Source Current (Body Diode) À 3.2 A VSD Diode Forward Voltage.2 V Tj = 25 C, IS =.8A, VGS = V à trr Reverse Recovery Time 55 ns Tj = 25 C, IF =.8A, di/dt A/µs QRR Reverse Recovery Charge 63 nc VDD 25V à ton Forward Turn-On Time Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD. Thermal Resistance (Per Die) Parameter Min Typ Max Units Test Conditions RthJA Junction-to-Ambient 2 Typical socket mount C/W Note: Corresponding Spice and Saber models are available International Rectifier Website. For footnotes refer to the last page 2 www.irf.com
Radiation Characteristics IRHLA77Z4, 2N762M2 International Rectifier Radiation Hardened MOSFETs are tested to verify their radiation hardness capability. The hardness assurance program at International Rectifier is comprised of two radiation environments. Every manufacturing lot is tested for total ionizing dose (per notes 5 and 6) using the TO-39 package. Both pre- and post-irradiation performance are tested and specified using the same drive circuitry and test conditions in order to provide a direct comparison. Table. Electrical Characteristics For Each N-Channel Device @Tj = 25 C, Post Total Dose Irradiation ÄÅ Parameter Up to 3K Rads (Si) Units Test Conditions Min Max BV DSS Drain-to-Source Breakdown Voltage 6 V V GS = V, I D = 25µA VGS(th) Gate Threshold Voltage. 2. VGS = V DS, I D = 25µA I GSS Gate-to-Source Leakage Forward na V GS = V I GSS Gate-to-Source Leakage Reverse - V GS = -V I DSS Zero Gate Voltage Drain Current. µa V DS = 48V, V GS = V R DS(on) Static Drain-to-Source On-State Resistance (TO-39).6 Ω VGS = 4.5V, I D =.5A R DS(on) Static Drain-to-Source On-state Resistance (4-Lead Flat Pack).6 Ω VGS = 4.5V, I D =.5A V SD Diode Forward Voltage.2 V VGS = V, I D =.8A. Part numbers IRHLA77Z4, IRHLA73Z4 International Rectifier radiation hardened MOSFETs have been characterized in heavy ion environment for Single Event Effects (SEE). Single Event Effects characterization is illustrated in Fig. a and Table 2. Table 2. Typical Single Event Effect Safe Operating Area (Per Die) Ion LET Energy Range VDS (V) (MeV/(mg/cm 2 )) (MeV) (µm) @VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS= V -2V -4V -5V -6V -7V -8V -V Br 37 35 39 6 6 6 6 6 35 3 2 I 6 37 34 6 6 6 6 6 2 5 - Au 84 39 3 6 6 6 6 - - - - VDS 7 6 5 4 3 2 - -2-3 -4-5 -6 VGS -7-8 -9 - Br I Au For footnotes refer to the last page Fig a. Typical Single Event Effect, Safe Operating Area www.irf.com 3
R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRHLA77Z4, 2N762M2 VGS TOP V 5.V 4.5V 3.5V 3.V 2.5V 2.25V BOTTOM 2.V VGS TOP V 5.V 4.5V 3.5V 3.V 2.5V 2.25V BOTTOM 2.V. 6µs PULSE WIDTH -T j = 25 C 2.V.. V DS, Drain-to-Source Voltage (V) 2.V 6µs PULSE WIDTH Tj = 5 C.. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 2. I D =.8A I D, Drain-to-Source Current (A).. T J = 5 C T J = 25 C V DS = 25V 6µs PULSE 5 WIDTH 2 2.5 3 3.5 4.5..5 V GS = 4.5V. -6-4 -2 2 4 6 8 2 4 6 V GS, Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 4 www.irf.com
V (BR)DSS, Drain-to-Source Breakdown Voltage (V) V GS(th) Gate threshold Voltage (V) R DS (on), Drain-to -Source On Resistance ( Ω) IRHLA77Z4, 2N762M2 R DS(on), Drain-to -Source On Resistance (Ω) 3.. 2.5 I D =.8A. T J = 5 C 2..9.8.5. T J = 5 C.7.6 T J = 25 C.5 T J = 25 C.5 Vgs = 4.5V 2 3 4 5 6 7 8 9 2.4.5..5 2. 2.5 3. 3.5 V GS, Gate -to -Source Voltage (V) I D, Drain Current (A) Fig 5. Typical On-Resistance Vs Gate Voltage Fig 6. Typical On-Resistance Vs Drain Current 8 I D =.ma 3.5 3. 7 2.5 2..5 6..5 I D = 5µA I D = 25µA I D =.ma I D = 5mA 5-6 -4-2 2 4 6 8 2 4 6 T J, Temperature ( C ). -6-4 -2 2 4 6 8 2 4 6 T J, Temperature ( C ) Fig 7. Typical Drain-to-Source Breakdown Voltage Vs Temperature Fig 8. Typical Threshold Voltage Vs Temperature www.irf.com 5
I D, Drain Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRHLA77Z4, 2N762M2 28 24 2 V GS = V, f = MHz C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 2 8 I D =.8A V DS = 48V V DS = 3V V DS = 2V 6 C iss 2 C oss 6 8 4 4 C rss V DS, Drain-to-Source Voltage (V) 2 FOR TEST CIRCUIT SEE FIGURE 7.5.5 2 2.5 3 3.5 4 4.5 5 Q G, Total Gate Charge (nc) Fig 9. Typical Capacitance Vs. Drain-to-Source Voltage Fig. Typical Gate Charge Vs. Gate-to-Source Voltage.8 I SD, Reverse Drain Current (A) T J = 5 C T J = 25 C.6.4.2 V GS = V..4.6.8..2.4.6 V SD, Source-to-Drain Voltage (V) 25 5 75 25 5 T C, Case Temperature ( C) Fig. Typical Source-to-Drain Diode Forward Voltage Fig 2. Maximum Drain Current Vs. Case Temperature 6 www.irf.com
I D, Drain-to-Source Current (A) E AS, Single Pulse Avalanche Energy (mj) IRHLA77Z4, 2N762M2 4 OPERATION IN THIS AREA LIMITED BY R DS (on) 32 I D TOP.36A.5A BOTTOM.8A µs 24 6. Tc = 25 C Tj = 5 C Single Pulse ms ms V DS, Drain-to-Source Voltage (V) 8 25 5 75 25 5 Starting T J, Junction Temperature ( C) Fig 3. Maximum Safe Operating Area Fig 4. Maximum Avalanche Energy Vs. Drain Current D =.5.2 P DM Thermal Response ( Z thja ).5.2. SINGLE PULSE ( THERMAL RESPONSE ). Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc + Tc E-5.... t, Rectangular Pulse Duration (sec) t t 2 Fig 5. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 7
IRHLA77Z4, 2N762M2 V (BR)DSS 5V tp V DS L DRIVER R G 2V V GS tp. D.U.T I AS.Ω + - V DD A I AS Fig 6a. Unclamped Inductive Test Circuit Fig 6b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 4.5V Q GS Q G Q GD 2V.2µF 5KΩ.3µF D.U.T. + V - DS V G V GS 3mA Charge Fig 7a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 7b. Gate Charge Test Circuit V GS V DS R D V DS 9% R G D.U.T. + - V DD V GS Pulse Width µs Duty Factor. % % V GS t d(on) t r t d(off) t f Fig 8a. Switching Time Test Circuit Fig 8b. Switching Time Waveforms 8 www.irf.com
Footnotes: À Repetitive Rating; Pulse width limited by maximum junction temperature. Á VDD = 25V, starting TJ = 25 C, L= 5mH Peak IL =.8A, VGS = V Â ISD.8A, di/dt 23A/µs, VDD 6V, TJ 5 C IRHLA77Z4, 2N762M2 Ã Pulse width 3 µs; Duty Cycle 2% Ä Total Dose Irradiation with VGS Bias. volt VGS applied and VDS = during irradiation per MIL-STD-75, method 9, condition A. Å Total Dose Irradiation with VDS Bias. 48 volt VDS applied and VGS = during irradiation per MlL-STD-75, method 9, condition A. Case Outline and Dimensions 4-Lead FlatPack LEAD ASSIGNMENT D D4 S G Q Q4 S4 G4 NC NC G2 S2 D2 Q2 Q3 G3 S3 D3 LEGEND D = DRAIN, S = SOURCE, G = GATE, NC = NO CONNECTION CHANNELS N Channel = Q,Q2, Q3 and Q4 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) 252-75 IR LEOMINSTER : 25 Crawford St., Leominster, Massachusetts 453, USA Tel: (978) 534-5776 TAC Fax: (3) 252-793 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 3/28 www.irf.com 9