FPO Serial Input, -Bit, Quad, Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES LOW POWER: mw UNIPOLAR OR BIPOLAR OPERATION SETTLING TIME: µs to.% -BIT LINEARITY AND MONOTONICITY: C to USER SELECTABLE RESET TO MID- SCALE OR ZERO-SCALE DOUBLE-BUFFERED DATA INPUTS DESCRIPTION The is a serial input, -bit, quad, voltage output digital-to-analog converter (DAC) with guaranteed -bit monotonic performance over the C to temperature range. An asynchronous reset clears all registers to either mid-scale (8 H ) or zero-scale ( H ), selectable via the RESETSEL pin. The individual DAC inputs are double buffered to allow for APPLICATIONS PROCESS CONTROL ATE PIN ELECTRONICS CLOSED-LOOP SERVO-CONTROL MOTOR CONTROL DATA ACQUISITION SYSTEMS DAC-PER-PIN PROGRAMMERS simultaneous update of all DAC outputs. The device can be powered from a single supply or from dual and 5V supplies. Low power and small size makes the ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servocontrol. The device is available in a -pin plastic DIP or a -lead SOIC package and is guaranteed over the C to temperature range. GND V DD V REFH Input Register A DAC Register A DAC A V OUTA Serial-to- Parallel Shift Register Input Register B DAC Register B DAC B V OUTB Input Register C DAC Register C DAC C V OUTC CS DAC Select Input Register D DAC Register D DAC D V OUTD LOADREG RESETSEL RESET V REFL V SS International Airport Industrial Park Mailing Address: PO Box, Tucson, AZ 857 Street Address: 7 S. Tucson Blvd., Tucson, AZ 857 Tel: (5) 7- Twx: -5- Internet: http://www.burr-brown.com/ FAXLine: (8) 58- (US/Canada Only) Cable: BBRCORP Telex: - FAX: (5) 88-5 Immediate Product Info: (8) 58-8 Burr-Brown Corporation PDS-A Printed in U.S.A. March, 8
SPECIFICATIONS At T A = C to, V DD =, V SS = 5V, V REFH = +.5V, and V REFL =.5V, unless otherwise noted. P, U PB, UB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ACCURACY Linearity Error () V SS = V or 5V ± ± LSB () Linearity Matching () V SS = V or 5V ± ± LSB Differential Linearity Error V SS = V or 5V ± ± LSB Monotonicity Bits Zero-Scale Error Code = H ± LSB Zero-Scale Drift 5 ppm/ C Zero-Scale Matching () ± ± LSB Full-Scale Error Code = FFF H ± LSB Full-Scale Matching () ± ± LSB Zero-Scale Error Code = A H, V SS = V ±8 LSB Zero-Scale Drift V SS = V 5 ppm/ C Zero-Scale Matching () V SS = V ± ± LSB Full-Scale Error Code = FFF H, V SS = V ±8 LSB Full-Scale Matching () V SS = V ± ± LSB Power Supply Rejection ppm/v ANALOG OUTPUT Voltage Output () V SS = V or 5V V REFL V REFH V Output Current.5 +.5 ma Load Capacitance No Oscillation pf Short-Circuit Current +5, ma Short-Circuit Duration Momentary REFERENCE INPUT V REFH Input Range V SS = V or 5V V REFL +.5 +.5 V V REFL Input Range V SS = V V REFH.5 V V REFL Input Range V SS = 5V.5 V REFH.5 V DYNAMIC PERFORMANCE Settling Time (5) To ±.% 5 µs Channel-to-Channel Crosstalk Full-Scale Step. LSB On Any Other DAC, R L = kω Output Noise Voltage Bandwidth: Hz to MHz nv/ Hz DIGITAL INPUT/OUTPUT Logic Family TTL Compatible CMOS Logic Levels V IH I IH µa. V DD +. V V IL I IL µa..8 V Data Format Straight Binary POWER SUPPLY REQUIREMENTS V DD.75 5.5 V V SS If V SS V 5.5.75 V I DD.5. ma I SS.. ma Power Dissipation V SS = 5V 5 mw V SS = V 7.5 mw TEMPERATURE RANGE Specified Performance +85 C Specification same as grade to the left. NOTES: () If V SS = V, specification applies at code A H and above. () LSB means Least Significant Bit, with V REFH equal to +.5V and V REFL equal to.5v, one LSB is.mv. () All DAC outputs will match within the specified error band. () Ideal output voltage, does not take into account zero or full-scale error. (5) If V SS = 5V, full-scale step from code H to FFF H or vice-versa. If V SS = V, full-scale positive step from code H to FFF H and negative step from code FFF H to A H. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
PIN CONFIGURATION Top View V DD V OUTD V OUTC V REFL V REFH V OUTB V OUTA V SS 5 7 8 5 ABSOLUTE MAXIMUM RATINGS () RESETSEL RESET LOADREG CS GND PDIP, SOIC V DD to V SS....V to +V V DD to GND....V to +5.5V V REFL to V SS....V to (V DD V SS ) V DD to V REFH....V to (V DD V SS ) V REFH to V REFL....V to (V DD V SS ) Digital Input Voltage to GND....V to V DD +.V Maximum Junction Temperature... +5 C Operating Temperature Range... C to Storage Temperature Range... 5 C to +5 C Lead Temperature (soldering, s)... + C NOTE: () Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PIN DESCRIPTIONS PIN LABEL DESCRIPTION V DD Positive Analog Supply Voltage, nominal. V OUTD DAC D Voltage Output. V OUTC DAC C Voltage Output. V REFL Reference Input Voltage Low. Sets minimum output voltage for all DACs. 5 V REFH Reference Input Voltage High. Sets maximum output voltage for all DACs. V OUTB DAC B Voltage Output. 7 V OUTA DAC A Voltage Output. 8 V SS Negative Analog Supply Voltage, V or 5V nominal. GND Ground Serial Data Input. Serial Data Clock. CS Chip Select Input All DAC registers become transparent when is LOW. They are in the latched state when is HIGH. LOADREG The selected Input Register becomes transparent when LOADREG is LOW. It is in the latched state when LOADREG is HIGH. 5 RESET Asynchronous Reset Input. Sets DAC and input registers to either zero-scale ( H ) or mid-scale (8 H ) when LOW. RESETSEL determines which code is active. RESETSEL When LOW, a LOW on RESET will cause the DAC and input registers to be set to code H. When RESETSEL is HIGH, a LOW on RESET will set the registers to code 8 H. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MAXIMUM MAXIMUM DIFFERENTIAL SPECIFICATION PACKAGE LINEARITY LINEARITY TEMPERATURE DRAWING MODEL ERROR (LSB) ERROR (LSB) RANGE PACKAGE NUMBER () P ± ± C to -Pin Plastic DIP 8 U ± ± C to -Lead SOIC PB ± ± C to -Pin Plastic DIP 8 UB ± ± C to -Lead SOIC NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
TYPICAL PERFORMANCE CURVES: V SS = V At T A = +5 C, V DD =, V SS = V, V REFH = +.5V, and V REFL = V, representative unit, unless otherwise specified. DIFFERENTIAL (DAC A) DIFFERENTIAL (DAC B) DIFFERENTIAL (DAC C) DIFFERENTIAL (DAC D) C (DAC A, C and ) C (DAC B, C and )
TYPICAL PERFORMANCE CURVES: V SS = V (CONT) At T A = +5 C, V DD =, V SS = V, V REFH = +.5V, and V REFL = V, representative unit, unless otherwise specified. C (DAC C, C and ) C (DAC D, C and ) A: Output Voltage (V) POSITIVE SLEW RATE and SETTLING TIME.75.5 5V.75 V B.5 A.75 5 7 8 Time (µs) B: Output Voltage, D from +.5V (LSB) A: Output Voltage (V) NEGATIVE SLEW RATE and SETTLING TIME.75.5.75 A B.5 5V.75 V 5 7 8 Time (µs) B: Output Voltage, D from Code A H (LSB) 5
TYPICAL PERFORMANCE CURVES: V SS = 5V At T A = +5 C, V DD =, V SS = 5V, V REFH = +.5V, and V REFL =.5V, representative unit, unless otherwise specified. DIFFERENTIAL (DAC A) DIFFERENTIAL (DAC B) DIFFERENTIAL (DAC C) DIFFERENTIAL (DAC D) C (DAC A, C and ) C (DAC B, C and )
TYPICAL PERFORMANCE CURVES: V SS = 5V (CONT) At T A = +5 C, V DD =, V SS = 5V, V REFH = +.5V, and V REFL =.5V, representative unit, unless otherwise specified. C (DAC C, C and ) +85 C C (DAC D, C and +85 C) A: Output Voltage (V) POSITIVE SLEW RATE and SETTLING TIME 5V V A B 5 7 8 Time (µs) B: Output Voltage, D from +.5V (LSB) A: Output Voltage (V) NEGATIVE SLEW RATE and SETTLING TIME A B 5V V 5 7 8 Time (µs) B: Output Voltage, D from.5v (LSB) V REFH CURRENT vs CODE (All DACs Set to Indicated Code) V REFL CURRENT vs CODE (All DACs Set to Indicated Code) 5 V REH Current (µa) V REL Current (µa) 5 H H 8 H C H FFF H H H 8 H C H FFF H 7
THEORY OF OPERATION The is a serial input, -bit, quad, voltage output digital-to-analog converter (DAC). The architecture is a classic R-R ladder configuration followed by an operational amplifier that serves as a buffer. Each DAC has its own R-R ladder network and output op amp, but all share the reference voltage inputs. The minimum voltage output ( zero-scale ) and maximum voltage output ( full-scale ) are set by external voltage references (V REFL and V REFH, respectively). The digital input is a -bit serial word that contains the -bit DAC code and a -bit address code that selects one of the four DACs (the two remaining bits are unused). The converter can be powered from a single supply or a dual ±5V supply. Each device offers a reset function which immediately sets all DAC output voltages and internal registers to either zeroscale (code H ) or mid-scale (code 8 H ). The reset code is selected by the state of the RESETSEL pin (LOW = H, HIGH = 8 H ). See Figures and for the basic operation of the. ANALOG OUTPUTS When V SS = 5V (dual supply operation), the output amplifier can swing to within.5v of the supply rails, guaranteed over the C to temperature range. With V SS = V (single-supply operation), the output can swing to ground. Note that the settling time of the output op amp will be longer with voltages very near ground. Also, care must be taken when measuring the zero-scale error when V SS = V. If the output amplifier has a negative offset, the output voltage may not change for the first few digital input codes ( H, H, H, etc.) since the output voltage cannot swing below ground. The behavior of the output amplifier can be critical in some applications. Under short-circuit conditions (DAC output shorted to ground), the output amplifier can sink a great deal more current than it can source. See the Specifications Table for more details concerning short circuit current. + µf to µf.µf V DD RESETSEL V to +.5V V to +.5V +.5V.µF 5 V OUTD V OUTC V REFL V REFH RESET LOADREG CS 5 Reset DACs () Update Selected Register Update All DAC Registers Chip Select V to +.5V V to +.5V 7 8 V OUTB V OUTA V SS GND Clock Serial Data In NOTE: () As configured, RESET LOW sets all internal registers to code H (V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 8 H (.5V). FIGURE. Basic Single-Supply Operation of the. + µf to µf.µf V DD RESETSEL.5V to +.5V V OUTD RESET 5 Reset DACs ().5V to +.5V V OUTC LOADREG Update Selected Register.5V +.5V.µF.µF 5 V REFL V REFH V OUTB CS Update All DAC Registers Chip Select Clock.5V to +.5V.5V to +.5V 7 8 V OUTA V SS GND Serial Data In 5V + µf to µf.µf NOTE: () As configured, RESET LOW sets all internal registers to code 8 H (V). If RESETSEL is LOW, RESET LOW sets all internal registers to code H (.5V). FIGURE. Basic Dual-Supply Operation of the. 8
REFERENCE INPUTS The reference inputs, V REFL and V REFH, can be any voltage between V SS +.5V and V DD.5V provided that V REFH is at least.5v greater than V REFL. The minimum output of each DAC is equal to V REFL LSB plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to V REFH plus a similar offset voltage. Note that V SS (the negative power supply) must either be connected to ground or must be in the range of.75v to 5.5V. The voltage on V SS sets several bias points within the converter. If V SS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. The current into the reference inputs depends on the DAC output voltages and can vary from a few microamps to approximately. milliamp. Bypassing the reference voltage or voltages with a.µf capacitor placed as close to the package is strongly recommended. DIGITAL INTERFACE Figure and Table I provide the basic timing for the. The interface consists of a serial clock (), serial data (), a load register signal (LOADREG), and a load all DAC registers signal (). In addition, a chip select (CS) input is available to enable serial communication when there are multiple serial devices. An asyn- SYMBOL DESCRIPTION MIN TYP MAX UNITS t DS Data Valid to Rising 5 ns t DH Data Held Valid after Rises ns t CH HIGH ns t CL LOW 5 ns t CSS CS LOW to Rising 55 ns t CSH HIGH to CS Rising 5 ns t LD LOADREG HIGH to Rising ns t LD Rising to LOADREG LOW 5 ns t LDRW LOADREG LOW Time 5 ns t LDDW LOW Time 5 ns t RSSH RESETSEL Valid to RESET LOW 5 ns t RSTW RESET LOW Time 7 ns t S Settling Time µs TABLE I. Timing Specifications (T A = C to ). chronous reset input (RESET) is provided to simplify startup conditions, periodic resets, or emergency resets to a known state. The DAC code and address are provided via a -bit serial interface as shown in Figure. The first two bits select the input register that will be updated when LOADREG goes LOW (see Table II). The next two bits are not used. The last -bits are the DAC code which is provided, most significant bit first. A (MSB) (LSB) A X X D D D D D D D t css t CSH CS t LD t LD LOADREG t LDRW t DS t DH t CL t CH t LDDW V OUT t S LSB ERROR BAND t S LSB ERROR BAND t RSTW RESET t RSSH RESETSEL FIGURE. Timing.
STATE OF SELECTED SELECTED STATE OF INPUT INPUT ALL DAC A A LOADREG RESET REGISTER REGISTER REGISTERS L () L L H () H A Transparent Latched L H L H H B Transparent Latched H L L H H C Transparent Latched H H L H H D Transparent Latched X () X H L H NONE (All Latched) Transparent X X H H H NONE (All Latched) Latched X X X X L ALL Reset () Reset () NOTES: () L = Logic LOW. () H = Logic HIGH. () X = Don t Care. () Resets to either H or 8 H, per the RESETSEL state (LOW = H, HIGH = 8 H ). When RESET rises, all registers that are in their latched state retain the reset value. TABLE II. Control Logic Truth Table. CS () () LOADREG RESET SERIAL SHIFT REGISTER H () X () H H No Change L () L H H No Change L (5) H H Advanced One Bit L H H Advanced One Bit H () X L (7) H No Change H () X H L (8) No Change NOTES: () CS and are interchangeable. () H = Logic HIGH. () X = Don t Care. () L = Logic LOW (5) = Positive Logic Transition. () A HIGH value is suggested in order to avoid a false clock from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOADREG is LOW, the selected Input Register will change as the shift register bits flow through A and A. This will corrupt the data in each Input Register that has been erroneously selected. (8) RESET LOW causes no change in the contents of the serial shift register. TABLE III. Serial Shift Register Truth Table. Note that CS and are combined with an OR gate and the output controls the serial-to-parallel shift register internal to the (see the block diagram on the front of this data sheet). These two inputs are completely interchangeable. In addition, care must be taken with the state of when CS rises at the end of a serial transfer. If is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong input register. If both CS and are used, then CS should rise only when is HIGH. If not, then either CS or can be used to operate the shift register. See Table III for more information. The digital data into the is double-buffered. This allows new data to be entered for each DAC without disturbing the analog outputs. When the new settings have been entered into the device, all of the DAC outputs can be updated simultaneously. The transfer from the input registers to the DAC registers is accomplished with a HIGH to LOW transition on the input. Because the DAC registers become transparent when is LOW, it is possible to keep this pin LOW and update each DAC via LOADREG. However, as each new data word is entered into the device, the corresponding output will update immediately when LOADREG is taken LOW. Digital Input Coding The input data is in Straight Binary format. The output voltage is given by the following equation: (V REFH V REFL ) N V OUT = V REFL + where N is the digital input code (in decimal). This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors.
LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As the offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance from the converter. Because the has a single ground pin, all return currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system (see Figure ). The power applied to V DD (as well as V SS, if not grounded) should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, V DD should be connected to a power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the µf to µf and.µf capacitors shown in Figure are strongly recommended. In some situations, additional bypassing may be required, such as a µf electrolytic capacitor or even a Pi filter made up of inductors and capacitors all designed to essentially lowpass filter the supply, removing the high frequency noise (see Figure ). Digital Circuits Power Supply Ground Ground µf + + µf to µf.µf V DD GND Optional Other Analog Components FIGURE. Suggested Power and Ground Connections for a Sharing a Supply with a Digital System.