SMPS MOSFET HEXFET Power MOSFET Applications Reset Switch for Active Clamp Reset DC-DC converters V DSS R DS(on) (max) I D - 150V 150m @ V GS = -V -27A Benefits Low Gate to Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design (See App. Note AN1) Fully Characterized Avalanche Voltage and Current Lead-Free D S G D2 Pak G D S Gate Drain Source Base part number Package Type D2-Pak Standard Pack Form Quantity Orderable Part Number Tube 50 Tape and Reel Left 800 IRF6218STRLPbF Absolute Maximum Ratings Symbol Parameter Max. Units V DS Drain-to-Source Voltage -150 V GS Gate-to-Source Voltage ± 20 V I D @ T C = 25 C Continuous Drain Current, V GS @ V - 27 I D @ T C = C Continuous Drain Current, V GS @ V -19 A I DM Pulsed Drain Current - 1 P D @T C = 25 C Maximum Power Dissipation 250 W Linear Derating Factor 1.6 W/ C dv/dt Peak Diode Recovery dv/dt 8.2 V/ns T J Operating Junction and -55 to + 175 T STG Storage Temperature Range C Soldering Temperature, for seconds (1.6mm from case) 300 Thermal Resistance Symbol Parameter Typ. Max. Units R JC Junction-to-Case 0.61 R JA Junction-to-Ambient ( PCB Mount, steady state) 40 C/W Notes through are on page 2 1 2016-5-26
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage -150 V V GS = 0V, I D = -250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient -0.17 V/ C Reference to 25 C, I D = -1mA R DS(on) Static Drain-to-Source On-Resistance 120 150 m V GS = -V, I D = -16A V GS(th) Gate Threshold Voltage -3.0-5.0 V V DS = V GS, I D = -250µA I DSS Drain-to-Source Leakage Current -25 V µa DS = -120V, V GS = 0V -250 V DS = -120V,V GS = 0V,T J = 150 C Gate-to-Source Forward Leakage - V I GSS na GS = -20V Gate-to-Source Reverse Leakage V GS = 20V Dynamic @ T J = 25 C (unless otherwise specified) gfs Forward Trans conductance 11 S V DS = -50V, I D = -16A Q g Total Gate Charge 71 1 I D = -16A Q gs Gate-to-Source Charge 21 nc V DS = -120V Q gd Gate-to-Drain ( Miller ) Charge 32 V GS = -V t d(on) Turn-On Delay Time 21 V DD = -75V t r Rise Time 70 I D = -16A ns t d(off) Turn-Off Delay Time 35 R G = 3.9 t f Fall Time 30 V GS = -V C iss Input Capacitance 22 V GS = 0V C oss Output Capacitance 370 V DS = -25V C rss Reverse Transfer Capacitance 89 ƒ = 1.0MHz pf C oss Output Capacitance 2220 V GS = 0V, V DS = -1.0V, ƒ = 1.0MHz C oss Output Capacitance 170 V GS = 0V, V DS = -120V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 340 V GS = 0V, V DS = 0V to -120V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 2 mj I AR Avalanche Current -16 A Diode Characteristics Parameter Min. Typ. Max. Units Conditions Continuous Source Current MOSFET symbol I S -27 (Body Diode) showing the A Pulsed Source Current integral reverse I SM -1 (Body Diode) p-n junction diode. V SD Diode Forward Voltage -1.6 V T J = 25 C,I S = -16A,V GS = 0V t rr Reverse Recovery Time 150 ns T J = 25 C,I F = -16A, V DD = -25V Q rr Reverse Recovery Charge 860 nc di/dt = A/µs Notes: Repetitive rating; pulse width limited by max. junction temperature. starting T J = 25 C, L = 1.6mH, R G = 25, I AS = -17A I SD -17A, di/dt -520A/µs, V DD V (BR)DSS, T J 175 C. Pulse width 300µs; duty cycle 2%. R is measured at T J of approximately 90 C. When mounted on 1" square PCB ( FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #AN-994. 2 2016-5-26
-I D, Drain-to-Source Current ) (Normalized) -I D, Drain-to-Source Current (A) -I D, Drain-to-Source Current (A) 0 VGS TOP -15V -V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V 0 VGS TOP -15V -V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V 1 0.1-4.5V 60µs PULSE WIDTH Tj = 25 C 0.01 0.1 1 -V DS, Drain-to-Source Voltage (V) 1-4.5V 60µs PULSE WIDTH Tj = 175 C 0.1 0.1 1 -V DS, Drain-to-Source Voltage (V) Fig. 1 Typical Output Characteristics Fig. 2 Typical Output Characteristics T J = 25 C T J = 175 C R DS(on), Drain-to-Source On Resistance 2.5 I D = -27A V GS = -V 2.0 1.5 1.0 1.0 V DS = 50V 60µs PULSE WIDTH 2 4 6 8 12 -V GS, Gate-to-Source Voltage (V) 0.5-60 -40-20 0 20 40 60 80 120 140 160 180 T J, Junction Temperature ( C) Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance vs. Temperature 3 2016-5-26
-I SD, Reverse Drain Current (A) -I D, Drain-to-Source Current (A) C, Capacitance(pF) -V GS, Gate-to-Source Voltage (V) 000 00 V GS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 12.0.0 I D = -16A V DS = 120V V DS = 75V V DS = 30V 8.0 C iss 0 6.0 C oss 4.0 C rss 2.0 1 0.0 0 20 30 40 50 60 70 80 -V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 0.00 0 OPERATION IN THIS AREA LIMITED BY R DS (on).00 T J = 175 C.00 T J = 25 C 1.00 V GS = 0V 0. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -V SD, Source-to-Drain Voltage (V) 1 Tc = 25 C Tj = 175 C Single Pulse µsec 1msec msec 1 0 -V DS, Drain-to-Source Voltage (V) Fig. 7 Typical Source-to-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 2016-5-26
-I D, Drain Current (A) 30 25 20 15 Fig a. Switching Time Test Circuit 5 0 25 50 75 125 150 175 T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig b. Switching Time Waveforms 1 D = 0.50 0.1 0.20 0. Thermal Response ( Z thjc ) 0.01 0.001 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) J J 1 1 2 2 3 3 Ci= i Ri Ci= i Ri R 1 R 2 R 3 R 1 R 2 R 3 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t 1, Rectangular Pulse Duration (sec) C C Ri ( C/W) i (sec) 0.264 0.000285 0.206 0.001867 0.140 0.013518 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 2016-5-26
R DS (on), Drain-to-Source On Resistance (m ) 400 350 R DS(on), Drain-to -Source On Resistance (m ) 0 900 800 300 250 V GS = -V 700 600 500 I D = -27A 400 200 300 150 200 0 20 40 60 80 0 4 5 6 7 8 9 11 12 -I D, Drain Current (A) -V GS, Gate -to -Source Voltage (V) Fig 12. On-Resistance vs. Drain Current Fig 13. On-Resistance vs. Gate Voltage E AS, Single Pulse Avalanche Energy (mj) 900 800 700 600 I D TOP -4.6A -6.3A BOTTOM -16A Fig 14a&b. Basic Gate Charge Test Circuit and Waveform 500 400 300 200 0 25 50 75 125 150 175 Starting T J, Junction Temperature ( C) Fig 15c. Maximum Avalanche Energy vs. Drain Current Fig 15a&b. Unclamped Inductive Test circuit and Waveforms 6 2016-5-26
D2-Pak (TO-263AB) Package Outline (Dimensions are shown in millimeters (inches)) D2-Pak (TO-263AB) Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE P = DESIGNATES LEAD - FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE Note: For the most current drawing please refer to Infineon s web site www.infineon.com 7 2016-5-26
D2-Pak (TO-263AB) Tape & Reel Information (Dimensions are shown in millimeters (inches)) TRR 1.60 (.063) 1.50 (.059) 4. (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941).90 (.429).70 (.421) 16. (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Note: For the most current drawing please refer to Infineon s web site www.infineon.com 8 2016-5-26
Qualification Information Qualification Level Moisture Sensitivity Level RoHS Compliant D2-Pak Industrial (per JEDEC JESD47F) MSL1 (per JEDEC J-STD-020D) Yes Qualification standards can be found at Infineon s web site www.infineon.com Applicable version of JEDEC standard at the time of product release. Revision History Date 3/25/2015 5/26/2016 Comments Updated datasheet based on IR corporate template. Updated package outline and part marking on page 7. Removed TO-262 Pak (IRF6218LPbF) from datasheet-all pages Updated datasheet with corporate template. Added disclaimer on last page. Trademarks of Infineon Technologies AG µhvic, µipm, µpfc, AU ConvertIR, AURIX, C166, CanPAK, CIPOS, CIPURSE, CoolDP, CoolGaN, COOLiR, CoolMOS, CoolSET, CoolSiC, DAVE, DI POL, DirectFET, DrBlade, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, eupec, FCOS, GaNpowIR, HEXFET, HITFET, HybridPACK, imotion, IRAM, ISOFACE, IsoPACK, LEDrivIR, LITIX, MIPAQ, ModSTACK, my d, NovalithIC, OPTIGA, Op MOS, ORIGA, PowIRaudio, PowIRStage, PrimePACK, PrimeSTACK, PROFET, PRO SIL, RASIC, REAL3, SmartLEWIS, SOLID FLASH, SPOC, StrongIRFET, SupIRBuck, TEMPFET, TRENCHSTOP, TriCore, UHVIC, XHP, XMC Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respec ve owners. Edi on 2016 04 19 Published by Infineon Technologies AG 81726 Munich, Germany 2016 Infineon Technologies AG. All Rights Reserved. Do you have a ques on about this document? Email: erratum@infineon.com Document reference ifx1 IMPORTANT NOTICE The informa on given in this document shall in no event be regarded as a guarantee of condi ons or characteris cs ( Beschaffenheitsgaran e ). With respect to any examples, hints or any typical values stated herein and/or any informa on regarding the applica on of the product, Infineon Technologies hereby disclaims any and all warran es and liabili es of any kind, including without limita on warran es of non infringement of intellectual property rights of any third party. In addi on, any informa on given in this document is subject to customer s compliance with its obliga ons stated in this document and any applicable legal requirements, norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applica ons. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended applica on and the completeness of the product informa on given in this document with respect to such applica on. For further informa on on the product, technology, delivery terms and condi ons and prices please contact your nearest Infineon Technologies office (www.infineon.com). Please note that this product is not qualified according to the AEC Q or AEC Q1 documents of the Automo ve Electronics Council. WARNINGS Due to technical requirements products may contain dangerous substances. For informa on on the types in ques on please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a wri en document signed by authorized representa ves of Infineon Technologies, Infineon Technologies products may not be used in any applica ons where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 9 2016-5-26