Scalable Front-End Digital Signal Processing for a Phased Array Radar Demonstrator. International Radar Symposium 2012 Warsaw, 24 May 2012

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Transcription:

Scalable Front-End Digital Signal Processing for a Phased Array Radar Demonstrator F. Winterstein, G. Sessler, M. Montagna, M. Mendijur, G. Dauron, PM. Besso International Radar Symposium 2012 Warsaw, 24 May 2012

Background of the SSA activity Context ESA Space Situational Awareness (SSA) initiative Objective of the SSA initiative Support of the European independent utilisation of and access to space 3 segments Space weather events Near-Earth Objects: Potential asteroid impact hazards Space Surveillance and Tracking: Objects orbiting the Earth Impact on Hubble solar panel Source: http://www.esa.int/ssa

SSA Radar Element Managed by ESA and contracted to Industry Timeframe 2010-2012 2013-2020 System Detection design goal Phased array radar demonstrator ~ large objects Radar to catalogue objects in low-earth orbit ~5-10cm objects at 800 km altitude ESA internal development Independent experimental system in support of SSA Radar Element Mini-Radar demonstrator Not designed for space surveillance but for nearby objects

Outline of presentation Space surveillance for ESA s SSA preparatory programme Mini-Radar system architecture FPGA signal processing architecture Synthesis results System tests Summary and outlook

Mini-Radar System Architecture TX RX 16-Patch Antenna Array High-power RF signals 16 Analog Front-end and Phase Shifters 16-Patch Antenna Array 16 Analog Front-end RF signals 16 fully parallel TX/RX chains

Mini-Radar System Architecture High-power RF signals Low-power RF signals TX 16-Patch Antenna Array 16 Analog Front-end and Phase Shifters 16 Divider 1 Arbitrary Waveform Generator Synchronization / Control 16-Patch Antenna Array 16 Analog Front-end 16 16 FPGA RX A/D Converter N Host Computer RF signals IF signals Digitized IF samples Beam samples Waveform flexibility: CW or pulsed LFM Large-scale phased array radar: Distributed processing nodes Computational burden for a single node? Scope of this work: Estimation of computational complexity wrt. FPGA utilization

Outline of presentation Space surveillance for ESA s SSA preparatory programme Mini-Radar system architecture FPGA signal processing architecture Synthesis results System tests Summary and outlook

FPGA Signal Processing Architecture FPGA A/D 1 A/D 2 A/D 16 DC I/Q-Demodulation Filtering CIC, Integrator, FIR Doppler Process / Pulse Compress FFT, Weighting, IFFT DC I/Q-Demodulation Filtering CIC, Integrator, FIR, Doppler Process / Pulse Compress FFT, Weighting, IFFT, Beamforming Channel Equalization, (u/v)-to-weight Transformation, Formation of N Beams Host Computer Input Synchronization N, Direct Memory Access Interface N, Detection and Post-Processing DC I/Q-Demodulation,,, Filtering CIC, Integrator, FIR,, Doppler Process / Pulse Compress FFT, Weighting, IFFT,, 50 MHz Domain 200 MHz Domain Simultaneous sampling of 16 RX channels Digital down-conversion to complex baseband Low-pass filtering, highpass filtering, integration FFT processing (CW) / Pulse compression (LFM) Channel equalization / Digital beamforming Transfer to host PC FPGA Implementation: Hardware-folding 4-to-1 to save FPGA resources

FPGA Output Data Cube CW LFM

Outline of presentation Space surveillance for ESA s SSA preparatory programme Mini-Radar system architecture FPGA signal processing architecture Synthesis results System tests Summary and outlook

Resource utilization (%) Resource utilization (%) Resource utilization (%) Resource utilization (%) Scaling number of RX channels and bandwidth 100 80 60 CW, 97.7 khz bandwidth, 256 beams REG LUT BRAM DSP 100 80 60 REG LUT BRAM DSP CW, 16 channels, 256 beams 40 40 20 20 0 0 4 8 12 16 20 24 28 32 Parallel RX channels 100 80 60 40 20 LFM, 6.4 MHz bandwidth, 256 beams REG LUT BRAM DSP 0 0 4 8 12 16 20 24 28 32 Parallel RX channels 0 0 0.1 0.2 0.3 0.4 Bandwidth (MHz) 100 80 60 40 20 LFM, 16 channels, 256 beams REG LUT BRAM DSP 0 0 4 8 12 16 20 24 Bandwidth (MHz)

Outline of presentation Space surveillance for ESA s SSA preparatory programme Mini-Radar system architecture FPGA signal processing architecture Synthesis results System tests Summary and outlook

Angle of arrival (deg) Angle of arrival (deg) Radar Measurements Close mono-static setup CW radar end-to-end test Direction finding Doppler RX TX Beam-former output for scan in azimuth 80 60 40 20 0-20 -40-60 -80 0 5 10 15 20 Time (s) Beam-former output for scan in elevation 80 60 40 20 0-20 -40-60 -80 0 5 10 15 20 Time (s)

Radial velocity (km/h) Radar Measurements Close mono-static setup CW radar end-to-end test Direction finding Doppler RX TX 20 10 0-10 -20 0 5 10 15 20 Time (s)

Outline of presentation Space surveillance for ESA s SSA preparatory programme Mini-Radar system architecture FPGA signal processing architecture Synthesis results System tests Summary and outlook

Summary and Outlook Mini-Radar to serve as an experimental reference system Full radar development from scratch Flexible FPGA signal processing implementation Waveform flexibility Scalable in number of channels, bandwidth, number of beams, and processing throughput Estimation of computational complexity of the receiver signal processor in terms of FPGA resource consumption System tests to validate the Mini-Radar system Future activities: Further signal processing techniques (such as pulse-topulse-processing)

Thank you for your attention!

Annex

Distribution (%) Comparison GOPS DSP Slices 60 50 GOPS DSP resources utilization 40 30 20 10 0 Down-converter Filtering Doppler Processing Beam-former Others

SNR (db) SNR (db) Processing Gain Measurements CW 100 80 60 CW application processing gain 59 db Theoretical value Measured value 40 20 0 A/D out DC CIC Integr. FIR FFT Beamf. 100 80 LFM application processing gain Theoretical value Measured value LFM 60 43 db 40 20 0 A/D out DC FIR Pulse com. Beamf.

Mini-Radar link budget System properties Transmit power 40.0 dbm Required SNR 20.0 db Target properties Target RCS (metallic sphere with 0.5m radius) -1.1 dbm² Antenna properties Transmit antenna gain (phased array antenna) 16.0 dbi Receive antenna gain (single element) Receiver noise Receiver noise temperature at 1 st LNA input (290K physical temperature) Analog front-end noise bandwidth System losses Receiver cable and additional losses (due to implementation imperfections) Receiver processing gain Required signal power at 1 st LNA input Reference range Receiver processing gain Required signal power at 1 st LNA input Reference range CW Operation LFM Operation 6.0 dbi 170.4 K 8.8 MHz 2.6 db 59 db -145.7 dbm 9063 m 43 db -130.3 dbm 3742 m

Execution time time (ms) (ms) Scaling throughput 25 15.7 GOPS 20 15 10 5 46.7 GOPS 7.4 ms 0 40 50 60 70 80 90 100 FPGA DSP slice utilization (%) 16 RX channels, 6.4 MHz bandwidth (LFM), 256 beams

Frequency choice & licence for Mini-Radar Measurement of interferers within radar band to find a good frequency for the Mini-Radar Frequency licence for Mini-Radar: 1300-1320 MHz

Mini-Radar system design: Receiver Receiver block diagram Configuration 16-Patch Antenna Array RF signals Analogue Front-end IF signals A/D Converter Digitised IF samples FPGA Beam samples / Channel samples HOST Computer

Mini-Radar system design: Receiver Receiver block diagram Configuration 16-Patch Antenna Array RF signals Analogue Front-end IF signals A/D Converter Digitised IF samples FPGA Beam samples / Channel samples HOST Computer From antenna RF Cable RF Amplifier RF Filter Mixer IF Filter IF: 20 MHz IF Amplifier IF Cable Chain 1 Chain n Chain 16 To A/D converter Signal Generator Amplifier 16-Way-Splitter LO Cables Single receiver chain

Mini-Radar system design: Receiver Receiver block diagram Configuration 16-Patch Antenna Array RF signals Analogue Front-end IF signals A/D Converter Digitised IF samples FPGA Beam samples / Channel samples HOST Computer

Mini-Radar system design: Receiver Receiver block diagram Configuration 16-Patch Antenna Array RF signals Analogue Front-end IF signals A/D Converter Digitised IF samples FPGA Beam samples / Channel samples HOST Computer

Mini-Radar system design: Transmitter Transmitter design (signal generator) TX control from Receiver R&S Signal Generator Divider 16 Phase Shifter / 16 Power Amplifier Low-power RF signals High-power RF signals 16-Patch Antenna Array Arbitrary waveform generator

Mini-Radar system design: Transmitter Transmitter design (phase shifter / power amplifier) TX control from Receiver R&S Signal Generator Divider 16 Phase Shifter / 16 Power Amplifier Low-power RF signals High-power RF signals 16-Patch Antenna Array 16 parallel modules Digitally-controlled phase shifter (360, 6 bit) Power amplifier (1 Watt output, 30 db gain) Output low-pass filter Design and manufacturing by external supplier RF input Chain 1 Chain 2 Chain 16 Phase Shifter φ 6 Latch RF Amplifier RF Filter To antenna Becker Nachrichtentechnik GmbH

Mini-Radar system design: Transmitter Transmitter design (antenna) TX control from Receiver R&S Signal Generator Divider 16 Phase Shifter / 16 Power Amplifier Low-power RF signals High-power RF signals 16-Patch Antenna Array 16 element patch antenna array Dual polarization (horizontal + vertical) Same design as receive antenna

Mini-Radar project Mini-Radar project Develop a small-scale radar demonstrator Support industrial SSA radar developments Build up internal experience SSA radar system building blocks Antenna design RX/TX frontend hardware System calibration Space debris cataloguing Link budget Radar waveforms Beamforming Orbit determination Frequency choice / allocation Signal processing Range / Velocity / Angle estimation Detection algorithms Covered by Mini-Radar project

Mini-Radar direction finding Measurement setup: Direction finding radar target Radar measurement setup: Phased array receiver Determine direction of reflected signal via beam-forming MTI filter for clutter suppression 15 30 45 0-15 -30-45 -> Validate receiver beam-forming Transmitter Receiver

Beam power [db] Angle [deg] Beam power [db] Mini-Radar beam-forming measurements Receiver beam-forming: Beam-forming angle versus angle of actual signal direction. Red: high signal power 0 Blue: low signal power Black line: expected maximum value -10 40 Cut at 0-20 20 0-30 -40-20 0 20 40 Angle [deg] 0-20 -40-40 -20 0 20 40 Actual angle [deg] Cut at -20-10 -20-30 -40-20 0 20 40 Angle [deg]

Angle of arrival (deg) Angle of arrival (deg) Radar Measurements Close mono-static setup 20 deg CW radar end-to-end test Direction finding Doppler TX 10 deg RX Beam-former output for scan in azimuth 80 60 40 20 0-20 -40-60 -80 0 1 2 3 Time (s) Beam-former output for scan in elevation 80 60 40 20 0-20 -40-60 -80 0 1 2 3 Time (s)

Radar Measurements Radial velocity (km/h) Close mono-static setup 20 deg CW radar end-to-end test Direction finding Doppler TX 10 deg RX 50 25 0-25 -50 0 1 2 3 Time (s)