AN Programming the PCA200x family of watch ICs. Document information

Similar documents
R_ Driving LPC1500 with EPSON Crystals. Rev October Document information. Keywords Abstract

AN NHS3xxx Temperature sensor calibration. Document information

TED-Kit 2, Release Notes

UM Slim proximity touch sensor demo board OM Document information

AN Energy Harvesting with the NTAG I²C and NTAG I²C plus. Application note COMPANY PUBLIC. Rev February Document information

AN MIFARE Plus Card Coil Design. Application note COMPANY PUBLIC. Rev April Document information

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

AN Maximum RF Input Power BGU6101. Document information. Keywords Abstract

UM OM29263ADK Quick start guide antenna kit COMPANY PUBLIC. Document information

AN12232 QN908x ADC Application Note

TN LPC1800, LPC4300, MxMEMMAP, memory map. Document information

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

AN High-performance PCB antennas for ZigBee networks. Document information. Keywords

AN NTAG21xF, Field detection and sleep mode feature. Rev July Application note COMPANY PUBLIC. Document information

UM DALI getting started guide. Document information

AN PR533 USB stick - Evaluation board. Application note COMPANY PUBLIC. Rev May Document information

UM User manual for di2c demo board. Document information

AN11994 QN908x BLE Antenna Design Guide

AN TEA1892 GreenChip synchronous rectifier controller. Document information

OM29110 NFC's SBC Interface Boards User Manual. Rev May

PTN5100 PCB layout guidelines

AN12165 QN908x RF Evaluation Test Guide

AN NFC, PN533, demo board. Application note COMPANY PUBLIC. Rev July Document information

UM DALI getting started guide. Document information

PN7120 NFC Controller SBC Kit User Manual

ES_LPC1114. Errata sheet LPC1114. Document information

AN Ohm FM LNA for embedded Antenna in Portable applications with BGU7003W. Document information. Keywords Abstract

UM10950 Start-up Guide for FRDM-KW41Z Evaluation Board Bluetooth Paring example with NTAG I²C plus Rev February

UM GreenChip TEA1995DB1295 synchronous rectifier controller demo board. Document information

AN UBA2015/UBA2017 saturating inductor support during ignition. Document information

AN Replacing HMC625 by NXP BGA7204. Document information

AN PN7150X Frequently Asked Questions. Application note COMPANY PUBLIC. Rev June Document information

UM TEA1721 universal mains white goods flyback SMPS demo board. Document information

UM Description of the TDA8029 I2C Demo Board. Document information

BGU8007/BGU7005 Matching Options for Improved LTE Jammer Immunity

AN GHz to 2.7 GHz Doherty power amplifier using the BLF7G27LS-150P. Document information

AN12082 Capacitive Touch Sensor Design

AN How to design an antenna with DPC. Rev November Application note COMPANY PUBLIC. Document information.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

AN Thermal considerations BGA3131. Document information. Keywords Abstract

AN Relay replacement by NXP high-power bipolar transistors in LFPAK56. Document information

AN UCODE I2C PCB antenna reference designs. Application note COMPANY PUBLIC. Rev October Document information

PN7150 Raspberry Pi SBC Kit Quick Start Guide

VHF variable capacitance diode

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

PN7120 NFC Controller SBC Kit User Manual

AN BFU725F/N1 2.4 GHz LNA evaluation board. Document information. Keywords. LNA, 2.4GHz, BFU725F/N1 Abstract

MC33PF8100, MC33PF8200

TN ADC design guidelines. Document information

AN Low Noise Fast Turn ON-OFF GHz WiFi LNA with BFU730F. Document information

Quad 2-input EXCLUSIVE-NOR gate

4-bit bidirectional universal shift register

Planar PIN diode in a SOD523 ultra small plastic SMD package.

B (bottom) Package type descriptive code. VFBGA176 Package style descriptive code

Four planar PIN diode array in SOT363 small SMD plastic package.

AN BGA GHz 16 db gain CATV amplifier. Document information. Keywords. BGA3021, Evaluation board, CATV, Medium Power.

BB Product profile. 2. Pinning information. 3. Ordering information. FM variable capacitance double diode. 1.1 General description

Planar PIN diode in a SOD882D leadless ultra small plastic SMD package.

Two elements in series configuration in a small SMD plastic package Low diode capacitance Low diode forward resistance AEC-Q101 qualified

50 ma LED driver in SOT457

BAP Product profile. 2. Pinning information. 3. Ordering information. Silicon PIN diode. 1.1 General description. 1.2 Features and benefits

HEF4002B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Dual 4-input NOR gate

4-bit bidirectional universal shift register

AN Application and soldering information for the PCA2129 and PCF2129 TCXO RTC. Document information

BFU550XR ISM 433 MHz LNA design. BFU520, BFU530, BFU550 series, ISM-band, 433MHz 866MHz Abstract

Dual 4-bit static shift register

Quad 2-input NAND buffer (open collector) The 74F38 provides four 2-input NAND functions with open-collector outputs.

Quad 2-input EXCLUSIVE-NOR gate

Hex non-inverting precision Schmitt-trigger

Single Schottky barrier diode

HEF4518B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual BCD counter

40 V, 0.75 A medium power Schottky barrier rectifier

12-stage binary ripple counter

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit

BT D. 1. General description. 2. Features and benefits. 3. Applications. 4. Quick reference data. 4Q Triac

HEF4069UB-Q General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Hex inverter

LOCMOS (Local Oxidation CMOS) to DTL/TTL converter HIGH sink current for driving two TTL loads HIGH-to-LOW level logic conversion

Dual 4-bit static shift register

PMEG4050ETP. 1. General description. 2. Features and benefits. 3. Applications. 4. Quick reference data

LOCMOS (Local Oxidation CMOS) to DTL/TTL converter HIGH sink current for driving two TTL loads HIGH-to-LOW level logic conversion

UM UBA2024 application development tool. Document information

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit

HEF4014B-Q General description. 2. Features and benefits. 3. Applications. 8-bit static shift register

HEF4014B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. 8-bit static shift register

AN BLF0910H9LS600

Hex inverting HIGH-to-LOW level shifter

Single Schmitt trigger buffer

Quad 2-input EXCLUSIVE-NOR gate

HEF4001B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NOR gate

KMA22x; KMA32x handling information

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit

Quad 2-input NAND Schmitt trigger

PMEG2005EGW. 1. General description. 2. Features and benefits. 3. Applications. 4. Quick reference data

30 V, 0.1 A low VF MEGA Schottky barrier rectifier. Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit I F(AV)

PMEG3050BEP. 1. General description. 2. Features and benefits. 3. Applications. 4. Quick reference data

Hex non-inverting HIGH-to-LOW level shifter

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

RB520CS30L. 1. Product profile. 100 ma low V F MEGA Schottky barrier rectifier. 1.1 General description. 1.2 Features and benefits. 1.

Low voltage rectification High efficiency DC-to-DC conversion Switch mode power supply Reverse polarity protection Low power consumption application

SJA1105P/Q/R/S. 1 Features and benefits. 1.1 General features. 1.2 Ethernet switching and AVB features. 1.3 Interface features

Transcription:

Rev. 1 4 September 2012 Application note Document information Info Keywords Abstract Content PCA2000, PCA2001, PCA2002, PCA2003, Calibration The PCA200x are CMOS integrated circuits for battery operated wrist watches with a 32 khz quartz crystal as the timing element and a bipolar 1 Hz stepping motor. The quartz crystal oscillator and the frequency divider are optimized for minimum power consumption. A timing accuracy of 1 ppm is achieved with a programmable, digital frequency adjustment. This document describes how the calibration can be performed.

Revision history Rev Date Description v.1 20120904 Initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 2 of 23

1. Introduction The PCA200x are CMOS integrated circuits for battery operated wrist watches with a 32 khz quartz crystal as the timing element and a bipolar 1 Hz stepping motor. The quartz crystal oscillator and the frequency divider are optimized for minimum power consumption. A timing accuracy of 1 ppm is achieved with a programmable, digital frequency adjustment. To obtain the minimum overall power consumption for the watch, an automatic motor pulse adaptation function is provided. The circuit supplies only the minimum drive current, which is necessary to ensure a correct motor step. Changing the drive current of the motor is achieved by chopping the motor pulse with a variable duty cycle. The pulse width and the range of the variable duty cycle can be programmed to suit different types of motors. A pin RESET is provided which can be used for stopping the motor, for accurate time setting, and for accelerated testing of the watch. 2. Functional description The PCA2000 has a battery End Of Life (EOL) warning function. If the battery voltage drops below the EOL threshold voltage (which can be programmed for silver oxide or lithium batteries), the motor steps change from one pulse per second to a burst of four pulses every 4 seconds. The EOL function is not present in PCA2001, PCA2002 and PCA2003. 2.1 Motor pulse The motor driver delivers pulses with an alternating polarity. The output waveform across the motor terminals is illustrated in Figure 1. Between the motor pulses, both terminals are connected to V DD which means that the motor is short-circuit. The following parameters can be programmed in a One Time Programmable (OTP) memory: Output periods of 1 s, 5 s, 10 s, 20 s, and 30 s Pulse width (t p ) between 0.98 ms and 7.8 ms in steps of 0.98 ms Full or chopped (75 %) output pulse Pulse stretching: An enlargement pulse added to the primary motor pulse. This enlargement pulse has a duty cycle of 25 % and a width which is twice the programmed motor pulse width. The repetition period for the chopping pattern is 0.98 ms. Figure 2 shows an example for a 3.9 ms pulse. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 3 of 23

period full pulse chopped pulse full pulse with stretching chopped pulse with stretching t p 2t p t p 2t p mgu718 Fig 1. Motor output waveforms Figure 2 shows an example for a 3.9 ms pulse. DUTY CYCLE 0.244 ms 0.122 ms 37.5 % 43.75 % 50 % 56.25 % 62.5 % 68.75 % 75 % 81.25 % 100 % 0.98 ms 0.98 ms 0.98 ms 0.98 ms mgw351 Fig 2. Possible modulations for a 3.9 ms motor pulse All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 4 of 23

2.2 Time calibration The quartz oscillator frequency would be exactly 32.768 khz if the oscillator load capacitance would fit exactly the requirements of the crystal. The quartz oscillator frequency is internally divided by 1024 and is nominally f nom = 32.768 khz 1024 = 32 Hz. This frequency can be measured at pin RESET as a square wave signal (f o ). The quartz crystal oscillator has an integrated capacitance of 5.2 pf, which is lower than the specified load capacitance (C L ) of 8.2 pf for the quartz crystal. Therefore, the oscillator frequency is typically 60 ppm higher than 32.768 khz (corresponding to about 3 minutes too fast per month). This positive frequency offset is compensated by removing the appropriate number of 8192 Hz pulses in the divider chain (maximum 127 pulses), every 1 or 2 minutes. The time correction is given in Table 1. Table 1. Time calibration Calibration Correction per step (n = 1) Correction per step (n = 127) period ppm seconds per day ppm seconds per day 1 minute 2.03 0.176 258 22.3 2 minutes 1.017 0.088 129 11.15 After measuring the effective oscillator frequency, the number of correction pulses must be calculated and stored together with the calibration period in the OTP memory (see Section 3 on page 12). Before programming the calibration word A (state 3) which contains the number of 8192 Hz pulses to be removed and the calibration period, first the motor pulse parameters must be programmed using word B (state 4). Since the programming is done using an OTP, a register bit can be changed from 0 to 1, but once programmed to 1 it can t be set back to 0. An automatic test sequence might have two phases: 2.3 Reset Program the IC in accordance with the mechanism used, followed by calibration Verify that the IC has been correctly programmed (optional for large series production) At pin RESET an output signal with the frequency f o is provided. Connecting pin RESET to V DD stops the motor drive and opens the motor switches. After releasing pin RESET, the first motor pulse is generated exactly one period later with the opposite polarity to the last pulse before stopping. The debounce time for the reset function is between 31 ms and 62 ms. Connecting pin RESET to V SS activates the test mode. In this mode the motor output frequency is 32 Hz, which can be used to test the mechanical function of the watch. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 5 of 23

Table 2. Word Bit 2.4 Programming possibilities 2.4.1 PCA2000 and PCA2001 The programming data is organized in an array of four 8-bit words (see Table 2): Word A for the time calibration, Words B and C for setting of the motor pulses and Word D for the type recognition. PCA2000 and PCA2001 register overview 1 2 3 4 5 6 7 8 A number of 8192 Hz pulses to be removed calibration period B lowest stage: duty cycle number of driving stages highest stage: duty cycle pulse stretching C pulse width maximum time delay between positive and negative detection pulses D type factory test bits factory test bits EOL voltage factory test bit Table 3. PCA2000 and PCA2001 description of word A bits Bit Value Description Inhibition time 1 to 7 - adjust the number of the 8192 Hz pulses to be removed; bit 1 is the MSB and bit 7 is the LSB Calibration period 8 0 1 minute 1 2 minutes Table 4. PCA2000 and PCA2001 description of word B bits Bit Value Description Duty cycle lowest driving stage 1to2 00 37.5 % 01 43.75 % 10 50 % 11 56.25 % Number of driving stages 3to4 00 3 01 4 10 5 11 6 [1] Duty cycle highest driving stage 5 0 75 % [2] 1 100 % Pulse stretching All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 6 of 23

Table 4. PCA2000 and PCA2001 description of word B bits continued Bit Value Description 6 0 no pulse stretching 1 pulse of 2 t p and duty cycle of 25 % are added Factory test bits 7to8 - - [1] Including the highest driving stage, which one has no motor step detection. [2] If the maximum duty cycle of 75 % is selected, not all programming combinations are possible since the second highest level must be smaller than the highest driving level. Table 5. PCA2000 and PCA2001 description of word C bits Bit Value Description Pulse width t p 1 to 3 000 0.98 ms 001 1.95 ms 010 2.93 ms 011 3.91 ms 100 4.88 ms 101 5.86 ms 110 6.84 ms 111 7.81 ms Time delay t [1] d(max) 4 to 6 000 3.91 ms 001 4.88 ms 010 5.86 ms 011 6.84 ms 100 7.81 ms 101 8.79 ms 110 9.77 ms 111 10.74 ms EOL voltage of the battery 7 0 1.38 V (silver-oxide) 1 2.5 V (lithium) Factory test bit 8 - - [1] Between positive and negative detection pulses. 2.4.2 PCA2002 The programming data is organized in an array of four 8-bit words (see Table 6). Word A for the time calibration, Word B for setting of the motor pulses, Word C is not used with PCA2002 and All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 7 of 23

Word D for the type recognition. Table 6. Word PCA2002 register overview Bit 1 2 3 4 5 6 7 8 A number of 8192 Hz pulses to be removed calibration period B pulse width output period duty cycle C - - - - - - - - D type factory - - - test bit pulse stretching There are four words, only words A and B can be programmed. The meaning of the individual bits is given in Table 7 and Table 8. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 8 of 23

Table 7. PCA2002 description of word A bits Bit Value Description Inhibit time 1 to 7 - adjust the number of the 8192 Hz pulses to be removed; bit 1 is the MSB and bit 7 is the LSB Calibration period 8 0 1 minute 1 2 minutes Table 8. PCA2002 description of word B bits Bit Value Description Pulse width t p (ms) 1 to 3 000 0.98 ms 001 1.95 ms 010 2.93 ms 011 3.91 ms 100 4.88 ms 101 5.86 ms 110 6.84 ms 111 7.81 ms Output period (s) 4to6 000 1 001 5 010 10 011 20 100 30 Duty cycle of motor pulse 7 0 75 % 1 100 % Pulse stretching 8 0 no pulse stretching 1 a pulse width of 2 t p and a duty factor of 25 % are added 2.4.3 PCA2003 The programming data is organized in an array of four 8-bit words (see Table 9): Word A for the time calibration, Words B and C for setting of the motor pulses and Word D for the type recognition. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 9 of 23

Table 9. Word Bit PCA2003 register overview 1 2 3 4 5 6 7 8 A number of 8192 Hz pulses to be removed calibration period B lowest stage: duty cycle number of driving stages highest stage: duty cycle pulse stretching C pulse width maximum time delay between positive and negative detection pulses D type factory test bits output period output period factory test bit Table 10. PCA2003 description of word A bits Bit Value Description Inhibition time 1 to 7 - adjust the number of the 8192 Hz pulses to be removed; bit 1 is the MSB and bit 7 is the LSB Calibration period 8 0 1 minute 1 2 minutes Table 11. PCA2003 description of word B bits Bit Value Description Duty cycle lowest driving stage 1to2 00 37.5 % 01 43.75 % 10 50 % 11 56.25 % Number of driving stages 3to4 00 3 01 4 10 5 11 6 [1] Duty cycle highest driving stage 5 0 75 % [2] 1 100 % Pulse stretching 6 0 no pulse stretching 1 pulse of 2 t p and duty cycle of 25 % are added Output period 7to8 00 1 s 01 5 s 10 10 s 11 20 s All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 10 of 23

[1] Including the highest driving stage, which one has no motor step detection. [2] If the maximum duty cycle of 75 % is selected, not all programming combinations are possible since the second highest level must be smaller than the highest driving level. Table 12. PCA2003 description of word C bits Bit Value Description Pulse width t p 1 to 3 000 0.98 ms 001 1.95 ms 010 2.93 ms 011 3.91 ms 100 4.88 ms 101 5.86 ms 110 6.84 ms 111 7.81 ms Time delay t [1] d(max) 4 to 6 000 3.91 ms 001 4.88 ms 010 5.86 ms 011 6.84 ms 100 7.81 ms 101 8.79 ms 110 9.77 ms 111 10.74 ms Output period 7 0 bit 7 and 8 of word B active 1 30 s, bit 7 and 8 of word B inactive Factory test bit 8 - - [1] Between positive and negative detection pulses. 2.5 Type recognition Byte D is read only and is to determine which type of the PCA200x family is used in a particular application. Table 13. Description of word D bits Bit Value Description Type recognition 1 to 4 0000 PCA2002 1000 PCA2000 0100 PCA2001 1100 PCA2003 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 11 of 23

3. Programming procedure The flow chart in Figure 3 indicates the programming procedure of the PCA2002. Details are given in the description on the following pages. Reset sequence/start-up This means, applying the supply voltage, wait the maximum oscillator start-up time t startup (0.9 s) after which the stop pulse t p(stop) must be given (max 0.5 ms). This step takes 0.9 s. See Figure 4 in the PCA2002 data sheet. Enter state 4 Program register B Exit state 4 Before programming the calibration word A, the motor pulse parameters must be programmed in word B. The optimal parameters have been established during the development and are the same for every watch of the same model which is being produced. Enter state 1 Measurement of f o (32 Hz) (crystal oscillator frequency / 1024) Exit state 1 Now that we are in state 1 it is possible to measure the frequency f o (32 Hz), which is the oscillator frequency divided by 1024. This can be done at pin RESET or by measuring the current modulation. Calculate frequency deviation in ppm f o f dev = -1 106 32 Hz The actual oscillator frequency is now known. It will be higher than. the nominal 32.768 khz. The deviation in ppm can. be calculated using this equation. Chose calibration period Correction once per minute or once per two minutes The correction can be applied once per minute or once per two minutes. A choice must be made whether to correct every minute or once per two minutes. Calculate n Once per min: n = f dev / 2.03 Once per 2 mins: n = f dev / 1.017 (1) The deviation in ppm was calculated before. If a correction is made every minute, a certain value n which will be programmed into A, will have an impact twice as high as when the correction is made once every two minutes. The correct value for n can be calculated with the equations given here. Enter state 3 Program word A Exit state 3 Program word A: The previously calculated value for n and if correction is performed every minute or once per two minutes. Enter state 2 Check inhibition time in state 2 Exit state 2 In order to check if programming was successful it is possible to measure the inhibition time by entering state 2. The inhibition time has a value of n 0.122 ms. A signal with the periodicity of 31.25 ms + n 0.122 ms appears at pin RESET and as a current modulation at pin V DD. Fig 3. (1) In this flowchart n = f dev /C ppm. In this case C ppm is the correction per step in ppm. In commercial calibration equipment often a slightly different calculation is used: n = (f dev -f goal )/C ppm, because some watch manufacturer want to program a target correction rate other than 0 (typically 0.15 s / day). Reasons for doing so can be for example, higher watch temperatures on the arm compared to the temperature during programming or that company policy requires that watches should run slightly faster than slightly too slow. Programming flow chart All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 12 of 23

For a watch, it is essential that the timing calibration can be made after the watch has been fully assembled. In this situation, the supply pins are often the only terminals which are still accessible. Figure 4 shows the set-up for programming 1 the assembled watch. 32 khz FREQUENCY COUNTER PCA200x M motor PROGRAMMABLE DC POWER SUPPLY battery PC INTERFACE PC mgw568 Fig 4. Frequency tuning the assembled watch Executing a power-on-reset, writing to the OTP cells and performing the related functional checks is achieved in the PCA200x by modulating the supply voltage. The necessary control circuit consists basically of a voltage level detector, an instruction counter which determines the function to be performed and an 8-bit shift register, which allows programming the OTP cells of an 8-bit word in one step and which acts also as a data pointer for checking the OTP content. In order to ensure that the oscillator starts up correctly after powering up the watch, a reset sequence must be executed. The reset sequence is given in Figure 5. Important: The programming procedure requires a stable oscillator, which means that a waiting time, determined by the start-up time of the oscillator, is necessary after power-up of the circuit. The maximum oscillator start-up time of the oscillator is 0.9 s. In Figure 5 t d(start) > 500 ms is indicated. In most cases this is enough but it may be necessary to reserve up to 900 ms for the oscillator start-up. This reset sequence is only required after power-up and not in between the various programming stages. That means that it is required just once during a normal programming procedure. 1. As far as NXP CWG knows, the two Swiss companies, Witschi and Femto, offer commercial programmers. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 13 of 23

V DD t p(stop) V P(prog)(stop) t d(start) > 500 ms V DD(nom) V SS 001aac503 Fig 5. t d(start) : start delay time. V DD(nom) : nominal supply voltage. Start-up reset sequence by varying the supply voltage in predefined manner The control circuit consists of an instruction counter which determines the function to be performed and an 8-bit shift register, which allows programming the OTP cells of an 8-bit word in one step and which acts also as a data pointer for checking the OTP content. There are six different states. In a normal programming procedure, these states are not accessed in sequence from 1 to 6. The different states are: State 1 measurement of f o (32Hz), the oscillator frequency divided by 1024 State 2 measurement of the inhibition time State 3 write/check word A State 4 write/check word B State 5 check word C (for PCA2002 don t care since no meaning) State 6 check word D (type recognition) Every instruction state is switched on with a programming start pulse, V P(prog)(start) with duration t p(start). This is the only way to enter the programming mode. For details about voltage levels and duration of the various pulses, please refer to the data sheets. After this large pulse, an initial waiting time t 0 is required. The programming instructions are then entered by modulating the supply voltage with small pulses (amplitude V P(mod ) and pulse width t mod ). The first small pulse defines the start time, the following pulses perform three different functions depending on the time delay (t d ) from the preceding pulse (see Figure 6, Figure 7, Figure 8 and Figure 9): t d = t 1 (0.7 ms) increments the instruction counter t d = t 2 (1.7 ms) clocks the shift register with data = logic 0 t d = t 3 (2.7 ms) clocks the shift register with data = logic 1 After the V P(prog)(start) pulse, the instruction counter is in state 1 and the data shift register is cleared. As mentioned above there is only one method to enter the programming mode, but there are two different methods to leave the programming mode: 1. The instruction stated ends with a second pulse to V P(prog)(stop) or with the pulse to V store. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 14 of 23

2. If no pulse to V P(prog)(stop) or V store is given, the instruction states are terminated automatically two seconds after the last supply modulation pulse. Examples are given below. 3.1 Enter state 4, program register B and exit state 4 Before programming the calibration word A, the motor pulse parameters must be programmed in word B. This means that state 4 is needed. The optimal parameters depend on the mechanism that is being used and during development of the watch the best settings for the mechanism must be established. These are then the same for every watch of the same model that is being produced. In general, in order to program a memory word (here memory word B), the following steps need to be performed: 1. Start with a V P(prog)(start) pulse, wait for the time period t 0 and then set the instruction counter to the word to be written (t d = t 1 ). After t 0 the first small pulse puts the IC in state 1. Every consecutive waiting time t d = t 1 followed by a small pulse increases the state; 2. Enter the data to be stored into the shift register (t d = t 2 or t 3 ), LSB first (bit 8) and MSB last (bit 1); 3. Applying the two-stage programming pulse V prestore followed by V store stores the word. The delay between the last data bit and the pre-store pulse V prestore is t d = t 4. Store the word by raising the supply voltage to V store ; the delay between the last data bit and the store pulse is t d. The example below in Figure 6 shows programming of B = 110101 (the sequence is LSB first and MSB last) 2. It performs the following functions: Start; Setting the instruction counter to state 4 (word B); Entering data word 110101 into the shift register (sequence: LSB first, MSB last); Writing the OTP cells for word B. 2. This example is only valid for PCA2000 and PCA2001; for PCA2002 the sequence would be 11001001, programming a pulse width of 6.8 ms, an output period of 10 s, a duty cycle of 75 %. and a pulse stretching of 1. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 15 of 23

t w(prestore) V DD V store t p(start) V P(prog)(start) V prestore t 0 t 1 t 1 t 1 t 3 t 2 t 3 t 2 t 3 t 3 t 4 t w(store) V P(mod) V DD(nom) V SS mgw356 V DD(nom) : nominal supply voltage. Fig 6. Supply voltage modulation for programming word B (state 4) 3.2 Enter state 1, measure the oscillator frequency and leave state 1 Now that the motor pulse parameters have been programmed, it is possible to calibrate the watch. This is done by first measuring the actual oscillator frequency. From there the required number of inhibition pulses can be calculated. In short, enter state 1, measure the frequency f o (which is the oscillator frequency divided by 1024) and leave state 1. State 1 starts with a pulse to V P and ends with a second pulse to V P as indicated below. In order to enter state 1 the following step needs to be performed: 1. Start with a V P(prog)(start) pulse, wait for the time period t 0 and then give a small pulse. This is indicated in Figure 7. V DD t p(start) V P(prog)(start) start programming (state 1) t 0 V P(mod) V DD(nom) V SS Fig 7. Entering state 1 where the oscillator frequency can be measured The frequency f o can either be monitored directly at pin RESET or as a modulation of the supply current (a modulating resistor of 30 kω is connected between V DD and V SS when the signal at pin RESET is HIGH, increasing the supply current accordingly). Leave state 1 by giving a pulse to V P(prog)(stop). If no such pulse is given, state 1 is left automatically two seconds after the last supply modulation pulse. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 16 of 23

3.3 Calculate the frequency deviation of the oscillator in ppm, and the value of n The actual oscillator frequency is now known. It was purposely set higher than 32.768 khz. The frequency adjustment is made by introducing longer seconds at certain intervals (pulses from the quartz are inhibited at those intervals). During the inhibition sequence one 32 Hz-period at the pin RESET is increased by n x 0.122 ms. Here n is the number that is programmed in the OTP. The programmed inhibition time can later easily be measured in state 2, see Section 3.5. The frequency deviation in ppm can be calculated as follows: f dev = f o ------------- 1 32 Hz 10 6 (1) The correction can be applied once per minute or once per two minutes (calibration period). This is a choice that has to be made. If a correction is made ever minute a certain value n which will be programmed into word A will have an impact twice as high as when the correction is made only once every two minutes. The correct value for n (the number of 8192 Hz pulses to be inhibited) can be calculated with the following formulas (see also Table 1): Correction once per minute: Correction once per two minutes: n = f dev 2.03 n = f dev 1.017 The calculated value n must be programmed into register A, together with the calibration period in the next step. 3.4 Enter state 3, program word A and leave state 3 In general, in order to program a memory word (here memory word A), the following steps need to be performed: 1. Start with a V P(prog)(start) pulse, wait for the time period t 0 and then set the instruction counter to the word to be written (t d = t1). After t 0 the first small pulse puts the IC in state 1. Every consecutive waiting time t d = t1 followed by a small pulse increases the state; 2. Enter the data to be stored into the shift register (t d = t 2 or t 3 ), LSB first (bit 8) and MSB last (bit 1); 3. Applying the two-stage programming pulse V prestore followed by V store stores the word. The delay between the last data bit and the pre-store pulse V prestore is t d = t 4. Store the word by raising the supply voltage to V store ; the delay between the last data bit and the store pulse is t d. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 17 of 23

V DD t p(start) V P(prog)(start) state 3 t 0 t 1 t 1 V P(mod) V DD(nom) V SS Fig 8. Supply voltage modulation for entering state 3 (programming of word A) After state 3 has been entered the programming of the word and leaving state 3 is as indicated in the example of Figure 8. 3.5 Check the inhibition time in State 2 In order to check whether programming was successful it is possible to measure the inhibition time. Also the inhibition time can either be monitored directly at pin RESET or as a modulation of the supply current (a modulating resistor of 30 kω is connected between V DD and V SS when the signal at pin RESET is HIGH, increasing the supply current accordingly). The inhibition time is measured in state 2. The inhibition time has a value of n 0.122 ms (reciprocal of 8192 Hz). A signal with the periodicity of 31.25 ms + n 0.122 ms appears at pin RESET and as a current modulation at pin V DD, see Figure 9 and Figure 10. The 31.25 ms is the reciprocal of 32 Hz. V DD t p(start) t p(stop) V P(prog)(start) V P(prog)(stop) t 0 t 1 V P(mod) V DD(nom) V SS mgu719 V DD(nom) : nominal supply voltage. Fig 9. Supply voltage modulation for entering and leaving state 2 Figure 9 above indicates how to enter and leave state 2. Figure 10 below indicates the output waveforms that appear at pin RESET in state 2. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 18 of 23

31.25 ms + inhibition time V DD V SS V O(dif) mgw355 Fig 10. Output waveform at pin RESET for instruction state 2 4. References [1] AN10439 Wafer Level Chip Size Package [2] AN10706 Handling bare die [3] PCA2000; PCA2001 32 khz watch circuit with programmable adaptive motor pulse; product data sheet [4] PCA2002 32 khz watch circuit with programmable output period and pulse width; product data sheet [5] PCA2003 32 khz watch circuit with programmable adaptive motor pulse and pulse period; product data sheet All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 19 of 23

5. Legal information 5.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 5.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations A non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 5.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 20 of 23

6. Tables Table 1. Time calibration.........................5 Table 2. PCA2000 and PCA2001 register overview....6 Table 3. PCA2000 and PCA2001 description of word A bits...................................6 Table 4. PCA2000 and PCA2001 description of word B bits...................................6 Table 5. PCA2000 and PCA2001 description of word C bits...................................7 Table 6. PCA2002 register overview................8 Table 7. PCA2002 description of word A bits.........9 Table 8. PCA2002 description of word B bits.........9 Table 9. PCA2003 register overview...............10 Table 10. PCA2003 description of word A bits........10 Table 11. PCA2003 description of word B bits........10 Table 12. PCA2003 description of word C bits........ 11 Table 13. Description of word D bits................ 11 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 21 of 23

7. Figures Fig 1. Motor output waveforms....................4 Fig 2. Possible modulations for a 3.9 ms motor pulse...4 Fig 3. Programming flow chart....................12 Fig 4. Frequency tuning the assembled watch.......13 Fig 5. Start-up reset sequence by varying the supply voltage in predefined manner...............14 Fig 6. Supply voltage modulation for programming word B (state 4)................................16 Fig 7. Entering state 1 where the oscillator frequency can be measured............................16 Fig 8. Supply voltage modulation for entering state 3 Fig 9. (programming of word A)...................18 Supply voltage modulation for entering and leaving state 2.................................18 Fig 10. Output waveform at pin RESET for instruction state 2.................................19 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 1 4 September 2012 22 of 23

8. Contents 1 Introduction............................ 3 2 Functional description................... 3 2.1 Motor pulse............................ 3 2.2 Time calibration........................ 5 2.3 Reset................................ 5 2.4 Programming possibilities................. 6 2.4.1 PCA2000 and PCA2001.................. 6 2.4.2 PCA2002............................. 7 2.4.3 PCA2003............................. 9 2.5 Type recognition....................... 11 3 Programming procedure................. 12 3.1 Enter state 4, program register B and exit state 4.............................. 15 3.2 Enter state 1, measure the oscillator frequency and leave state 1...................... 16 3.3 Calculate the frequency deviation of the oscillator in ppm, and the value of n........ 17 3.4 Enter state 3, program word A and leave state 3............................... 17 3.5 Check the inhibition time in State 2......... 18 4 References............................ 19 5 Legal information....................... 20 5.1 Definitions............................ 20 5.2 Disclaimers........................... 20 5.3 Trademarks........................... 20 6 Tables................................ 21 7 Figures............................... 22 8 Contents.............................. 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 September 2012 Document identifier: