.5 Ω On Resistance, ±5 V/+2 V/±5 V, icmos, Quad SPST Switches ADG4/ADG42/ADG43 FEATURES.5 Ω on resistance.3 Ω on-resistance flatness. Ω on-resistance match between channels Continuous current per channel LFCSP package: 25 ma TSSOP package: 9 ma Fully specified at +2 V, ±5 V, and ±5 V No V L supply required 3 V logic-compatible inputs Rail-to-rail operation 6-lead TSSOP and 6-lead, 4 mm 4 mm LFCSP Qualified for automotive applications APPLICATIONS Automated test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communications systems Relay replacement GENERAL DESCRIPTION The ADG4/ADG42/ADG43 are monolithic complementary metal-oxide semiconductor (CMOS) devices containing four independently selectable switches designed on an icmos process. icmos (industrial CMOS) is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, icmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching signals. icmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. The ADG4/ADG42/ADG43 contain four independent single-pole/single-throw (SPST) switches. The ADG4 and IN IN2 IN3 IN4 ADG4 FUNCTIONAL BLOCK DIAGRAM S D S2 D2 S3 D3 S4 D4 IN IN2 IN3 IN4 ADG42 S D S2 D2 S3 D3 S4 D4 IN IN2 IN3 IN4 SWITCHES SHOWN FOR A LOGIC INPUT. Figure. ADG43 ADG42 differ only in that the digital control logic is inverted. The ADG4 switches are turned on with Logic on the appropriate control input, whereas the ADG42 switches are turned on with Logic. The ADG43 has two switches with digital control logic similar to that of the ADG4; the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The ADG43 exhibits break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection, which results in minimum transients when the digital inputs are switched. PRODUCT HIGHLIGHTS. 2.6 Ω maximum on resistance over temperature. 2. Minimum distortion. 3. Ultralow power dissipation: <.3 µw. 4. 6-lead TSSOP and 6-lead, 4 mm 4 mm LFCSP packages. S D S2 D2 S3 D3 S4 D4 685- Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 262-96, U.S.A. Tel: 78.329.47 www.analog.com Fax: 78.46.33 28 2 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Product Highlights... Revision History... 2 Specifications... 3 ±5 V Dual Supply... 3 +2 ingle Supply... 4 ±5 V Dual Supply... 5 Absolute Maximum Ratings...6 ESD Caution...6 Pin Configurations and Function Descriptions...7 Typical Performance Characteristics...8 Terminology... 2 Test Circuits... 3 Outline Dimensions... 5 Ordering Guide... 6 Automotive Products... 6 REVISION HISTORY 3/ Rev. A to Rev. B Changes to Features Section... Changes to Table 5, Added Exposed Pad Notation... 3 Updated Outline Dimensions... 5 Changes to Ordering Guide... 4 Added Automotive Products Section... 4 3/9 Rev. to Rev. A Changes to Power Requirements, I DD, Digital Inputs = 5 V Parameter, Table... 3 Changes to Power Requirements, I DD, Digital Inputs = 5 V Parameter Table 2... 4 5/8 Revision : Initial Version Rev. B Page 2 of 6
SPECIFICATIONS ±5 V DUAL SUPPLY V DD = 5 V ± %, S = 5 V ± %, GND = V, unless otherwise noted. Rev. B Page 3 of 6 ADG4/ADG42/ADG43 Table. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V DD to S V On Resistance, R ON.5 Ω typ = ± V, I S = ma; see Figure 23.8 2.3 2.6 Ω max V DD = +3.5 V, S = 3.5 V On-Resistance Match. Ω typ = ± V, I S = ma Between Channels, R ON.8.9.2 Ω max On-Resistance Flatness, R FLAT(ON).3 Ω typ = ± V, I S = ma.36.4.45 Ω max LEAKAGE CURRENTS V DD = +6.5 V, S = 6.5 V Source Off Leakage, I S (Off) ±.3 na typ = ± V, V D = V; see Figure 24 ±.55 ±2 ±2.5 na max Drain Off Leakage, I D (Off) ±.3 na typ = ± V, V D = V; see Figure 24 ±.55 ±2 ±2.5 na max Channel On Leakage, I D, I S (On) ±.5 na typ = V D = ± V; see Figure 25 ±2 ±4 ±3 na max DIGITAL INPUTS Input High Voltage, V INH 2. V min Input Low Voltage, V INL.8 V max Input Current, I INL or I INH.5 µa typ V IN = V GND or V DD ±. µa max Digital Input Capacitance, C IN 3.5 pf typ DYNAMIC CHARACTERISTICS t ON ns typ R L = 3 Ω, C L = 35 pf 5 7 9 ns max = V; see Figure 3 t OFF 9 ns typ R L = 3 Ω, C L = 35 pf 2 4 6 ns max = V; see Figure 3 Break-Before-Make Time Delay, t D (ADG43 Only) 25 ns typ R L = 3 Ω, C L = 35 pf ns min = 2 = V; see Figure 3 Charge Injection, Q INJ 2 pc typ = V, R S = Ω, C L = nf; see Figure 32 Off Isolation 8 db typ R L = 5 Ω, C L = 5 pf, f = khz; see Figure 26 Channel-to-Channel Crosstalk db typ R L = 5 Ω, C L = 5 pf, f = MHz; see Figure 27 Total Harmonic Distortion + Noise.4 % typ R L = Ω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 7 MHz typ R L = 5 Ω, C L = 5 pf; see Figure 28 Insertion Loss.35 db typ R L = 5 Ω, C L = 5 pf, f = MHz; see Figure 28 C S (Off) 23 pf typ = V, f = MHz C D (Off) 23 pf typ = V, f = MHz C D, C S (On) 6 pf typ = V, f = MHz POWER REQUIREMENTS V DD = +6.5 V, S = 6.5 V I DD. µa typ Digital inputs = V or V DD µa max I DD 22 µa typ Digital inputs = 5 V 38 µa max I SS. µa typ Digital inputs = V or V DD µa max V DD /S ±4.5/±6.5 V min/v max GND = V Guaranteed by design; not subject to production test.
+2 INGLE SUPPLY V DD = 2 V ± %, S = V, GND = V, unless otherwise noted. Table 2. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V DD V On Resistance, R ON 2.8 Ω typ = V to V, I S = ma; see Figure 23 3.5 4.3 4.8 Ω max V DD =.8 V, S = V On-Resistance Match.3 Ω typ = V to V, I S = ma Between Channels, R ON.2.23.25 Ω max On-Resistance Flatness, R FLAT(ON).6 Ω typ = V to V, I S = ma..2.3 Ω max LEAKAGE CURRENTS V DD =.8 V, S = V Source Off Leakage, I S (Off) ±.2 na typ = V/ V, V D = V/ V; see Figure 24 ±.55 ±2 ±2.5 na max Drain Off Leakage, I D (Off) ±.2 na typ = V/ V, V D = V/ V; see Figure 24 ±.55 ±2 ±2.5 na max Channel On Leakage, I D, I S (On) ±.5 na typ = V D = V/ V; see Figure 25 ±.5 ±4 ±3 na max DIGITAL INPUTS Input High Voltage, V INH 2. V min Input Low Voltage, V INL.8 V max Input Current, I INL or I INH. µa typ V IN = V GND or V DD ±. µa max Digital Input Capacitance, C IN 3.5 pf typ DYNAMIC CHARACTERISTICS t ON 7 ns typ R L = 3 Ω, C L = 35 pf 25 295 33 ns max = 8 V; see Figure 3 t OFF 75 ns typ R L = 3 Ω, C L = 35 pf 35 65 9 ns max = 8 V; see Figure 3 Break-Before-Make Time Delay, t D (ADG43 Only) ns typ R L = 3 Ω, C L = 35 pf 4 ns min = 2 = 8 V; see Figure 3 Charge Injection, Q INJ 3 pc typ = 6 V, R S = Ω, C L = nf; see Figure 32 Off Isolation 8 db typ R L = 5 Ω, C L = 5 pf, f = khz; see Figure 26 Channel-to-Channel Crosstalk db typ R L = 5 Ω, C L = 5 pf, f = MHz; see Figure 27 3 db Bandwidth 3 MHz typ R L = 5 Ω, C L = 5 pf; see Figure 28 Insertion Loss.5 db typ R L = 5 Ω, C L = 5 pf, f = MHz; see Figure 28 C S (Off) 38 pf typ = 6 V, f = MHz C D (Off) 4 pf typ = 6 V, f = MHz C D, C S (On) 4 pf typ = 6 V, f = MHz POWER REQUIREMENTS V DD = 3.2 V I DD. µa typ Digital inputs = V or V DD µa max 22 µa typ Digital inputs = 5 V 38 µa max V DD 5/6.5 V min/v max GND = V, S = V Guaranteed by design; not subject to production test. Rev. B Page 4 of 6
±5 V DUAL SUPPLY V DD = 5 V ± %, S = 5 V ± %, GND = V, unless otherwise noted. Table 3. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V DD to S V On Resistance, R ON 3.3 Ω typ = ±4.5 V, I S = ma; see Figure 23 4 4.9 5.4 Ω max V DD = +4.5 V, S = 4.5 V On-Resistance Match.3 Ω typ = ±4.5 V, I S = ma Between Channels, R ON.22.23.25 Ω max On-Resistance Flatness, R FLAT(ON).9 Ω typ = ±4.5 V; I S = ma..24.3 Ω max LEAKAGE CURRENTS V DD = +5.5 V, S = 5.5 V Source Off Leakage, I S (Off) ±.3 na typ = ±4.5 V, V D = 4.5 V; see Figure 24 ±.55 ±2 ±2.5 na max Drain Off Leakage, I D (Off) ±.3 na typ = ±4.5 V, V D = 4.5 V; see Figure 24 ±.55 ±2 ±2.5 na max Channel On Leakage, I D, I S (On) ±.5 na typ = V D = ±4.5 V; see Figure 25 ±. ±4 ±3 na max DIGITAL INPUTS Input High Voltage, V INH 2. V min Input Low Voltage, V INL.8 V max Input Current, I INL or I INH. µa typ V IN = V GND or V DD ±. µa max Digital Input Capacitance, C IN 3.5 pf typ DYNAMIC CHARACTERISTICS t ON 275 ns typ R L = 3 Ω, C L = 35 pf 4 465 5 ns max = 3 V; see Figure 3 t OFF 75 ns typ R L = 3 Ω, C L = 35 pf 29 32 38 ns max = 3 V; see Figure 3 Break-Before-Make Time Delay, t D (ADG43 Only) ns typ R L = 3 Ω, C L = 35 pf 5 ns min = 2 = 3 V; see Figure 3 Charge Injection, Q INJ 3 pc typ = V, R S = Ω, C L = nf; see Figure 32 Off Isolation 8 db typ R L = 5 Ω, C L = 5 pf, f = khz; see Figure 26 Channel-to-Channel Crosstalk db typ R L = 5 Ω, C L = 5 pf, f = MHz; see Figure 27 Total Harmonic Distortion + Noise.3 % typ R L = Ω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 3 MHz typ R L = 5 Ω, C L = 5 pf; see Figure 28 Insertion Loss.5 db typ R L = 5 Ω, C L = 5 pf, f = MHz; see Figure 28 C S (Off) 32 pf typ = V, f = MHz C D (Off) 33 pf typ = V, f = MHz C D, C S (On) 6 pf typ = V, f = MHz POWER REQUIREMENTS V DD = +5.5 V, S = 5.5 V I DD. µa typ Digital inputs = V or V DD. µa max I SS. µa typ Digital inputs = V or V DD. µa max V DD /S ±4.5/±6.5 V min/v max GND = V Guaranteed by design; not subject to production test. Rev. B Page 5 of 6
ABSOLUTE MAXIMUM RATINGS, unless otherwise noted. Table 4. Parameter V DD to S V DD to GND S to GND Analog Inputs Digital Inputs Peak Current, Sx or Pins Rating 35 V.3 V to +25 V +.3 V to 25 V S.3 V to V DD +.3 V or 3 ma, whichever occurs first GND.3 V to V DD +.3 V or 3 ma, whichever occurs first 5 ma (pulsed at ms, % duty cycle maximum) Continuous Current per Channel at 25 C 6-Lead TSSOP 9 ma 6-Lead LFCSP 25 ma Continuous Current per Channel at 25 C 6-Lead TSSOP 9 ma 6-Lead LFCSP ma Operating Temperature Range Automotive (Y Version) 4 C to +25 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C 6-Lead TSSOP, θ JA Thermal 2 C/W Impedance (Four-Layer Board) 6-Lead LFCSP, θ JA Thermal 3.4 C/W Impedance Reflow Soldering Peak 26(+/ 5) C Temperature, Pb Free Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION Overvoltages at the INx, Sx, and pins are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B Page 6 of 6
D4 IN4 IN3 D3 5 6 7 8 ADG4/ADG42/ADG43 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN 6 IN2 D 2 5 D2 S 3 ADG4/ 4 S2 S 4 ADG42/ ADG43 3 V DD GND 5 TOP VIEW 2 NC S4 6 (Not to Scale) S3 D4 7 D3 IN4 8 9 IN3 NC = NO CONNECT Figure 2. TSSOP Pin Configuration 685-2 S S 2 GND 3 S4 4 6 D 5 IN 4 IN2 3 D2 PIN INDICATOR ADG4/ ADG42/ ADG43 TOP VIEW (Not to Scale) 2 S2 V DD NC 9 S3 NOTES. EXPOSED PAD TIED TO SUBSTRATE, S. 2. NC = NO CONNECT. Figure 3. LFCSP Pin Configuration 685-3 Table 5. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 5 IN Logic Control Input. 2 6 D Drain Terminal. This pin can be an input or output. 3 S Source Terminal. This pin can be an input or output. 4 2 S Most Negative Power Supply Potential. 5 3 GND Ground ( V) Reference. 6 4 S4 Source Terminal. This pin can be an input or output. 7 5 D4 Drain Terminal. This pin can be an input or output. 8 6 IN4 Logic Control Input. 9 7 IN3 Logic Control Input. 8 D3 Drain Terminal. This pin can be an input or output. 9 S3 Source Terminal. This pin can be an input or output. 2 NC No Connection. 3 V DD Most Positive Power Supply Potential. 4 2 S2 Source Terminal. This pin can be an input or output. 5 3 D2 Drain Terminal. This pin can be an input or output. 6 4 IN2 Logic Control Input. N/A EP Exposed Pad. Tie the exposed pad to the substrate, S. N/A means not applicable. Table 6. ADG4/ADG42 Truth Table ADG4 INx ADG42 INx Switch Condition On Off Table 7. ADG43 Truth Table ADG43 INx S, S4 S2, S3 Off On On Off Rev. B Page 7 of 6
TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) 2.5 2..5. V DD = +V, S = V V DD = +3.5V, S = 3.5V V DD = +2V, S = 2V V DD = +5V, S = 5V V DD = +6.5V, S = 6.5V ON RESISTANCE (Ω) 3. 2.5 2..5. T A = +25 C T A = +85 C T A = +25 C T A = 4 C.5 I S = ma 6.5 2.5 8.5 4.5.5 3.5 7.5.5 5.5 OR V D (V) 685-4.5 V DD = +5V S = 5V I S = ma 5 5 5 5 OR V D (V) 685-7 Figure 4. On Resistance vs. V D or, Dual Supply Figure 7. On Resistance vs. V D or for Different Temperatures, ±5 V Dual Supply ON RESISTANCE (Ω) 4. 3.5 3. 2.5 2..5. V DD = +4.5V, S = 4.5V V DD = +5V, S = 5V V DD = +5.5V, S = 5.5V V DD = +7V, S = 7V.5 I S = ma 7 6 5 4 3 2 2 3 4 5 6 7 OR V D (V) 685-5 ON RESISTANCE (Ω) 5. 4.5 4. 3.5 3. 2.5 2..5 T A = +25 C T A = +85 C T A = +25 C T A = 4 C..5 V DD = +5V S = 5V I S = ma 5 4 3 2 2 3 4 5 OR V D (V) 685-8 Figure 5. On Resistance vs. V D or, Dual Supply Figure 8. On Resistance vs. V D or for Different Temperatures, ±5 V Dual Supply 7 6 V DD = 5V, S = V 4.5 4. 3.5 T A = +25 C ON RESISTANCE (Ω) 5 4 3 2 V DD = 8V, S = V V DD = 3.2V, S = V I S = ma 2 4 6 8 2 4 OR V D (V) V DD =.8V, S = V Figure 6. On Resistance vs. V D or, Single Supply V DD = 2V, S = V V DD = 5V, S = V 685-6 ON RESISTANCE (Ω) 3. 2.5 2..5 T A = +85 C T A = +25 C T A = 4 C..5 V DD = 2V S = V I S = ma 2 4 6 8 2 OR V D (V) Figure 9. On Resistance vs. V D or for Different Temperatures, +2 ingle Supply 685-9 Rev. B Page 8 of 6
ON RESISTANCE (Ω) 5. 4.5 4. 3.5 3. 2.5 2..5 T A = 25 C I S = ma I S = 9mA LEAKAGE (na) 9 8 7 6 5 4 3 2 V DD = 2V S = V V BIAS = V/V I S (OFF) + I D (OFF) + I S (OFF) + I D (OFF) + I D, I S (ON) ++ I D, I S (ON)..5 V DD = +5V S = 5V 5 4 3 2 2 3 4 5 OR V D (V) Figure. On Resistance vs. V D or for Different Current Levels, ±5 V Dual Supply 685-2 4 6 8 2 TEMPERATURE ( C) Figure 3. Leakage Currents vs. Temperature, +2 ingle Supply 685-7.5..5 I D (OFF) + I S (OFF) + I D, I S (ON) + + 8 7 6 I DD PER LOGIC INPUT LEAKAGE (na).5..5 2. I D, I S (ON) 2.5 V DD = +5V I S (OFF) + 3. S = 5V V BIAS = +V/ V 3.5 2 4 6 8 2 TEMPERATURE ( C) I D (OFF) + 685-5 I DD (µa) 5 4 3 2 V DD = +2V S = V V DD = +5V S = 5V V DD = +5V S = 5V 2 4 6 8 2 4 LOGIC, INx (V) 685-8 Figure. Leakage Currents vs. Temperature, ±5 V Dual Supply Figure 4. I DD vs. Logic Level LEAKAGE (na).5..5 V DD = +5V S = 5V V BIAS = +4.5V/ 4.5V.5 I S (OFF) + I D (OFF) + I S (OFF) +. I D (OFF) + I D, I S (ON) ++ I D, I S (ON).5 2 4 6 8 2 TEMPERATURE ( C) 685-6 CHARGE INJECTION (pc) 6 4 2 2 4 V DD = +5V, S = 5V V DD = +5V, S = 5V 6 5 5 5 5 (V) V DD = +2V, S = V 685-2 Figure 2. Leakage Currents vs. Temperature, ±5 V Dual Supply Figure 5. Charge Injection vs. Source Voltage Rev. B Page 9 of 6
3 25.5 V DD = +5V S = 5V 2S t ON. TIME (ns) 2 5 5V DS t ON 2S t OFF 5V DS t OFF INSERTION LOSS (db).5 2. 2.5 3. 5 3.5 4 2 2 4 6 8 2 TEMPERATURE ( C) 685-3 4. k k M M M G FREQUENCY (Hz) 685-6 Figure 6. t ON /t OFF Times vs. Temperature for Single Supply (SS) and Dual Supply (DS) Figure 9. On Response vs. Frequency, ±5 V Dual Supply 2 V DD = +5V S = 5V 2 V DD = +5V S = 5V V p-p =.62V OFF ISOLATION (db) 3 4 5 6 7 ACPSRR (db) 3 4 5 6 7 NO DECOUPLING CAPACITORS DECOUPLING CAPACITORS ON SUPPLIES 8 8 9 9 k k k M M M G FREQUENCY (Hz) 685-4 k k k M M FREQUENCY (Hz) 685-7 Figure 7. Off Isolation vs. Frequency, ±5 V Dual Supply Figure 2. ACPSRR vs. Frequency, ±5 V Dual Supply CROSSTALK (db) 2 3 4 5 6 7 8 9 V DD = +5V S = 5V 2 k k M M M G FREQUENCY (Hz) Figure 8. Crosstalk vs. Frequency, ±5 V Dual Supply 685-5 THD + N (%).28.26.24.22.2.8.6.4.2..8.6.4 V DD = +5V S = 5V = 2V p-p = 5V p-p = V p-p.2 k k k FREQUENCY (Hz) Figure 2. THD + N vs. Frequency, ±5 V Dual Supply 685-7 Rev. B Page of 6
V DD = +5V S = 5V = V p-p. THD + N (%). = 5V p-p = 2.5V p-p. k k k FREQUENCY (Hz) Figure 22. THD + N vs. Frequency, ±5 V Dual Supply 685-8 Rev. B Page of 6
TERMINOLOGY I DD The positive supply current. I SS The negative supply current. V D, The analog voltage on Terminal D and Terminal S. R ON The ohmic resistance between Terminal D and Terminal S. R FLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. I S (Off) The source leakage current with the switch off. I D (Off) The drain leakage current with the switch off. I D, I S (On) The channel leakage current with the switch on. V INL The maximum input voltage for Logic. V INH The minimum input voltage for Logic. I INL, I INH The input current of the digital input when high or when low. C S (Off) The off switch source capacitance, which is measured with reference to ground. C D (Off) The off switch drain capacitance, which is measured with reference to ground. C D, C S (On) The on switch capacitance, which is measured with reference to ground. C IN The digital input capacitance. t ON The delay between applying the digital control input and the output switching on. See Figure 3. t OFF The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) A measure of the part s ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of.62 V p-p. The ratio of the amplitude of the signal on the output to the amplitude of the modulation is the ACPSRR. Rev. B Page 2 of 6
TEST CIRCUITS DD S.µFV.µF V DD S NETWORK ANALYZER I S INx Sx 5Ω 5Ω Sx V V IN GND R L 5Ω V OUT R ON = V/I S Figure 23. On Resistance 685-2 Figure 26. Off Isolation OFF ISOLATION = 2 log V OUT 685-26 DD S.µFV.µF NETWORK ANALYZER V OUT R L 5Ω S S2 V DD S R L 5Ω I S (OFF) A Sx I D (OFF) A GND V D 685-2 CHANNEL-TO-CHANNEL CROSSTALK = 2 log V OUT 685-27 Figure 24. Off Leakage Figure 27. Channel-to-Channel Crosstalk DD S.µFV.µF V DD S NETWORK ANALYZER INx Sx 5Ω NC Sx I D (ON) A V IN GND R L 5Ω V OUT NC = NO CONNECT V D 685-22 V OUT WITH SWITCH INSERTION LOSS = 2 log V OUT WITHOUT SWITCH 685-28 Figure 25. On Leakage Figure 28. Bandwidth Rev. B Page 3 of 6
DD S.µFV.µF AUDIO PRECISION V DD S R S INx V IN GND Sx R L Ω V OUT V p-p 685-29 Figure 29. THD + Noise DD S.µFV.µF V IN ADG42 5% 5% V DD S INx Sx R L 3Ω V OUT C L 35pF V IN V OUT ADG4 5% 5% 9% 9% GND t ON t OFF 685-23 Figure 3. Switching Times DD S.µFV.µF V IN V 5% 5% V DD S S D 2 IN, IN2 S2 D2 ADG43 GND R L 3Ω V OUT2 C L 35pF R L 3Ω C L 35pF V OUT V OUT V OUT2 V V 9% t D 9% 9% t D 9% 685-24 Figure 3. Break-Before-Make Time Delay V DD S R S V DD Sx S V OUT V IN ADG42 ON OFF INx C L nf V IN ADG4 GND V OUT Q INJ = C L ΔV OUT ΔV OUT 685-25 Figure 32. Charge Injection Rev. B Page 4 of 6
OUTLINE DIMENSIONS 5. 5. 4.9 6 9 4.5 4.4 4.3 6.4 BSC 8.5.5 PIN.65 BSC.3.9 COPLANARITY..2 MAX.2.9.75 SEATING PLANE 8.6.45 COMPLIANT TO JEDEC STANDARDS MO-53-AB Figure 33. 6-Lead Thin Shrink Small Outline Package [TSSOP] (RU-6) Dimensions shown in millimeters 4. BSC SQ.5.4.6 MAX.3 PIN INDICATOR PIN INDICATOR..85.8 SEATING PLANE TOP VIEW 3.75 BSC SQ 2 MAX.8 MAX.65 TYP.3.23.8.65 BSC 2 3.95 BCS BOTTOM VIEW.5 MAX.2 NOM COPLANARITY.2 REF.8 COMPLIANT TO JEDEC STANDARDS MO-22-VGGC. 9 6 EXPOSED PAD 8 4 5 2.65 2.5 SQ 2.35.25 MIN Figure 34. 6-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm 4 mm Body, Very Thin Quad (CP-6-3) Dimensions shown in millimeters FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 36-A Rev. B Page 5 of 6
ORDERING GUIDE Model, 2 Temperature Range Package Description Package Option ADG4YRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package (TSSOP) RU-6 ADG4YRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package (TSSOP) RU-6 ADG4YCPZ-REEL 4 C to +25 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-3 ADG4YCPZ-REEL7 4 C to +25 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-3 ADG4WBCPZ-REEL 4 C to +25 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-3 ADG42YRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package (TSSOP) RU-6 ADG42YRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package (TSSOP) RU-6 ADG42YCPZ-REEL 4 C to +25 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-3 ADG42YCPZ-REEL7 4 C to +25 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-3 ADG43YRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package (TSSOP) RU-6 ADG43YRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package (TSSOP) RU-6 ADG43YCPZ-REEL 4 C to +25 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-3 ADG43YCPZ-REEL7 4 C to +25 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-3 Z = RoHS Compliant Part. 2 W = qualified for automotive applications. AUTOMOTIVE PRODUCTS The ADG4W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. 28 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D685--3/(B) Rev. B Page 6 of 6