Application Note Leveraging High-Accuracy Models to Achieve First Pass Success in Power Amplifier Design Overview Nonlinear transistor models enable designers to concurrently optimize gain, power, efficiency, and modulation linearity over a desired operational bandwidth and temperature. While the use of such nonlinear models adds cost, the return on investment (ROI) can be justified by shortened development schedules and improved designer productivity. This application note illustrates the use of accurate nonlinear power transistor models to facilitate a first pass successful design flows for a power amplifier (PA)[1]. In this example, a two-stage telemetry amplifier was successfully designed in a single pass using NI AWR Design Environment, specifically Microwave Office circuit design software, and Modelithics model libraries, inclusive of Modelithics CLR and Modelithics-Qorvo GaN Library [2]. Nonlinear models and load-pull power device data, as well as other models for active devices, are provided by many device manufacturers. Yet, not all devices have suitably accurate models or data available. Thus, there is a cost associated with the development of high-accuracy models, whether the needed model is provided by the manufacturer, developed in-house by the design group, or developed by a third-party model provider [3][4]. Nonlinear Device Models Designing a PA requires trading off gain versus power, efficiency versus linearity, and return loss versus bandwidth [5][6]. Matching a nonlinear amplifier to load-pull derived source (Z S ) and load (Z L ) target impedances is straightforward for designing a narrowband, single-linear stage amplifier at a single bias point, but significantly more difficult when optimizing a multistage broadband amplifier. Assuming a nonlinear device model is available for the transistor(s) of interest, NI AWR Design Environment platform can accurately simulate nonlinear circuits, facilitating the design of the input and output matching circuits to optimize gain, output power, efficiency, modulation linearity, and even harmonic levels across the entire frequency band. Unfortunately, few manufacturers supply nonlinear models for all of their devices, leaving engineers to decide whether to develop their own nonlinear model, contract for development of a custom nonlinear transistor model by a third-party model provider such as Modelithics, or rely on the Z S and Z L provided in the device datasheet and then build and optimize the prototype on the bench. Amplifier Example The requirements for the medium power telemetry transmitter PA example in this application note include: Frequency range of 2200-2400 MHz Minimum output power of 1 W at 85 C Maximum current draw of 300 ma at 12 V Output power design goal of 32 dbm at 25 C (see note below) Footprint not to exceed 2.8 sq in Note: Adding the insertion loss of the harmonic filter [1] and desired design margin yielded a final stage output power design goal of 32 dbm at 25 C. Because the shaped offset quadrature phase-shift keying (SOQPSK) modulation for this application was constant amplitude, the amplifier was operated in a compressed mode. The allowable size for the complete transmitter was 2.8 sq in, with 0.5 sq in allocated to the driver and final stage RF circuitry. ni.com/awr
The Qorvo TGF2965-SM, which is an input matched 32 V gallium nitride (GaN) transistor rated at 6.0 W, was chosen for this application. The small size and integrated input match on this device were important for meeting the stringent size requirements of this transmitter, and the surface mount package facilitated manufacturing. Because of its small size, high gain, and low current consumption, the TGF2965-SM was also chosen for the driver stage on this transmitter. This was more than needed for this 1 W application but worked well when operated at a lower supply voltage. It was also appropriate when operated at the recommended supply voltage for a higher power 6 W version described below. This design (Figure 1) also incorporated a bandpass filter to reduce the transmit noise level at GPS L1 and L2 bands. Figure 1: Transmitter amplifier block diagram. Matching The first effort was to determine the optimal input and output match, which produced the desired gain, output power, and efficiency across the operating frequency. Typically, without nonlinear models, this is completed using a load-pull setup, or manufacturer published Z S and Z L load impedance. In the absence of a nonlinear model or load-pull data, knowledgeable designers can for some applications proceed to achieve reasonable starting point designs using load-line methods combined with small-signal data [7]. When an accurate nonlinear model exists for the transistor of interest, it is then possible to directly optimize the transistor circuit for performance. Starting with a nonlinear model provided by Modelithics for the Qorvo TGF2965-SM device, the final stage input and output match was optimized for performance across the 2200-2400 MHz operating bandwidth using the harmonic balance tuner (HBTUNER) within NI AWR Design Environment, specifically Microwave Office software (Figure 2). Figure 2: Final stage schematic with HBTUNER in place of actual load matching circuit. To allow for higher power versions of this transmitter with minimal changes to the circuitry, the output match was optimized to maintain high efficiency at 32 dbm output power at a reduced drain voltage of 12 V. Optimizing gain, output power, and efficiency at this substantially lower Vdd is only possible due to the accurate nonlinear transistor models. However, this was not done for the effort described below in which a 32 V optimized model actually worked quite well at 12 V.
Figure 3 shows nearly +33 dbm output power at 61 percent efficiency and compressed gain of 11 db at an input power of +22 dbm. The plot also shows the decrease in output power and efficiency, and the increase in gain as the input power is reduced in 2 db steps to 16 dbm. No attempt was made to optimize the matching at the harmonic frequencies for even higher efficiency. The optimized output load impedance was determined at 2.3 GHz. This was used as a design goal when the HBTUNER was replaced by actual output circuitry. Minimizing the overlap between non-zero current and non-zero voltage is the key to optimizing transistor efficiency through waveform engineering. The nonlinear transistor model utilized in this simulation provided an inspection node that enabled visualization of the simulated voltage and currents at the intrinsic ports of the transistor model. This facilitated efficiency optimization when used in concert with the HBTUNER tool. Figure 4 shows that the drain voltage for the final stage design is at a maximum when the drain current is at a minimum, indicating high efficiency. Figure 3: Final stage gain, output power, efficiency at Vdd = 12 V, Pin +16 to +22 dbm. The next step was to replace the HBTUNER tool with discrete and distributed components to present the same optimal Z L to the transistor drain, and then re-optimize the input and output match for optimal performance across the operating frequency, as shown in Figure 5. The series inductors were used in the output match instead of a transmission line to reduce the physical layout area and to facilitate implementation of higher power amplifier versions using the same PCB. The optimization of the best values for the surface mount capacitors, inductors, and resistors included in the matching bias and stabilization networks was facilitated with the part-value scalability of the Modelithics Global Microwave Models. Figure 4: Transistor die simulated drain voltage and current at intrinsic reference plane. Figure 5: Final stage amplifier, 1.5 W.
Design of Cascaded Amplifier After the final stage matching was complete, the driver stage and an interstage surface mount bandpass filter were introduced. The impedances of the matched driver and final stage circuits were close to 50 Ohms only at that center frequency. Given that most designs operate over a 10 percent or larger frequency bandwidth, a significant variation in gain, linearity, efficiency, and output power can be expected after cascading devices together due to the variation in source and load impedances presented by the devices to each another. Since nonlinear transistor models are available for the chosen transistor, it was straightforward to simultaneously optimize the cascaded non-50-ohm driver stage output match, bandpass filter, and final stage input together using NI AWR Design Environment simulation capabilities (Figure 6). Figure 6: Amplifier schematic. As shown in Figure 7, the simulated gain, output power, and efficiency are flat across the frequency band as the input power is increased in 2 db steps from 0 to +8 dbm at a drain voltage of +12 V. The levels outside of the passband are reduced by the bandpass filter. At a drive level of +8 dbm, the gain of the cascaded stages is over 3 db compressed at 24.4 db, the output power is 32.5 dbm, and the multi-stage efficiency is 47.8 percent, thereby meeting the design goals. Recall that this design has a maximum current requirement of 300 ma at 12 V, at 32 dbm output power. The simulated current draw at +6 dbm input power, which produces 31.9 dbm output power, is 54 ma (driver) + 227 ma (final) = 281 ma, as shown in Figure 8. Knowing the current draw of the nonlinear components early in the design process provided assurance that the customer specifications would be met without building a prototype. Figure 7: Amplifier gain 1.5 W, output power, and efficiency after optimization for 12 V operation. Figure 8: Driver and final stage nonlinear current draw.
The level of the harmonics can be simulated using the nonlinear model, as shown in Figure 9. In this case, the final stage output match was adjusted slightly to compensate for the return loss of the harmonic filter and to reduce the level of the fourth harmonic. Given the simulated harmonic levels above, maximum permissible harmonic level of -25 dbm for the second and third, and -80 dbc for other harmonics, the requirements for the harmonic filter could be determined. Including a 5 - db margin, the design parameters for this filter are +13.5 dbm - (-30 dbm) = 44 db rejection across 4.4 to 7.2 GHz, +30.5 dbm - 85 dbc - 11.1 dbm = 66 db rejection 8.8 to 9.6 GHz, and 55 db rejection for higher frequencies. A combined discrete and distributed harmonic filter was designed to meet the above requirements and was incorporated into the simulation [1]. Figure 9: Simulated amplifier harmonics before adding harmonic rejection filter. Appending the filter to the output of the PA reduced the simulated level of the harmonics below the required levels. The ability to determine the requirements of the harmonic filter while still in the paper design phase was a key enabler for the successful first-pass transmitter design, since the harmonic filter was an integral part of the transmitter. High Power In order to provide for possible changes in product requirements, this 1.5 W amplifier was optimized with a drain voltage of +12 V. This facillitated an increase in power capability to 6 W with mimimal matching changes. In this example, the output power on this cascade can be increased to +38 dbm without changing the PCB by increasing the drain voltage on the driver and final stages from +12 V to +32 V and adjusting the values of the discrete components, as shown in Table 1. Item 1.5 W PA 6 W PA Transistor Drain Voltage 12 32 Drain Inductor L33 15 nh 8.7 nh Output Series Inductors L42 1.0 nh 3.9 nh Output Shunt Cap C2 0.6 pf 0.3 pf Table 1: Voltage and component value comparison. Figure 10 shows a compressed output power of +38 dbm at a nominal cascaded amplifier gain of 28 db, and efficiency of 48 percent for the 6 W, 32 V design version. Note the 2.5 db increase in gain due to the higher drain voltage, which reduces the need for additional gain stages to support the higher output power level. This is an excellent way to leverage the design effort into two distinct high efficiency amplifier products. From here, the designer can then optimize the circuit performance for a particular application given simulation capability and component models that accurately predict the operating performance: it is easy to redesign the amplifier for a different frequency band or power level to meet customer requirements. Although not required for this application, the degradation of the modulated transmit signal error vector magnitude (EVM) and increase in adjacent channel interference can be simulated using Visual System Simulator (VSS) system design software, since the bias points, matching, and drive levels have been determined. Figure 10: Output power and efficiency after optimization for 32 V operation.
PCB Fabrication and Measurement The RF amplifier portion described above was only a small section of this single board transmitter, which also included gate bias circuitry, synthesizer, modulator, attenuator, DC power converters and regulators, field-programmable gate array (FPGA), and more. However, these items are common from one transmitter to another, require minimal design effort, and entail minimal risk. When developing a new transmitter, Quasonix typically builds the entire transmitter, rather than prototypes, relying on the accuracy of the RF simulations, including the component models, to ensure success. The large-signal (compressed) gain of the cascaded driver, bandpass filter, and final stages were measured using short pigtails connected to the PCB, as shown in Figure 11. The final stage transistors were biased to the manufacturer s recommended 25 ma drain current at a 12 V drain voltage, while the driver stage was biased to 30 ma for additional gain. The pigtail insertion loss was de-embedded from the measured data. Figure 11: Fabricated board with pigtails (right). The S 21 at power levels of -10 dbm and +8 dbm (Figure 12) reveals very good agreement between the simulated and measured compressed gain in the 2.2 to 2.4 GHz filter passband. The higher measured gain at -10 dbm input power is a result of the sensitivity of the small-signal gain to the transistor bias current while operating in the linear range, and the fact that the simulation model was derived at 32 V operation instead of the 12 V bias in this design. The discrepancy between simulated and measured responses outside of the passband is due to sharper roll off of the actual filter compared to the S2P data file used in the simulation downloaded from the Mini-Circuits website. Figure 12: Simulated and measured power gain input power. The simulated and measured output power at +8 dbm input is in very close agreement across the filter passband, especially considering that the TGF2965-SM model was created based on the manufacturer s rated +32 V drain voltage, compared to the +12 V drain voltage used in this application. Additionally, the output power versus input power, provided in Figure 13, shows excellent agreement between simulated and measured output power, including gain compression at the higher power levels. The +12 V current draw shows excellent agreement at lower power levels and diverges slightly near compression. The measured efficiency is higher than simulated in the low to mid power range due to the higher gain (and thus higher output power) describe above. The data below does not include the harmonic filter losses. Figure 13: Output power, current, and efficiency vs. input power.
Conclusion Accurate simulations of microwave circuits can be computed if the component parasitics and nonlinearities are included in the simulations. Traditionally provided transistor Z S and Z L source and load impedances generally allow optimized design of a single stage amplifier at specific frequencies. Nonlinear transistor models facilitate the simultaneous optimization of gain, output power, efficiency, and linearity across the desired frequency band even for cascaded amplifiers. These models can substantially reduce the development schedule and cost for new amplifier programs. In the presented two-stage, 1 W PA example, a first pass design success was realized with excellent measured to simulated agreement and rapid cycle time. With this approach, an existing design can be easily optimized to meet other customer requirements with minimal development cost and risk. References [1] T. Longshore and L. Dunleavy, Using High Accuracy Models to Achieve First Pass Success- A Transmitter Case Study: Part 2, Power Amplifier Design, High Frequency Electronics, September 2017. [2] L. Dunleavy, H. Morales, C. Suckling and K. Tran, Device and PA Circuit Level Validation of a High Power GaN Model Library, Microwave Journal, Aug. 2016. See also https://www.modelithics.com/mvp/qorvo. [3] Mike Golio and Jim Cozzie, Who Pays for Characterization?: The Final Dilemma for MESFET Modeling, 48 th ARFTG Conference Digest, Fall 1996. [4] L. Dunleavy, Modeling-The Hot Potato In the RF & Microwave Industry, Microwave Product Digest, April 2002. [5] S. Cripps, RF Power Amplifiers for Wireless Communications, Artech House, 1999. [6] F. Giannini and G. Leuzzi, Nonlinear Microwave Circuit Design, John WiIey & Sons, 2004. [7] S. C. Cripps, A Theory for the Prediction of GaAs Load-pull Power Contours, IEEE MTT-S Int l Microwave Symposium Digest, 1983, pp221-223. Special thanks to Ted Longshore of Quasonix and Larry Dunleavy of Modelithics for their technical article published in High Frequency Electronics in September 2017 titled Using High Accuracy Models to Achieve First Pass Success A Transmitter Case Study: Part 2: Power Amplifier Design, which inspired the creation of this first-pass success example. 2018 National Instruments Corporation. All rights reserved. AWR, AWR Design Environment, Microwave Office, National Instruments, NI, and ni.com are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies. AN-M-FST-PSS-2018.5.11