HSMP - 389x & HSMP - 89x Series Surface Mount R PIN Switch iodes ata Sheet escription The HSMP-389x series is optimized for switching applications where low resistance at low current and low capacitance are required. The HSMP-89x series products feature ultra low parasitic inductance. These products are specifically designed for use at frequencies which are much higher than the upper limit for conventional PIN diodes. Pin onnections and Package Marking 3 GUx 6 5 Notes:. Package marking provides orientation, identification, and date code.. See lectrical Specifications for appropriate package marking. eatures Unique onfigurations in Surface Mount Packages Add lexibility Save Board Space Reduce ost Switching Low apacitance Low Resistance at Low urrent Low ailure in Time (IT) Rate [] Matched iodes for onsistent Performance Better Thermal onductivity for Higher Power issipation Lead-free Option Available Note:. or more information see the Surface Mount PIN Reliability ata Sheet.
Package Lead ode Identification, SOT-3/3 (Top View) Package Lead ode Identification, SOT-33 (Top View) Package Lead ode Identification, SOT-363 (Top View) SINGL SRIS SINGL SRIS UNONNT TRIO 6 5 UAL SWITH MOL 6 5 # OMMON ANO # OMMON ATHO B OMMON ANO OMMON ATHO 3 L LOW INUTAN SINGL 6 5 3 R SRISÐ SHUNT PAIR 6 5 #3 # UNONNT PAIR #5 UAL ANO 89 UAL ANO 89B 3 T HIGH RQUNY SRIS 6 5 3 U 3 V S WARNING: Handling Precautions Should Be Taken To Avoid Static ischarge. Absolute Maximum Ratings [] T = +5 Symbol Parameter Unit SOT-3/3 SOT-33/363 If orward urrent ( µs Pulse) Amp P IV Peak Inverse Voltage V T j Junction Temperature 5 5 T stg Storage Temperature -65 to 5-65 to 5 θ jc Thermal Resistance [] /W 5 5 Notes:. Operation in excess of any one of these conditions may result in permanent damage to the device.. T = +5, where T is defined to be the temperature at the package pins where contact is made to the circuit board.
lectrical Specifications, T = 5, each diode Part Number HSMP- 389 389 3893 389 3895 389B 389 389 389 389L 389R 389T 389U 389V Test onditions Package Marking ode G G G3 G G5 G G G3 G GL S Z GU GV Lead ode 3 5 B L R T U V onfiguration Single Series ommon Anode ommon athode Unconnected Pair Single Series ommon Anode ommon athode Unconnected Trio ual Switch Mode Low Inductance Single Series-Shunt Pair High requency Series Pair Minimum Breakdown Voltage V BR (V) Maximum Series Resistance R S (Ω).5.3 V R = V BR Measure I R µa I = 5 ma f = MHz Maximum Total apacitance T (p) V R = 5 V f = MHz High requency (Low Inductance, 5 MHz 3 GHz) PIN iodes Part Number HSMP- Package Marking ode [] onfiguration Minimum Breakdown Voltage V BR (V) Maximum Series Resistance R S (Ω) Typical Total apacitance T (p) Maximum Total apacitance T (p) Typical Total Inductance L T (nh) 89x GA ual Anode.5.33.375. Test onditions V R = V BR Measure I R µa I = 5 ma f = MHz V R = 5 V V R = 5 V f = MHz f=5 MHz 3 GHz Typical Parameters at T = 5 Part Number HSMP- Series Resistance R S (Ω) arrier Lifetime τ (ns) 389x 3.8. @ 5V Test onditions I = ma f = MHz I = ma I R = 6 ma Total apacitance T (p)
HSMP-389x Series Typical Performance, T = 5, each diode R RSISTAN (OHMS)... I - ORWAR BIAS URRNT (ma) igure. Total R Resistance at 5 vs. orward Bias urrent. TOTAL APAITAN (p).55.5.5..35.3.5 GHz MHz. 8 6 V R - RVRS VOLTAG (V) igure. apacitance vs. Reverse Voltage. INPUT INTRPT POINT (dbm) 5 5 95 9 iode Mounted as a Series Attenuator in a 5 Ohm Microstrip and Tested at 3 MHz 85 3 I - ORWAR BIAS URRNT (ma) igure 3. nd Harmonic Input Intercept Point vs. orward Bias urrent. T rr - RVRS ROVRY TIM (ns) 6 8 V R = - V V R = - 5V V R = - V 5 5 3 I - ORWAR URRNT (ma). 5 5-5....6.8.. ORWAR URRNT (ma) igure. Typical Reverse Recovery Time vs. Reverse Voltage. V - ORWAR VOLTAG (V) igure 5. orward urrent vs. orward Voltage. Typical Applications for Multiple iode Products 3 3 "ON" "O" +V -V 5 6 3 b b b3 5 6 R in R out igure 6. HSMP-389L used in a SP3T Switch. igure 7. HSMP-389L Unconnected Trio used in a ual Voltage, High Isolation Switch.
Typical Applications for Multiple iode Products (continued) "ON" "O" +V +V R out 6 5 6 5 R in 3 R out 3 R in igure 8. HSMP-389L Unconnected Trio used in a Positive Voltage, High Isolation Switch. igure 9. HSMP-389T used in a Low Inductance Shunt Mounted Switch. Bias Xmtr Ant λ Rcvr Bias Xmtr Ant λ Rcvr Bias PA bias Xmtr Antenna λ HSMP-389V LNA HSMP-389U λ Rcvr igure. HSMP-389U Series/Shunt Pair used in a 9 MHz Transmit/Receive Switch. igure. HSMP-389V Series/Shunt Pair used in a.8 GHz Transmit/Receive Switch.
Typical Applications for Multiple iode Products (continued) R OMMON R OMMON R R R R BIAS BIAS BIAS BIAS igure. Simple SPT Switch, Using Only Positive urrent. igure 3. High Isolation SPT Switch, ual Bias. R OMMON R OMMON BIAS R R R BIAS R igure. Switch Using Both Positive and Negative Bias urrent. igure 5. Very High Isolation SPT Switch, ual Bias.
Typical Applications for HSMP-89x Low Inductance Series Microstrip Series onnection for HSMP-89x Series In order to take full advantage of the low inductance of the HSMP 89x series when using them in series applications, both lead and lead should be connected together, as shown in igure 7. 3 5 OHM MIROSTRIP LINS PA ONNT TO GROUN BY TWO VIA HOLS HSMP-89x igure 8. ircuit Layout. igure 6. Internal onnections..5 nh.5 nh.3 p igure 7. ircuit Layout..3 nh Microstrip Shunt onnections for HSMP-89x Series In igure 8, the center conductor of the microstrip line is interrupted and leads and of the HSMP-89x diode are placed across the resulting gap. This forces the.5 nh lead inductance of leads and to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The.3 nh of shunt inductance external to the diode is created by the via holes, and is a good estimate for.3 thick material. o-planar Waveguide Shunt onnection for HSMP-89x Series o-planar waveguide, with ground on the top side of the printed circuit board, is shown in igure. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. o-planar Waveguide Groundplane enter onductor Groundplane.3 nh igure 9. quivalent ircuit. quivalent ircuit Model: HSMP-389x hip* R s R j.5 Ω j. p* * Measured at - V R T =.5 + R j T = P + R j igure. ircuit Layout. R j = Ω I.9 I = orward Bias urrent in ma * See AN for package models.3 p A SPI model is not available for PIN diodes as SPI does not provide for a key PIN diode characteristic, carrier lifetime..75 nh igure. quivalent ircuit.
Assembly Information.39 igure. Recommended PB Pad Layout for Avago Technologies S7 6L / SOT-363 Products..39 igure 3. Recommended PB Pad Layout for Avago Technologies S7 3L / SOT-33 Products..39.6.6.8..79.79.39.79. SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. omponents with a low mass, such as the SOT package, will reach solder reflow temperatures faster than those with a greater mass. Avago Technologies diodes have been qualified to the time-temperature profile shown in igure 6. This profile is representative of an IR reflow type of surface mount assembly process. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (T MAX ) should not exceed 35. These parameters are typical for a surface mount assembly process for Avago Technologies diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder..35.9 5 T MAX IMNSIONS IN inches mm.3.8 igure. Recommended PB Pad Layout for Avago Technologies SOT-3 Products. TMPRATUR ( ) 5 5 Preheat Zone Reflow Zone ool own Zone..85.79.33.85 6 TIM (seconds) igure 6. Surface Mount Assembly Profile. 8 3.6.5.7.8.8...9.33.85.7..3.8.33.85 IMNSIONS IN inches mm igure 5. Recommended PB Pad Layout for Avago Technologies SOT-3 Products.
Package imensions Outline SOT-363 (S-7 6 Lead) Symbol Agilent (New) MIN (mm) MAX (mm).... H.. A.. A. A. Q.. e. BS b.. c.. L.. Outline SOT-33 (S-7 3 Lead) e A e XXX B A L AGILNT SYMBOL MIN MAX A. A. B........ e e. typical. typical.. L. typical
Outline 3 (SOT-3) e e e XXX B A SYMBOL AGILNT MIN MAX A.. A. B........ e.. e.. e.... L.. A Outline 3 (SOT-3) e XXX e A B L AGILNT SYMBOL MIN MAX A.. A.. B.. B........ e.. e.. e.... L.. A
evice Orientation RL or Outlines SOT-3, -33 TOP VIW mm N VIW ARRIR TAP 8 mm AB AB AB AB USR IRTION OVR TAP Note: "AB" represents package marking code. "" represents date code. or Outline SOT-3 or Outline SOT-363 TOP VIW N VIW TOP VIW N VIW mm mm 8 mm AB AB AB AB 8 mm AB AB AB AB Note: "AB" represents package marking code. "" represents date code. Note: "AB" represents package marking code. "" represents date code. Tape imensions and Product Orientation or Outline SOT-3 P P P W t 9 MAX Ko 8 MAX 3.5 MAX A B AVITY PRORATION ARRIR TAP SRIPTION SYMBOL SIZ (mm) SIZ (INHS) LNGTH WITH PTH PITH BOTTOM HOL IAMTR IAMTR PITH POSITION WITH THIKNSS A B K P P W t 3.5 ±..77 ±.. ±.. ±.. +.5.5 +.. ±..75 ±. 8. +.3..9 ±.3. ±..9 ±..8 ±..57 ±..39 ±..59 +..57 ±..69 ±..35 +...9 ±.5 ISTAN BTWN NTRLIN AVITY TO PRORATION (WITH IRTION) AVITY TO PRORATION (LNGTH IRTION) P 3.5.5. ±.5.38 ±..79 ±.
Tape imensions and Product Orientation or Outline SOT-3 P P P W t 9 MAX K 9 MAX A B AVITY PRORATION SRIPTION SYMBOL SIZ (mm) SIZ (INHS) LNGTH WITH PTH PITH BOTTOM HOL IAMTR IAMTR PITH POSITION A B K P P 3.9 ±..8 ±..3 ±.. ±.. +.5.5 +.. ±..75 ±..6 ±.. ±..5 ±..57 ±..39 +..59 +..57 ±..69 ±. ARRIR TAP WITH THIKNSS W t 8. +.3..5 ±.3.35+... ±.5 ISTAN AVITY TO PRORATION (WITH IRTION) AVITY TO PRORATION (LNGTH IRTION) P 3.5 ±.5. ±.5.38 ±..79 ±. or Outlines SOT-33, -363 P P P W t (ARRIR TAP THIKNSS) T t (OVR TAP THIKNSS) An K An A B AVITY PRORATION ARRIR TAP OVR TAP ISTAN ANGL SRIPTION SYMBOL SIZ (mm) SIZ (INHS) LNGTH WITH PTH PITH BOTTOM HOL IAMTR IAMTR PITH POSITION WITH THIKNSS WITH TAP THIKNSS AVITY TO PRORATION (WITH IRTION) AVITY TO PRORATION (LNGTH IRTION) A B K P P W t Tt P. ±.. ±.. ±.. ±.. +.5.55 ±.5. ±..75 ±. 8. ±.3.5 ±. 5. ±..6 ±. 3.5 ±.5. ±.5 OR SOT-33 (S7-3 LA) An 8 MAX OR SOT-363 (S7-6 LA) MAX.9 ±..9 ±..7 ±..57 ±..39 +..6 ±..57 ±..69 ±..35 ±.. ±.8.5 ±..5 ±..38 ±..79 ±.
Ordering Information Specify part number followed by option. or example: HSMP - 389x - XXX Bulk or Tape and Reel Option Part Number; x = Lead ode Surface Mount PIN Option escriptions -BLK = Bulk, pcs. per antistatic bag -TR = Tape and Reel, 3 devices per 7 reel -TR = Tape and Reel,, devices per 3 reel Tape and Reeling conforms to lectronic Industries RS-8, Taping of Surface Mounted omponents for Automated Placement. or lead-free option, the part number will have the character G at the end, eg. -TRG for a K pc lead-free reel. Package haracteristics Lead Material... opper (SOT-33/363); Alloy (SOT-3/3) Lead inish... Tin-Lead 85-5% (Non lead-free option)... Tin % (Lead-free option) Maximum Soldering Temperature... 6 for 5 seconds Minimum Lead Strength... pounds pull Typical Package Inductance... nh Typical Package apacitance...8 p (opposite leads) or product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. ata subject to change. opyright 6 Avago Technologies Pte. All rights reserved. 5989-386N - March 9, 6 3