Agilent HSMP-389x & HSMP-89x Series Surface Mount RF PIN Switch Diodes Data Sheet Features Description The HSMP-389x series is optimized for switching applications where low resistance at low current and low capacitance are required. The HSMP-89x series products feature ultra low parasitic inductance. These products are specifically designed for use at frequencies which are much higher than the upper limit for conventional PIN diodes. Pin Connections and Package Marking 3 GUx Notes:. Package marking provides orientation, identification, and date code.. See lectrical Specifications for appropriate package marking. 6 5 Unique Configurations in Surface Mount Packages Add Flexibility Save Board Space Reduce Cost Switching Low Capacitance Low Resistance at Low Current Low Failure in Time (FIT) Rate [] Matched Diodes for Consistent Performance Better Thermal Conductivity for Higher Power Dissipation Lead-free Option Available Note:. For more information see the Surface Mount PIN Reliability Data Sheet.
Package Lead Code Identification, SOT-3/3 (Top View) Package Lead Code Identification, SOT-33 (Top View) Package Lead Code Identification, SOT-363 (Top View) SINGL SRIS SINGL SRIS UNCONNCTD TRIO 6 5 DUAL SWITCH MODL 6 5 # COMMON ANOD # COMMON CATHOD B COMMON ANOD C COMMON CATHOD 3 L LOW INDUCTANC SINGL 6 5 3 R SRISÐ SHUNT PAIR 6 5 #3 # F UNCONNCTD PAIR #5 DUAL ANOD 89 DUAL ANOD 89B 3 T HIGH FRQUNCY SRIS 6 5 3 U 3 V Absolute Maximum Ratings [] T C = +5 C Symbol Parameter Unit SOT-3/3 SOT-33/363 I f Forward Current ( µs Pulse) Amp P IV Peak Inverse Voltage V T j Junction Temperature C 5 5 T stg Storage Temperature C -65 to 5-65 to 5 θ jc Thermal Resistance [] C/W 5 5 SD WARNING: Handling Precautions Should Be Taken To Avoid Static Discharge. Notes:. Operation in excess of any one of these conditions may result in permanent damage to the device.. T C = +5 C, where T C is defined to be the temperature at the package pins where contact is made to the circuit board.
lectrical Specifications, T C = 5 C, each diode Package Minimum Maximum Maximum Part Number Marking Lead Breakdown Series Resistance Total Capacitance HSMP- Code Code Configuration Voltage V BR (V) R S (Ω) C T (pf) 389 G [] Single.5.3 389 G [] Series 3893 G3 [] 3 Common Anode 389 G [] Common Cathode 3895 G5 [] 5 Unconnected Pair 389B G [] B Single 389C G [] C Series 389 G3 [] Common Anode 389F G [] F Common Cathode 389L GL [] L Unconnected Trio 389R S [] R Dual Switch Mode 389T Z [] T Low Inductance Single 389U GU [] U Series-Shunt Pair 389V GV [] V High Frequency Series Pair Test Conditions V R = V BR I F = 5 ma V R = 5 V Measure f = MHz f = MHz I R µa Notes:. Package marking code is white.. Package is laser marked. High Frequency (Low Inductance, 5 MHz 3 GHz) PIN Diodes Minimum Maximum Typical Maximum Typical Part Package Breakdown Series Total Total Total Number Marking Voltage Resistance Capacitance Capacitance Inductance HSMP- Code [] Configuration V BR (V) R S (Ω) C T (pf) C T (pf) L T (nh) 89x GA Dual Anode.5.33.375. Test Conditions V R = V BR I F = 5 ma f = MHz V R = 5 V f = 5 MHz Measure V R = 5 V f = MHz 3 GHz I R µa Note:. SOT-3 package marking code is white; SOT-33 is laser marked. Typical Parameters at T C = 5 C Part Number Series Resistance Carrier Lifetime Total Capacitance HSMP- R S (Ω) τ (ns) C T (pf) 389x 3.8. @ 5 V Test Conditions I F = ma I F = ma f = MHz I R = 6 ma 3
HSMP-389x Series Typical Performance, T C = 5 C, each diode RF RSISTANC (OHMS)... I F - FORWARD BIAS CURRNT (ma) Figure. Total RF Resistance at 5 C vs. Forward Bias Current. TOTAL CAPACITANC (pf).55.5.5..35.3 MHz.5 GHz. 8 6 V R - RVRS VOLTAG (V) Figure. Capacitance vs. Reverse Voltage. INPUT INTRCPT POINT (dbm) 5 5 95 9 Diode Mounted as a Series Attenuator in a 5 Ohm Microstrip and Tested at 3 MHz 85 3 I F - FORWARD BIAS CURRNT (ma) Figure 3. nd Harmonic Input Intercept Point vs. Forward Bias Current. T rr - RVRS RCOVRY TIM (ns) 6 8 V R = - V V R = - 5V V R = - V 5 5 3 I F - FORWARD CURRNT (ma). 5 C 5 C - 5 C....6.8.. FORWARD CURRNT (ma) Figure. Typical Reverse Recovery Time vs. Reverse Voltage. V F - FORWARD VOLTAG (V) Figure 5. Forward Current vs. Forward Voltage. Typical Applications for Multiple Diode Products 3 3 "ON" "OFF" +V -V 5 6 3 b b b3 5 6 RF in RF out Figure 6. HSMP-389L used in a SP3T Switch. Figure 7. HSMP-389L Unconnected Trio used in a Dual Voltage, High Isolation Switch.
Typical Applications for Multiple Diode Products (continued) "ON" "OFF" +V +V RF out 6 5 6 5 RF in 3 RF out 3 RF in Figure 8. HSMP-389L Unconnected Trio used in a Positive Voltage, High Isolation Switch. Figure 9. HSMP-389T used in a Low Inductance Shunt Mounted Switch. Bias Xmtr C Ant λ C Rcvr Bias Xmtr Ant λ Rcvr Bias PA bias Xmtr Antenna λ HSMP-389V LNA HSMP-389U λ Rcvr Figure. HSMP-389U Series/Shunt Pair used in a 9 MHz Transmit/Receive Switch. Figure. HSMP-389V Series/Shunt Pair used in a.8 GHz Transmit/Receive Switch. 5
Typical Applications for Multiple Diode Products (continued) RF COMMON RF COMMON RF RF RF RF BIAS BIAS BIAS BIAS Figure. Simple SPDT Switch, Using Only Positive Current. Figure 3. High Isolation SPDT Switch, Dual Bias. RF COMMON RF COMMON BIAS RF RF RF BIAS RF Figure. Switch Using Both Positive and Negative Bias Current. Figure 5. Very High Isolation SPDT Switch, Dual Bias. 6
Typical Applications for HSMP-89x Low Inductance Series Microstrip Series Connection for HSMP-89x Series In order to take full advantage of the low inductance of the HSMP-89x series when using them in series applications, both lead and lead should be connected together, as shown in Figure 7. 3 5 OHM MICROSTRIP LINS Figure 8. Circuit Layout. PAD CONNCTD TO GROUND BY TWO VIA HOLS Co-Planar Waveguide Shunt Connection for HSMP-89x Series Co-Planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. HSMP-89x Figure 6. Internal Connections..5 nh.5 nh.3 pf Co-Planar Waveguide Groundplane Center Conductor Groundplane.3 nh.3 nh Figure. Circuit Layout. Figure 7. Circuit Layout. Figure 9. quivalent Circuit..3 pf Microstrip Shunt Connections for HSMP-89x Series In Figure 8, the center conductor of the microstrip line is interrupted and leads and of the HSMP-89x diode are placed across the resulting gap. This forces the.5 nh lead inductance of leads and to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The.3 nh of shunt inductance external to the diode is created by the via holes, and is a good estimate for.3" thick material. quivalent Circuit Model HSMP-389x Chip* R s.5 Ω R T =.5 + R j C T = C P + R j R j = Ω I.9 R j C j. pf* * Measured at - V I = Forward Bias Current in ma * See AN for package models Figure. quivalent Circuit..75 nh A SPIC model is not available for PIN diodes as SPIC does not provide for a key PIN diode characteristic, carrier lifetime. 7
Assembly Information.39 Figure. Recommended PCB Pad Layout for Agilent s SC7 6L / SOT-363 Products..39 Figure 3. Recommended PCB Pad Layout for Agilent s SC7 3L / SOT-33 Products..39.35.9.6.6.8..79.3.8.79.39.79. SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT package, will reach solder reflow temperatures faster than those with a greater mass. Agilent s diodes have been qualified to the timetemperature profile shown in Figure 6. This profile is representative of an IR reflow type of surface mount assembly process. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or 5 more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (T MAX ) should not exceed 35 C. These parameters are typical for a surface mount assembly process for Agilent diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. T MAX DIMNSIONS IN Figure. Recommended PCB Pad Layout for Agilent s SOT-3 Products...85.79.6.5.7.8 inches mm.8..33.85.33.85..9 TMPRATUR ( C) 5 5 6 Preheat Zone Figure 6. Surface Mount Assembly Profile. Reflow Zone Cool Down Zone 8 3 TIM (seconds).7..3.8.33.85 DIMNSIONS IN inches mm Figure 5. Recommended PCB Pad Layout for Agilent s SOT-3 Products. 8
Package Dimensions Outline SOT-363 (SC-7 6 Lead) Symbol Agilent (New) MIN (mm) MAX (mm).5.35 D.8.5 H.8. A.8. A.8 A. Q.. e.65 BCS b.5.3 c.. L..3 Outline SOT-33 (SC-7 3 Lead) e A e XXX D B A C L AGILNT SYMBOL MIN MAX A.8 A B.5. C.. D.8.5.. e e.65 typical.3 typical.8. L.5 typical 9
Outline 3 (SOT-3) e e e XXX D B A C SYMBOL AGILNT MIN MAX A.79. A. B.37.5 C.86.5 D.73 3.3.5.5 e.89. e.78. e.5.6..7 L.5.69 A Outline 3 (SOT-3) e XXX e D A B C L AGILNT SYMBOL MIN MAX A.79.97 A.3. B.36.5 B.76.9 C.86.5 D.8 3.6.. e.89. e.78. e.5.6..65 L.5.69 A
Device Orientation RL For Outlines SOT-3, -33 TOP VIW mm ND VIW CARRIR TAP 8 mm ABC ABC ABC ABC USR FD DIRCTION COVR TAP Note: "AB" represents package marking code. "C" represents date code. For Outline SOT-3 For Outline SOT-363 TOP VIW ND VIW TOP VIW ND VIW mm mm 8 mm ABC ABC ABC ABC 8 mm ABC ABC ABC ABC Note: "AB" represents package marking code. "C" represents date code. Note: "AB" represents package marking code. "C" represents date code. Tape Dimensions and Product Orientation For Outline SOT-3 P D P P F W t D 9 MAX Ko 8 MAX 3.5 MAX A B CAVITY PRFORATION CARRIR TAP DISTANC BTWN CNTRLIN DSCRIPTION SYMBOL SIZ (mm) SIZ (INCHS) LNGTH WIDTH DPTH PITCH BOTTOM HOL DIAMTR DIAMTR PITCH POSITION WIDTH THICKNSS CAVITY TO PRFORATION (WIDTH DIRCTION) CAVITY TO PRFORATION (LNGTH DIRCTION) A B K P D D P W t F P 3.5 ±..77 ±.. ±.. ±.. +.5.5 +.. ±..75 ±. 8. +.3..9 ±.3 3.5.5. ±.5. ±..9 ±..8 ±..57 ±..39 ±..59 +..57 ±..69 ±..35 +...9 ±.5.38 ±..79 ±.
Tape Dimensions and Product Orientation For Outline SOT-3 P P D P F W t D 9 MAX K 9 MAX A B CAVITY PRFORATION DSCRIPTION SYMBOL SIZ (mm) SIZ (INCHS) LNGTH WIDTH DPTH PITCH BOTTOM HOL DIAMTR DIAMTR PITCH POSITION A B K P D D P 3.9 ±..8 ±..3 ±.. ±.. +.5.5 +.. ±..75 ±..6 ±.. ±..5 ±..57 ±..39 +..59 +..57 ±..69 ±. CARRIR TAP WIDTH THICKNSS W t 8. +.3..5 ±.3.35+... ±.5 DISTANC CAVITY TO PRFORATION (WIDTH DIRCTION) CAVITY TO PRFORATION (LNGTH DIRCTION) F P 3.5 ±.5. ±.5.38 ±..79 ±. For Outlines SOT-33, -363 P D P P C F W t (CARRIR TAP THICKNSS) D T t (COVR TAP THICKNSS) An K An A B CAVITY PRFORATION CARRIR TAP COVR TAP DISTANC ANGL DSCRIPTION SYMBOL SIZ (mm) SIZ (INCHS) LNGTH WIDTH DPTH PITCH BOTTOM HOL DIAMTR A B K P D. ±.. ±.. ±.. ±.. +.5.9 ±..9 ±..7 ±..57 ±..39 +. DIAMTR D.55 ±.5.6 ±. PITCH P. ±..57 ±. POSITION.75 ±..69 ±. WIDTH W 8. ±.3.35 ±. THICKNSS t.5 ±.. ±.8 WIDTH C 5. ±..5 ±. TAP THICKNSS Tt.6 ±..5 ±. F 3.5 ±.5.38 ±. CAVITY TO PRFORATION (WIDTH DIRCTION) CAVITY TO PRFORATION (LNGTH DIRCTION) P. ±.5 FOR SOT-33 (SC7-3 LAD) An 8 C MAX FOR SOT-363 (SC7-6 LAD) C MAX.79 ±.
Ordering Information Specify part number followed by option. For example: HSMP - 389x - XXX Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLK = Bulk, pcs. per antistatic bag -TR = Tape and Reel, 3 devices per 7" reel -TR = Tape and Reel,, devices per 3" reel Tape and Reeling conforms to lectronic Industries RS-8, Taping of Surface Mounted Components for Automated Placement. For lead-free option, the part number will have the character "G" at the end, eg. -TRG for a K pc lead-free reel. Package Characteristics Lead Material... Copper (SOT-33/363); Alloy (SOT-3/3) Lead Finish... Tin-Lead 85-5% (Non lead-free option)... Tin % (Lead-free option) Maximum Soldering Temperature... 6 C for 5 seconds Minimum Lead Strength... pounds pull Typical Package Inductance... nh Typical Package Capacitance....8 pf (opposite leads) 3
www.agilent.com/ semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: + (8) 35-3 or (8) 65-8675 urope: +9 () 6 96 China: 8 65 7 Hong Kong: (+65) 6756 39 India, Australia, New Zealand: (+65) 6755 939 Japan: (+8 3) 3335-85(Domestic/International), or -6-8(Domestic Only) Korea: (+65) 6755 989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 Taiwan: (+65) 6755 83 Data subject to change. Copyright 5 Agilent Technologies, Inc. Obsoletes 5989-86N May 6, 5 5989-5N