Course Introduction Purpose: This course provides an overview of the timer peripherals built into popular SH-2 and SH-2A families of 32-bit RISC microcontrollers, which are members of the SuperH series Objectives: Gain a basic knowledge of the capabilities, modes and applications of the multifunction timer pulse unit (MTU) Learn about the enhanced capabilities of the MTU2 and MTU2S peripherals in newer SH-2 and SH-2A devices Get details on the motor management timer, watchdog timer and compare-match timer Content: 24 pages 3 questions Learning Time: 35 minutes 1
SuperH Peripheral Functions SH7047 SuperH Series Microcontroller SH-2 SuperH 32-bit RISC CPU MAC32/DSP Function Multi-function Timer Pulse Unit Motor Management Timer Watchdog Timer Compare-Match Timer A/D Converter Advanced User Debugger Bus Interface I/O Ports FLASH Data Transfer Controller Bus State Controller High-performance User Debug Interface Clock Pulse Generator RAM Interrupt Controller User Break Controller Controller Area Network Function Serial Communication Interface Microcontrollers for embedded system applications require extensive on-chip peripherals to Minimize system chip count Reduce overall system cost Facilitate small system size, etc. Built-in peripheral functions must Provide required capabilities Deliver needed performance levels Offer design flexibility Maintain a basic commonality within product family, if possible Offer an acceptable cost-benefit compromise, etc.
Multi-function Timer Pulse Unit MTU: Provides multiple 16-bit timer channels Processes 16 pulse inputs/outputs Provides 8 clock inputs for each channel Offers standard and application-specific functions (input capture, output compare sets/toggles output, counter clearing, etc.) Has 8 operating modes Provides 2-phase encoder up/down count Delivers 15mA output current (can drive opto isolators directly) Is supported by a port-outputenable function Has an A/D converter trigger (with optional delay) Supports Module Stop mode SH704x MCU MTU Output Pin I OL =15mA Vcc Opto Isolator MTU Driving Opto Isolator
MTU Operating Modes Ordinary Timer mode Each channel uses a counter and general register to create timing events or measure timing signals Synchronized Timer mode Counters for multiple channels are synchronously preset Buffer mode For output-compare, next compare value is buffered For input-capture, previous capture value is buffered Two values can be captured or loaded in quick succession Cascade mode Channels 1 and 2 are combined in a cascade connection to form a 32-bit counter - Overflow for channel 1 serves as the clock for channel 2
MTU Operating Modes (cont d) Phase Counting TCNT operates as up/down counter, depending on phase of the external clock inputs for channels 1 and 2 PWM (mode 1) Output of PWM signal can vary between 0% and 100% duty cycle Reset Synchronized PWM (mode 2) Outputs up to 8 PWM signals Waveforms share transition point on one side of signal repetition Complementary PWM Outputs three positive and three negative PWM waveforms Waveforms are centered and have no overlap - Deadtime is inserted between signal switching operations
MTU Block Diagram
Buffer Mode Output-compare operation Comparator generates signal when match occurs Buffer Register Timer General Register Comparator TCNT Input-capture operation Input-capture signal Buffer Register Timer General Register TCNT
Phase Counting Mode TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Increment Decrement Time Performs quadrature encoding Used to measure rotary displacement of motor armature, etc. Phase Count Mode 1 Up/Down Counting Conditions TCLKA (channel 1) TCLKB (channel 1) Operation TCLKC (channel 2) TCLKD (channel 2) Increment 1 (high level) Rising edge 0 (low level) Falling edge Rising edge 0 (low level) Falling edge 1 (high level) Decrement 1 (high level) Falling edge 0 (low level) Rising edge Rising edge 1 (high level) Falling edge 0 (low level)
PWM Modes Basic PWM (Mode 1) Each edge defined by a compare-match 1 output per pair of general registers TCNT Value 0xFFFF TGRA TGRB 0x0000 TIOCA Counter clear by TGRA compare match Freerunning Counter Reset synchronized (Mode 2) 1 output per general register 7 PWMs from only 3 channels! Channels 0, 1, 2: MTU2 only TCNT Value 0xFFFF TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A 0x0000 TIOC0A Counter clear by TGR1B compare match Freerunning Counter MTU MTU can can generate up up to to a 12-channel PWM PWM TIOC0B TIOC0C TIOC0D TIOC1A
Complementary PWM Mode TGR3A TCDR TCNT value TGR4A TGR4C TCNT3 TCNT4 TDDR 0x0000 Output Deadtime Deadtime /Output
Data Updates Data update timing: counter crest and trough Counter value Transfers from temporary register to compare register TGR3A Buffer register TGR4C TGR4A Compare register TCNTS H 0000 BR data1 data2 data3 data4 data5 data6 Temp_R data1 data2 data3 data4 data5 data6 GR data1 data2 data3 data4 data6
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MTU2: 6-channel Timer Extra timer (channel 5) supports: External pulse width measurement of 3 inputs Using input-capture capabilities, the actual delay between the complementary outputs can be measured in real time Deadtime compensation Channel 5 maintains safety margin by adding extra delay if normal deadtime won t accommodate slow response of switching devices 13
The MTU2S Peripheral SH7206 MTU2 MTU2S M1 M2 Multi-function Timer pulse Unit 2S: Provides three 16-bit timers: duplicates of MTU2 channels 3, 4 and 5 Can operate at up to 100MHz when generating complimentary PWM waveforms, and at up to 33MHz when being used for other functions Allows a microcontroller that also has a MTU2 peripheral to control two 3-phase motors simultaneously 14
MTU Interrupts Interrupts can be generated at crests and troughs of the triangular counting waveform MTU2 offers an interrupt skipping feature: Interrupts TGI3A (crest) and TCI4 (trough) in channels 3 and 4 can be skipped up to 7 times Transfers from a buffer register to a temporary register or compare register can also be skipped A/D converter start requests can be skipped, as well 15
Sources of MTU Interrupts Interrupt Sources Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5* 7 sources 4 sources 4 sources 5 sources 5 sources 3 sources Input capture 0A Input capture 1A Input capture 2A Input capture 3A Input capture 4A Compare match 5U Input capture 0B Input capture 1B Input capture 2B Input capture 3B Input capture 4B Compare match 5V Input capture 0C Overflow Overflow Input capture 3C Input capture 4C Compare match 5W Input capture 0D Underflow Underflow Input capture 3D Input capture 4D Compare match 0E Overflow Overflow or underflow Compare match 0F Overflow * MTU2
Output Shutdown by POE2 Port Output Enable circuit (POE2): Provides a key safety feature, eliminates some external components Implements a protection circuit for inverters that shuts down the power drive Is triggered by an external input signal (9 channels available) Accepts a falling-edge or low-level signal an an input Places the high-current pins in a high-impedance state (tri-state condition) when their output levels are compared and a simultaneous lowlevel output continues for one cycle or more Provides detection flags on each input pin Can request an interrupt to alert the application Operates independent of the main clock (works even when clock fails)
3-Phase AC Motor Control Typical Motor Drive Application SH-2 or SH-2A CPU Ch 4 15mA Sink Drive H Bridge MTU or MTU2 Ch 3 Ch 2 Ch 1 M 3-Phase Output Ch 0 Watchdog Timer 10-bit A/D SCI SCI I/O Amp Current Detect (U and V phases) Control Panel EEPROM Quadrature Encoder Inputs ROM RAM
Motor Management Timer TPBR MMT_TDDR TDCNT0 TPDR Comparators Comparators MMT_TCNT Magnitude Comparators Control Circuit PCIO Clock PUOA PUOB PVOA PVOB PWOA PWOB TGRUU TGRUU TBRU TGRUU TGRUU TGRUU TGRUU MMT: Is a dedicated peripheral for driving motors included in some SH-2 series devices (SH7047, etc.) Outputs 6-phase PWM waveforms with non-overlap times TGRUU 19 TGRUU TGRUU MMT_TMDR TCNR TBRV TBRW MMT_TSR A/D start conversion
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Watchdog: Key Safety Feature Internal Reset Signal ITI (interrupt request signal) Internal Clock Sources Interrupt Control Clock Select Clock Reset Control WDTOVF Internal bus WTSCR Bus I/F WTCNT WDT: Can be used to detect/correct internal problems by restarting device and applications if software runaways, etc., occur Must be periodically tickled (set back to zero) to prevent an overflow that would generate an inadvertent reset signal Outputs a signal useful for resetting external devices Is driven by a choice of clocks Can also be used as an interval timer to generate a periodic interrupt to ensure clock settling times are met when changing CPG frequency of SH-2A device in CPG and when leaving software standby mode 21 Overflow Module bus WRCSR
Compare-Match Timer CMT: Provides 2 channels of 16-bit compare-match timers and operates from 4 selectable internal clock sources Can generate interrupts at programmed intervals (software schedulers, etc.) and trigger DMAC Can be stopped when not needed to reduce power CMI0 Counter Value 0x0000 CMI1 Counter cleared by compare-match, status / interrupt set. Compare constant register value Control Circuit Clock Selection Control Circuit Clock Selection CMSTR CMCSR_0 CMCOR_0 Comparator CMCNT_0 Channel 0 CMCSR_1 CMCOR_1 Comparator CMCNT_1 Channel 1 Module bus Bus I/F Internal bus
PROPERTIES On passing, 'Finish' button: On failing, 'Finish' button: Allow user to leave quiz: User may view slides after quiz: User may attempt quiz: Goes to Next Slide Goes to Next Slide At any time After passing quiz Unlimited times
Course Summary MTU features and modes MTU2 and MTU2S Motor control application MMT WDT CMT 24