Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

LETTER IEICE Electronics Express, Vol.15, No.7, 1 10 Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS Korkut Kaan Tokgoz a), Seitaro Kawai, Kenichi Okada, and Akira Matsuzawa Department of Physical Electronics, Tokyo Institute of Technology, 2 12 1 S3 27, Oookayama, Meguro-ward, Tokyo 152 8552, Japan a) korkut@ssc.pe.titech.ac.jp Abstract: A 60 GHz antenna switching architecture is presented for millimeter-wave transceivers. This circuit topology re-uses the last stage s transistor of power amplifier (PA) and the first stage s transistor of low-noise amplifier (LNA) as switches, and the matching blocks. A two-stage LNA and a two-stage PA are designed considering antenna switching operation in 65 nm CMOS. The method has lower loss than conventional switches in receiver mode. The most important advantage is no additional area penalty compared to conventional methods. 2.9 db minimum noise figure (NF) in the receiver mode is measured, and 2 dbm of OP 1dB is measured in the transmitter mode. Keywords: CMOS, mm-wave, MIMO, TX/RX switch, phased arrays Classification: Microwave and millimeter-wave devices, circuits, and modules References [1] R. Wu, et al.: 64-QAM 60-GHz CMOS transceivers for IEEE 802.11ad/ay, IEEE J. Solid-State Circuits 52 (2017) 2871 (DOI: 10.1109/JSSC.2017. 2740264). [2] J. Pang, et al.: A 128-QAM 60 GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance, ISSCC Dig. Tech. Papers (2017) 424 (DOI: 10.1109/ISSCC.2017.7870442). [3] T. Mitomo, et al.: A 2Gb/s-throughput CMOS transceiver chipset with inpackage antenna for 60 GHz short-range wireless communication, ISSCC Dig. Tech. Papers (2012) 266 (DOI: 10.1109/ISSCC.2012.6177010). [4] Y. A. Atesal, et al.: Low-loss 0.13-m CMOS 50 70 GHz SPDT and SP4T switches, IEEE RFIC Symp. (2009) 43 (DOI: 10.1109/RFIC.2009.5135486). [5] M. Uzunkol and G. M. Rebeiz: A low-loss 50 70 GHz SPDT switch in 90 nm CMOS, IEEE J. Solid-State Circuits 45 (2010) 2003 (DOI: 10.1109/JSSC. 2010.2057950). [6] L. Kuang, et al.: Co-design of 60-GHz wideband front-end IC with on-chip T/R switch based on passive macro-modeling, IEEE Trans. Microw. Theory Techn. 62 (2014) 2743 (DOI: 10.1109/TMTT.2014.2359415). [7] M. Uzunkol and G. M. Rebeiz: 140 220 GHz SPST and SPDT switches in 45 nm CMOS SOI, IEEE Microw. Compon. Lett. 22 (2012) 412 (DOI: 10. 1109/LMWC.2012.2206017). 1

[8] A. Ç. Ulusoy, et al.: A low-loss and high isolation D-band SPDT switch utilizing deep-saturated SiGe HBTs, IEEE Microw. Compon. Lett. 24 (2014) 400 (DOI: 10.1109/LMWC.2014.2313529). [9] K. K. Tokgoz, et al.: A low-loss 60 GHz integrated antenna switch in 65 nm CMOS, IEEE Radio-Frequency Integration Technology (2017) 50 (DOI: 10. 1109/RFIT.2017.8048286). [10] C. W. Byeon and C. S. Park: Design and analysis of the millimeter-wave SPDT switch for TDD applications, IEEE Trans. Microw. Theory Techn. 61 (2013) 2858 (DOI: 10.1109/TMTT.2013.2271613). [11] J. He, et al.: Analysis and design of 60-GHz SPDT switch in 130-nm CMOS, IEEE Trans. Microw. Theory Techn. 60 (2012) 3113 (DOI: 10.1109/TMTT. 2012.2211380). 1 Introduction 60 GHz millimeter-wave (mm-wave) region gets more attention due to larger available bandwidths [1, 2, 3]. Transmit/receive switch for a mm-wave multi- Gb/s system is an advantageous block when considering phased array and multiinput multi-output (MIMO) communication for sharing antennas [3, 4, 5, 6, 7, 8, 9, 10, 11]. It is crucial to decrease the silicon area consumption of switch, while, also, care should be taken for noise figure (NF) of receiver (RX), and linearity of transmitter (TX). Although there are other topologies for switch architecture [3, 10, 11], the common topology for antenna switch is based on quarter-wavelength (=4) [4, 5, 6, 7, 8]. The conventional switches has long =4 length (typically 600 to 700 µm in standard CMOS) transmission lines (TLs) which consumes relatively large area on-chip and introduce loss especially in mm-wave frequency region. For instance, the switch in [5] has one of the best performance in terms of loss in the literature. However, the area of the switch is 0.275 mm 2 and for an 8 8 MIMO system, 8 of this switch would consume a total area of 2.2 mm 2. Considering advanced manufacturing nodes, this would result in increased cost for silicon. A small area switch is presented in [3] based on balun architecture consuming a total area of 0.024 mm 2. Nevertheless, this topology has higher loss which affects the overall TX-to-RX communication performance. In here, an integrated antenna switch with PA and LNA is proposed and the concept is illustrated in Fig. 1. Here, a 60 GHz antenna switch is presented with no additional area consumption and low-loss, by re-using the last stage s transistor of PA and first stage s transistor of LNA and the matching blocks. Next section presents the design and analysis of the proposed integrated antenna switch architecture. In section 3, the measurement Test Element Groups (TEGs) are explained along with the measurement results. Finally, section 4 concludes the paper. Different than [9], in here, more explanations and analysis about the proposed TRX switch design is explained in detail. More simulations are included about isolation from TX to RX. Moreover, additional measurement structures and results are included in this letter. 2

Fig. 1. Concept of the integrated antenna (transmitter-receiver) switch. LNA first-stage transistor gate impedance for ON and OFF states and PA last-stage transistor drain impedance for ON and OFF states at 60 GHz. 2 Proposed integrated antenna switch The concept is illustrated in Fig. 1. In the proposed case, matching blocks of LNA input and PA output are designed along with the considerations of switching transistors impedance values when they are biased differently for TX and RX modes. The impedance values for the switching transistors are given in Fig. 1 and explained in detail below. The switching biases are different than most transmit/receive switches [3, 4, 5, 6, 7, 8, 9, 10, 11]. In these conventional switches, the switching transistors are biased either at 0 or 1 V. For the proposed work, in TX mode, the PA transistor gate biases are set to 0.7 V considering gain and linearity of TX whereas the LNA gate biases are 0 V. For both LNA and PA transistors drain voltage is 1 V either for ON or OFF cases. The size of the PA transistor is selected as 120 µm total width (2 m 60) for higher saturated output power and linearity. In RX mode, the LNA transistor gate biases are set to 0.55 V considering NF of RX whereas the PA gate biases are 0 V. Again, for both LNA and PA transistors drain voltage is 1 V either for ON or OFF cases. The size of the LNA transistor is selected 3

as 36 µm total width (1:5 m 24) for lower NF and gain. Fig. 1 represents the impedance seen from the gate of the first-stage transistor of LNA when the biases are 0.55 V for RX mode and 0 V for TX mode. Furthermore, the impedance seen from the drain of the last-stage transistor of PA when biases are 0 V for RX mode and 0.7 V for TX mode. Note that the ON/OFF impedance difference for LNA case is much higher than that of PA. Because of this reason and the importance of RX gain, and NF; the design of LNA input matching block has the priority. Considering both the ON and OFF impedances of LNA first-stage transistor, a matching block design is presented in Fig. 2. In the same figure the impedances at 60 GHz are indicated. Moreover, design is illustrated based on simulations on Smith Chart in Fig. 2(c). The impedance at the gate of the transistor are indicated as Z LNA,ON and Z LNA,OFF. A 150 ff DC cut capacitor is placed before the gate of the transistor for bias and a 115 µm TL is placed. The impedance seen from this point is indicated as before the shunt short-circuited TL. A 157.5 µm short-circuited stub is used to match the ON state impedance to 50 Ω and that impedance is indicated as. With the same stub, the OFF state impedance become inductive. However, in this case the ON/OFF ratio is not high as desired. Hence, another series 115 µm TL is placed. By this way, the ON state impedance still near 50 Ω whereas the OFF state impedance become higher than the previous case. The LNA input impedance labels are Z LNA-IN,ON and Z LNA-IN,OFF. Inductive load is required for the OFF state impedance because when PA and LNA are combined the parasitic capacitance of the pad (27 ff) has to be accounted. Fig. 2 presents the PA output matching block design. Similarly, the impedance transformations at 60 GHz are illustrated in the same figure. Moreover, the impedance transformations for the PA design is shown on Smith Chart in Fig. 2(d). Since the ON/OFF impedances seen from the drain side of the last-stage transistor of PA are very close, higher ON/OFF ratio is more difficult to design as compared to LNA case. The impedance at the drain of the transistor are indicated as Z PA,ON and Z PA,OFF. A load connected to VDD is used right after the drain and these impedances are labelled as Z PA1,ON and Z PA1,OFF. In order to block the DC flowing through the LNA and avoid VDD-GND short circuiting a 150 f F of DC cut capacitor is used before the antenna port. To match the impedances after the load and before the DC cut capacitor, a 170 µm open-circuited stub is used after a 170 µm series TL. These points are indicated as and fi in the schematic. Both LNA output port and PA input port are matched to 50 Ω. The PA and LNA are combined directly to a Tee-junction before the antenna port pad. The RX mode of the combined circuitry is shown in Fig. 3. Thanks to the high impedance of the PA when it is in OFF state, the loss to TX is calculated to be 1.31 db at 60 GHz. The antenna input impedance is very close to 50 Ω with very small reactive component. Hence, the loss due to reflection in RX mode of the antenna switch circuit is as small as 0.07 db. As a result, total loss in RX mode from antenna input to LNA input is 1.38 db. Similarly, the TX mode of the circuitry is shown in Fig. 3. In this case, the ON state impedance is close to OFF state and hence it is not well matched to 50 Ω mostly due to the required DC cut capacitor. The loss to RX from the PA (TX) output is calculated to be 1.91 db at 60 GHz due to the mentioned impedance mismatch. The antenna input impedance 4

IEICE Electronics Express, Vol.15, No.7, 1 10 (c) Fig. 2. (d) Design of LNA input matching block for TRX operation at 60 GHz, design of PA output matching block for operation at 60 GHz, (c) simulated impedance results on Smith Chart from 57 to 66 GHz for LNA input matching design, and (d) simulated impedance results on Smith Chart from 57 to 66 GHz for PA input matching design. in this case is not close to 50 Ω mostly due to the large reactive component (j33 ). Hence, the loss due to reflection in TX mode of the antenna switch circuit is around 0.46 db. As a result, total loss in TX mode from PA output to antenna input is 2.37 db. One of the important point to be cleared out is the isolation from PA to LNA, as indicated in Fig. 3. The coupled power to the first-stage LNA transistor gate from the PA may open and close the transistor if the voltage amplitude of the coupled power exceeds the transistor threshold voltage value (around 0.4 V in this process) when the output power is large and the isolation is not enough. The peak voltage amplitude versus the output power from PA is calculated for different isolation values and plotted in Fig. 4. For instance, for a TX output power of 3 dbm an isolation of 10 db is enough to preserve linearity of the TX mode. A conceptual design is made for a two-stage LNA and a two-stage PA. The schematic of the antenna switch circuitry is shown in Fig. 5. The isolation from the last-stage 5

IEICE Electronics Express, Vol.15, No.7, 1 10 Fig. 3. The principle of operation when the RX mode is active. The principle of operation when the TX mode is active. Fig. 4. Peak voltage amplitude at the gate of LNA for different isolation values from TX to RX versus the output power of TX in dbm. Fig. 5. Overall schematic for proposed integrated antenna switching circuitry with two-stage PA and LNA. transistor output of PA to the first-stage transistor input of LNA is simulated and presented in Fig. 6. The simulated isolation is less than 10 db in the band of interest. This much isolation is enough for moderate power applications. Moreover, time domain simulation is made for TX output power of 1.6 dbm (simulated OP1dB point) and illustrated in Fig. 6. The antenna output time domain signal is illustrated in black and has a maximum of around 0.4 V, and the coupled time domain signal to the gate of LNA transistor is shown in red color which has a peak value of around 0.3 V (< Vth ¼ 0:4 V). The LNA transistor output time domain signal is plotted in blue. One can observe that the peak is less than the input as expected. The design satisfies the requirement for the isolation. 6

Fig. 6. Simulated isolation. Comparison of simulated time domain voltage signals. 3 Measurement structures and results LNA only and PA only Test Element Groups (TEGs) are implemented for comparison purposes. However, LNA input pad and PA output pad are just added for measurements. After the measurements these pads are de-embedded for fair comparison since the design of PA and LNA does not include those pads, and the impedances of LNA and PA are designed considering the antenna port pad parasitic capacitance. All TEGs are implemented in 65 nm bulk CMOS process. The overall designed antenna switch (schematic presented in Fig. 5) chip photo is shown in Fig. 7. The total area with pads is 0:78 0:68 mm 2, the core circuit area without pads and DC decoupling capacitors is 0:42 0:55 mm 2 ¼ 0:23 mm 2. Left hand side has a ground-signal-ground (GSG) pad as the antenna port. On the right hand side, a GSGSG pad is used. Upper signal pad is for the output of LNA and lower signal pad is for the input of PA. LNA only TEG chip photo is shown in Fig. 7 and the core circuit area without pads and DC decoupling capacitors is 0:25 0:57 mm 2 ¼ 0:143 mm 2, and PA only TEG chip photo is shown in Fig. 7(c) and the core circuit area without pads and DC decoupling capacitors is 0:23 0:55 mm 2 ¼ 0:127 mm 2. The total core area consumption for LNA only and PA only TEGs is calculated to be 0.27 mm 2. On the other hand, the total core area of the whole system is 0.23 mm 2. In this work, the area is saved by 0.04 mm 2. This clears the area advantage. First of all, all circuits are measured with a Vector Network Analyzer (VNA). Fig. 8 presents the antenna port reflection S-Parameter in RX mode for the switch circuit (red line) in comparison with LNA only TEG input port reflection S-Parameter (blue line) from 57 to 66 GHz. As it can be observed when the LNA and PA is combined in considerations with antenna port pad parasitic capacitance, the impedance is close to 50 Ω point on Smith Chart. Similarly, Fig. 8 presents the antenna port reflection S-Parameter in TX mode for the switch circuit (red line) in comparison with PA only TEG input port reflection S-Parameter (blue line) from 57 to 66 GHz. PA only TEG return loss results are more far from the center of Smith Chart when compared to the combined circuits return loss results. From the perspective of matching on the antenna port of the switch circuit, one can say that both TX mode and RX mode are well matched. The measured gain of LNA (RX, PA is OFF) mode of antenna switch circuit (red line) and de-embedded LNA only circuit (blue line) are presented in Fig. 9. 7

(c) Fig. 7. Measurement structures; the chip photo for overall switch with a two-stage PA and a two-stage LNA (Fig. 5), the chip photo of the two-stage LNA used in the switch circuit, and (c) the chip photo of the two-stage PA in the switch circuit. Fig. 8. Antenna port reflection S-Parameters measurement results comparisons of LNA only as blue line (Fig. 7) and LNA mode of antenna switch circuit (Fig. 7) as red line (PA is OFF), and PA only as blue line (Fig. 7(c)) and PA mode of antenna switch circuit as red line (LNA is OFF). The results are presented from 57 to 66 GHz. TRX switch LNA mode gain is around 10 db at 60 GHz. The gain difference between the TRX switch LNA mode and the LNA only is between 1.1 to 1.7 db. The minimum value is much smaller than one can achieve with a conventional switch structure. The NF of TRX switch and LNA only TEG is measured and presented in Fig. 9. The red dots are the NF of TRX switch RX mode and the blue dots are the NF of LNA only TEG. 8

Fig. 9. Measurement results of the gain of LNA only (blue line, Fig. 7), LNA mode of antenna switch circuit (red line, Fig. 7, when PA is OFF). Measured NF of LNA only in blue dots, LNA mode of the antenna switch circuit in red dots, the NF degradation because of the switch in black dots. Fig. 10. Measurement results of the gain of PA only (blue line, Fig. 7(c)), PA mode of antenna switch circuit (red line, Fig. 7, when LNA is OFF). Input-output power relation when only PA in blue line and PA mode of switch circuit in red line. Moreover, black dots represents the NF degradation due to the LNA and PA combination of antenna switch circuitry. The NF degradation aligns with the gain degradation of LNA circuit. The NF of RX mode is measured to be 2.9 db at lowest. LNA only TEG has a NF as low as 1.9 db. The measured gain of PA (TX, LNA is OFF) mode of antenna switch circuit (red line) and de-embedded PA only circuit (blue line) are presented in Fig. 10 from 57 to 67 GHz. TRX switch PA mode gain has a maximum of around 12 db at 65 GHz. PA only measured gain has a maximum of around 14 db around 65 GHz. The gain difference between the TRX switch PA mode and the PA only is between 2.3 to 2.7 db. The difference is flat which is desired for a wideband system gain flatness. However, the introduced loss is higher than the LNA case. As explained in the previous section, it is mostly because of matching the PA for ON state to 50 Ω. The main loss contribution is from the reflection and impedance mismatch between OFF state LNA and ON state PA. Fig. 10 presents the input-output power characteristics of PA only TEG (blue line) and the TRX switch PA mode (red line) at 61.56 GHz. The OP 1dB of the TRX switch PA mode is 2 dbm whereas the PA only TEG has an OP 1dB value at 3.1 dbm. The degradation in linearity is much 9

Ref. This Work Table I. Topology LNA+PA TDD Comparison with state-of-the-art literature. Freq. [GHz] RX Loss [db] TX Loss [db] Area [mm 2 ] NF [db] 57 66 1.1 1.7 2.3 2.7 0.04 2.9 [3] Balun 55 66 1.2 2.3 1.6 2.9 0.024 14 [4] [5] [10] [11] Quarter- Wavelength Quarter- Wavelength Double Shunt & Matching Matching Network 50 70 2 2 0.125-53 60 1.5 1.6 1.5 1.6 0.275-50 67 1.9 1.9 0.303-57 66 2 2 0.02 - lower than the introduced loss by the TRX switch combination which is around 2.3 db. Moreover, one can understand the isolation is not an issue at this OP 1dB since the degradation of linearity is lower than the combined switch loss. 4 Conclusions Table I presents the comparison table of the proposed structure with other state-ofthe-art switch circuits. Proposed antenna switch has a loss in RX mode as low as 1.1 db which is the lowest presented in the table. Hence, the NF degradation for RX is the lowest in the presented mode. The minimum NF for this work is measured as 2.9 db. Another clear advantage of the proposed work is the silicon area consumption, since the design does not use any additional switch or transmission lines. As indicated, matching blocks are re-used for switching purposes in consideration with the switch as re-using the transistor of last-stage of PA and first-stage of LNA. For massive MIMO applications or phased array applications, this method helps to save considerable silicon area. The loss in TX mode is higher than expected. One reason is the modeling issue of transistors. By using more accurate models, much lower loss is possible without degradation of TX linearity or gain. Both PA and LNA ON and OFF impedances are carefully designed to achieve this low loss antenna switching circuit. The presented switch method has several advantages in terms of area, lower loss, and lower NF degradation. The simulated isolation value of 14 db shows that the switch can work properly at an output power of OP 1dB ¼ 2 dbm, without any degradation on the linearity other than introduced loss of the switching architecture. Acknowledgments This work is partially supported by MIC, SCOPE, STAR, and VDEC in collaboration with Cadence Design Systems, Inc., Synopsys, Inc., Mentor Graphics, Inc., and Keysight Technologies Japan, Ltd. 10