www.dalsemi.com FEATURES All-silicon time delay taps equally spaced Delays are stable and precise Both leading and trailing edge accuracy Delay tolerance ±% or ± ns, whichever is greater Low-power CMOS TTL/CMOS-compatible Vapor phase, IR and wave solderable Custom delays available Fast turn prototypes Extended temperature range available (-D) -Tap Silicon Delay Line P ASSIGNMENT 0 TAP TAP GND 7 8 TAP -Pin DIP (00-mil) 9 GND TAP TAP TAP M 8-Pin DIP (00-mil) GND 8 7 8 7 TAP TAP TAP Z 8-Pin SOIC (0-mil) P DESCRIPTION TAP -TAP - TAP Output Number - + Volts GND - Ground - No Connection - Input DESCRIPTION The series delay lines have five equally spaced taps providing delays from ns to 00 ns. These devices are offered in a standard -pin DIP that is pin-compatible with hybrid delay lines. Alternatively, 8-pin DIPs and surface mount packages are available to save PC board area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 00% silicon delay line and industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead configurations. The series delay lines provide a nominal accuracy of ±% or ± ns, whichever is greater. The -Tap Silicon Delay Line reproduces the input logic state at the output after a fixed delay as specified by the extension of the part number after the dash. The is designed to reproduce both leading and trailing edges with equal precision. Each tap is capable of driving up to ten 7LS loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests and rapid delivery, call 97-7-8. of 799
LOGIC DIAGRAM Figure PART NUMBER DELAY TABLE (all values in ns) Table PART # - of TAP TAP TAP TOLERAE TOLERAE TOLERAE TOLERAE TOLERAE -0 8 0-0 0-0 8 0-7 8. -0 8 0. - 9 8 7... -0 0 0 0 0. 0.. -0. 8.. 0.8-7 0.. 0.8 7.8. -00 0 0. 0.8 80. 00-0.. 7.8. 00..8-0 0 0.8 90..7 0. 0 7.. -7. 70.. 0.. 0 7. 7 8.8. -00 0. 80. 0. 0 8.8 00 0-0 0.. 00 0 7.. 00 0 0. 7. -00 00 00 0 00 9 00 0 00 DC ELECTRICAL CHARACTERISTICS (0 C to 70 C; =.0V ± %) PARAMETER SYM TEST M TYP MAX UNITS NOTES CONDITION Supply Voltage.7.00. V High Level Input V IH. + 0. V Voltage Low Level Input V IL -0. 0.8 V Voltage Input Leakage I I 0.0V V I -.0.0 ua Active I CC =Max; 7 ma 7, 9 Period=Min. High Level Output I OH =Min. - ma V OH = Low Level Output I OL =Min. V OL =0. ma AC ELECTRICAL CHARACTERISTICS (T A = C; = V ± %) PARAMETER SYMBOL M TYP MAX UNITS NOTES Input Pulse Width t WI 0% of Tap t PLH ns 8 Input to Tap Delay (leading edge) t PLH Table ns,,,,, 0 Input to Tap Delay (trailing edge) t PHL Table ns,,,,, 0 Power-up Time t PU 00 ms Input Period Period (t WI ) ns 8
CAPACITAE (T A = C) PARAMETER SYMBOL M TYP MAX UNITS NOTES Input Capacitance C 0 pf NOTES:. Initial tolerances are ±=with respect to the nominal value at C and V.. Temperature tolerance is ±=with respect to the initial delay value over a range of 0 C to 70 C.. The delay will also vary with supply voltage, typically by less than % over the range.7 to.v.. All tap delays tend to vary uni-directionally with temperature or voltage changes. For example, if TAP slows down, all other taps also slow down; TAP can never be faster than TAP.. Intermediate delay values and packaging variations are available on a custom basis. For further information, call 97-7 8.. All voltages are referenced to ground. 7. Measured with outputs open. 8. Pulse width and period specifications may be exceeded; however, accuracy may be impaired depending on application (decoupling, layout, etc.). The device will remain functional with pulse widths down to 0% of Tap delay, and input periods as short as (t WI ). 9. I CC is a function of frequency and TAP delay. Only a - operating with a 0-ns period and =.V will have an I CC = 7 ma. For example a -00 will never exceed 0 ma, etc. 0. See Test Conditions section at the end of this data sheet. TIMG DIAGRAM: SILICON DELAY LE Figure of
TEST CIRCUIT Figure TERMOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t WI (Pulse Width): The elapsed time on the pulse between the.v point on the leading edge and the.v point on the trailing edge or the.v point on the trailing edge and the.v point on the leading edge. t RISE (Input Rise Time): The elapsed time between the 0% and the 80% point on the leading edge of the input pulse. t FALL (Input Fall Time): The elapsed time between the 80% and the 0% point on the trailing edge of the input pulse. t PLH (Time Delay, Rising): The elapsed time between the.v point on the leading edge of the input pulse and the.v point on the leading edge of any tap output pulse. t PHL (Time Delay, Falling): The elapsed time between the.v point on the trailing edge of the input pulse and the.v point on the trailing edge of any tap output pulse. TEST SETUP DESCRIPTION Figure illustrates the hardware configuration used for measuring the timing parameters on the. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (0 ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 88 bus. of
TEST CONDITIONS PUT: Ambient Temperature: Supply Voltage ( ): Input Pulse: Source Impedance: Rise and Fall Time: Pulse Width: 00 ns ( µs for -00) Period: µs ( µs for -00) C ±= C.0V ±=0.V High =.0V ±=0.V Low = 0.0V ±=0.V 0 ohm Max..0 ns Max. (measured between 0.V and.v) OUTPUT: Each output is loaded with the equivalent of one 7F0 input gate. Delay is measured at the.v level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. of