TX.3/97-009 CONTRIBUTION TO T STANDARDS PROJECT ************************************************************************************************ STANDARDS PROJECT: Digital Optical Hierarchy ************************************************************************************************ TITLE: Proposed U.S. Contribution to ITU-T SG3, Q. 8 (Formerly Q2) with Proposal for Clock Types II, III, and IV (Stratum 2, 3E, and 3) for New Revised Draft ITU-T Recommendation G.82 ************************************************************************************************ AUTHOR: SOURCE: Geoffrey Garner CONTACT: S.J. (John) Chen Lucent Technologies 0 Crawfords Corner Road, Room 4L-322 Holmdel, NJ 07733 (908) 949-579 ************************************************************************************************ Date: January, 997 ************************************************************************************************ DISTRIBUTION: TX.3 Working Group ************************************************************************************************ ABSTRACT This contribution proposes a U.S. contribution for the February, 997 ITU-T SG 3, Q.8 (formerly Q 2) meeting to propose specific requirements for many of the sections of New Revised Draft ITU-T G.82 that are currently TBD. All the proposals here are for clock types II, III, and IV, which correspond to stratum 2, 3E, and 3, respectively. All the proposals here are taken from existing specifications commonly used in North America, i.e., ANSI T.0-994, Bellcore GR-244-CORE, and, in a few instances, Bellcore GR- 253-CORE. ************************************************************************************************ NOTICE This document has been prepared to assist the Standard Committee T- Telecommunications. It is offered to the Committee as a basis for discussion and is not a binding proposal on Lucent Technologies. The requirements presented in this document are subject to change in form and numerical value after more study. Lucent Technologies specifically reserves the right to add to, or amend the statements contained within.
TX.3/97-009. Introduction An ITU-T Q 2/3 Expert Meeting was held November 3-5, 996 in Rome, Italy. The meeting was limited to progressing the revision of Recommendation G.82, Timing Requirements of Slave Clocks Suitable for Use as Node Clocks in Synchronization Networks. The results of this meeting are described in TX.3/97-004 [][]. The New Revised Draft G.82 produced by the Expert Meeting contains six clocks. These clocks are labeled Types I through VI, and correspond to clocks used in various regions of the world as summarized in Table. A copy of the New Revised Draft G.82 is provided in [2][2]. As indicated in [][], there was considerable controversy with respect to including all six clock types. Several members had the goal of including only Clock Type I in the document or, if this was not possible, minimizing the number of clock types. While it was agreed in the end to include all six clock types in the draft, it was clear that contributions that propose specific requirements for those specifications that are currently TBD and contributions that provide a basis for the network need for these clocks would be needed for the February, 997 ITU-T SG 3 meeting. The current contribution attempts to provide values for many of the specifications for the stratum clocks (Types II, III, and IV) in [2][2] that are currently TBD. A companion contribution [3] [3] attempts to provide the basis for the requirements and network need (i.e., network drivers) for these three clocks. It is felt that this type of information is needed to ensure that these clocks remain in G.82. One of the conclusions of [][] was that, without further input from ANSI at the February, 997 ITU-T SG 3 meeting, the stratum clocks could be removed from G.82. The attached proposed U.S. contribution to ITU-T SG 3 contains a short introduction followed by the proposal for G.82. The proposal is in the form of a base document that is equivalent to the result of the Expert meeting (TX.3/97-006 [2][2]), with the proposed new values, figures, tables, etc. indicated as revisions. For the revisions, each deletion from the base document is indicated as a strike-through, and each insertion or addition to the document is underlined (this scheme is used for entire figures where necessary). This scheme was chosen so it would be absolutely clear what is being proposed here (versus what was produced by the expert meeting). The proposal is limited to Clock Types II, III, and IV, with several very minor exceptions (for the other clock types) where obvious typographical errors were corrected. REFERENCES [] Christina Howe, Report from ITU Experts Group Meeting, Contribution to T Standards Project, TX.3/97-004, Plano, TX, January, 997. [2] New Revised Draft ITU-T G.82, Timing Requirements of Slave Clocks Suitable for Use as Node Clocks in Synchronization Networks, November, 996 (provided on TBBS as TX.3/97-006). [3] Geoffrey Garner, Proposed U.S. Contribution to ITU-T SG 3, Q. 8 (Formerly Q2) to provide basis and Network Need for Clock Types II, III, and IV (Stratum 2, 3E, and The February, 997 ITU-T SG 3 meeting will be the first of the new (997-2000) study period. The question number for the Timing and Synchronization question has changed from 2 to 8.
TX.3/97-009 3) in New Revised Draft ITU-T Recommendation G.82, Contribution to T Standards Project, TX.3/97-00, Plano, TX, January, 997. Table. Clock types in New Revised Draft G.82, and correspondence to existing clocks used in various regions of the world Clock Type I II III IV V VI Clock New ETSI DE/TM- 0307-4 ANSI Stratum 2 Bellcore Stratum 3E ANSI Stratum 3 G.82 Transit (Blue Book, 988, plus amendments) G.82 Local (Blue Book, 988, plus amendments)
TX.3/97-009 INTERNATIONAL TELECOMMUNICATION UNION TELECOMMUNICATION STANDARDIZATION SECTOR COM 3-D. -E February 997 Original: English STUDY PERIOD 997-2000 Question: 8/3 STUDY GROUP 3 - CONTRIBUTION SOURCE*: TITLE: TX (Proposed United States of America) Proposal for Clock Types II, III, and IV for New Revised Draft ITU-T Recommendation G.82 Abstract: This contribution proposes specific requirements for many of the sections of New Revised Draft ITU-T G.82 that are currently TBD. All the proposals here are for clock types II, III, and IV. The proposals are taken from existing specifications commonly used in North America.. Introduction At the November, 996 ITU-T Q 2/3 Expert Meeting, a New Revised Draft ITU-T G.82 was produced with six clock types (the meeting report and text of New Revised Draft ITU-T G.82 is contained in [][]). For Clock Types II, III, and IV, which correspond to clocks commonly used in North America, the requirements in many of the sections of G.82 are indicated as To Be Defined (TBD). The current contribution contains proposals for most of these requirements. A companion contribution [2] [2] provides the basis for the requirements (both the requirements for Clock Types II, III, and IV agreed to at the Expert Meeting and the proposals in the current contribution) and network need (i.e., network drivers) for these three clocks. The proposals are contained in the Annex. They are in the form of a base document that is equivalent to the New Revised Draft G.82 produced by the Expert meeting [][] with the proposed new values, figures, tables, etc. indicated as revisions. For the revisions, each deletion from the base document is indicated as a strike-through, and each insertion or addition to the document is underlined (this scheme is used for entire figures where necessary). This scheme was chosen so it would be absolutely clear what is being proposed here (versus what was produced by the expert meeting). The proposal is limited to Clock Types II, III, and IV, with several very minor exceptions (for the other clock types) where obvious typographical errors were corrected. REFERENCES * Contact Person - Mr. Geoffrey M. Garner Tel.: + 908 949 0374 Fax: + 908 949 320
[] SWP 43-6 Rapporteur Interim Meeting, Report of the Meeting, Temporary Document 2, Rome, Italy, November 3-5, 996 (to be submitted by the Rapporteur as a White Document to the February, 997 ITU-T SG 3 meeting). [2] Basis and Network Need for Clock Types II, III, and IV in New Revised Draft ITU-T Recommendation G.82, U.S. Contribution, Delayed Document, ITU-T SG 3, WP 4, Seoul, Korea, February, 997.
ANNEX The following pages contain the proposed text for New Revised Draft ITU-T G.82, with the proposals for Clock Types II, III, and IV.
INTERNATIONAL TELECOMMUNICATION UNION NEW REVISED DRAFT ITU-T G.82 TELECOMMUNICATION (/96) STANDARDIZATION SECTOR OF ITU DIGITAL NETWORKS NETWORK PERFORMANCE TIMING REQUIREMENTS OF SLAVE CLOCKS SUITABLE FOR USE AS NODE CLOCKS IN SYNCHRONISATION NETWORKS ITU-T Recommendation G.82
Draft Revised Recommendation G.82 TIMING REQUIREMENTS OF SLAVE CLOCKS SUITABLE FOR USE AS NODE CLOCKS IN SYNCHRONISATION NETWORKS Summary (Interim Q2/3 Meeting, Rome 3-5 November 996) Recommendation G.82 outlines minimum requirements for timing devices used as node clocks in synchronisation networks. These networks include Public Switch Telephone Networks (PSTN) and Synchronous Digital Hierarchy (SDH) networks. Keywords. Scope Clock Performance Objectives Clock Performance Parameters Jitter Performance Node Clock Wander Performance This recommendation outlines requirements for timing devices used in synchronizing network equipment that operate according to the principles governed by Public Switch Telephone Networks (PSTN) and the Synchronous Digital Hierarchy (SDH). These requirements apply under the normal environmental conditions specified for the equipment. In normal operation, these slave clocks are traceable to a primary reference clock. In general the node clock will have multiple reference inputs. In the event that all links between the master and the slave clock fail, the node clock should be capable of maintaining operation (holdover) within prescribed performance limits. The node clock can be a separate piece of equipment called a Standalone Synchronisation Supply Equipment (SASE) or it can form a logical function of another equipment such as a telephony exchange or SDH crossconnect. This recommendation includes six types of node clock. Type I describes node clocks suitable to synchronise SDH networks optimised for the 2048 kbit/s hierarchy. Types II, III, and IV describe node clocks suitable to synchronise SDH networks optimised for the particular 544 kbit/s hierarchy that includes the rates 544 kbit/s, 632 kbit/s, and 44736 kbit/s. Types V and VI describe node clocks suitable to synchronise PSTN exchanges. A G.82 clock should comply with all of the requirements specific to one type and should not mix requirements from different types. When the term G.82 is applied within this recommendation, then the requirement is applicable to all six types of clock. It is the intention that the number of clock types should be reduced in the future as result of harmonisation. 3
The clocks described in this recommendation can be used in synchronization networks that meet the requirements of the controlled octet slip rate objectives as described in ITU-T Rec G.822 for plesiochronous operation of international digital links. Hierarchical timing distribution is recommended for synchronisation networks. Timing should not be passed from a lower quality clock in free-run/holdover mode to a higher quality clock since the higher quality clock should not follow the lower quality clock signal during fault conditions. 2. References The following ITU-T Recommendations contain provisions which, through reference in this text, constitute provisions of this Recommendation. All Recommendations are subject to revision; all users of this Recommendation are therefore encouraged to investigate the possibility of applying the most recent edition of a Recommendation. A list of currently valid ITU-T Recommendations is regularly published. [] ITU-T Recommendation G.703 Physical/electrical characteristics of hierarchical digital interfaces [2] ITU-T Recommendation G.783 Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks [3] ITU-T Recommendation G.80 Definitions and terminology for synchronisation networks [4] ITU-T Recommendation G.8 Timing requirements at the outputs of primary reference clocks suitable for plesiochronous operation of international digital links [5] ITU-T Recommendation G.82 Timing requirements at the outputs of slave clocks suitable for plesiochronous operation of international digital links [6] ITU-T Recommendation G.822 Controlled slip rate objectives on an international digital connection [7] ITU-T Recommendation G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy [8] ITU-T Recommendation G.824 The control of jitter and wander within digital networks which are based on the 544 kbit/s hierarchy [9] ITU-T Recommendation G.825 The control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (SDH) 3. Definitions The terms and definitions used in this Recommendation are contained initu-t Recommendation G.80. 4. Abbreviations For the purpose of this Recommendation the following abbreviations are used: CMI Coded Mark Inversion SEC SDH Equipment Clock FPM Flicker Phase Modulation SSMB Synchronisation Status Message Byte MTIE Maximum Time Interval STM Synchronous Transport Module Error NE Network Element TDEV Time Deviation OAM Operations And Maintenance UI Unit Interval 23
PLL Phase Locked Loop UTC Coordinated Universal Time PRC Primary Reference Clock WFM White Frequency Modulation SDH Synchronous Digital Hierarchy 5. Frequency Accuracy Under prolonged holdover conditions, the output frequency accuracy of the different types of node clock should not exceed the values in Table /G.82 with regard to a reference traceable to a primary reference clock, over a time period T as reported in the same Table. Note: the time period T applies after TBD days of continuous synchronised operation. Table /G.82 Output Frequency Accuracy Requirements Type I Type II Type III Type IV Type V Type VI Accuracy NA.6 0-8 4.6 0-6 4.6 0-6 ND ND Period T NA TBD TBD TBD ND ND NA = Not Applicable. ND = Not Defined. TBD = To Be Defined. 6. Pull-in, Hold-in, and Pull-out Ranges The minimum Pull-in, Hold-in and Pull-out ranges for the different types of node clock should be according to Table 2/G.82, whatever the internal oscillator frequency offset may be. Table 2/G.82 Pull-in, hold-in, and pull-out requirements Type I Type II Type III Type IV Type V Type VI Pull in 0-8.6 0-8 4.6 0-6 4.6 0-6 ND ND Hold in NA.6 0-8 4.6 0-6 4.6 0-6 ND ND Pull out FFS TBD TBD TBD ND ND NA = Not Applicable. ND = Not Defined. TBD = To Be Defined. FFS = For Further Study. 7. Noise Generation The noise generation of a slave clock represents the amount of phase noise produced at the output when there is an ideal input reference signal or the clock is in holdover state (see sect. 0.2). A suitable reference, for practical testing purposes, implies a performance level at least 0 times more stable than the output requirements. The ability of the clock to limit this noise is described by its frequency stability. The measures MTIE and Time Deviation (TDEV) are useful for characterisation of noise generation performance. MTIE and TDEV are measured through an equivalent 0 Hz, first-order, low-pass measurement filter, at a maximum sampling time τ 0 of /30 seconds. The minimum measurement period for TDEV is twelve times the integration period (T = 2τ). 33
7. Wander in Locked Mode When the node clock is in the locked mode of operation, the MTIE at constant temperature (within ± K) measured using the synchronised clock configuration defined in Figure a/g.80, should have the limits in Tables 3/G.82, 4/G.82, and 5/G.82 for the different types of node clock. Table 3/G.82 Wander generation (MTIE) for Type I node clock at constant temperature (within ± K) MTIE limit Observation interval τ 24 ns 0. < τ 9 s 8τ 0.5 ns 9 < τ 400 s 60 ns 400 < τ 0000 s Table 4/G.82 Wander generation (MTIE) for Type II, III and IV node clocks at constant temperature (within ± K) MTIE limit NA Observation interval τt τt < 0. s 40 0. s < τt < s 40τ 0.4 40t 0.4 ns s < τt < 0 s 00 ns 0 < τt < 000 s 00 ns 000 s < τt Table 5/G.82 Wander generation (MTIE) for Type V and VI node clocks at constant temperature (within ± K) MTIE limit FFS Observation interval τ 0.05 s < τ < 00 s 000 ns 00 s < τ The resultant requirements are shown in Figure /G.82 43
0000 MTIE (ns) (Log scale) 000 60 00 TYPE V, VI TYPE I TYPE II, III, IV 40 24 0 0..0 9 0 00 400 k 0 k Observation Interval (Log scale) τ (s) Figure /G.82 Wander generation (MTIE) at constant temperature at constant temperature (within ± K) When the node clock is in the locked mode of operation, the TDEV at constant temperature (within ± K) measured using the synchronised clock configuration defined in Figure a/g.80, should have the limits in Tables 6/G.82, 7/G.82, and 8/G.82 for the different types of node clock. Table 6/G.82 Wander generation (TDEV) for Type I node clock at constant temperature (within ± K) MTIE limit Observation interval τ 3 ns 0. < τ 25 s 0.2τ ns 25 < τ 00 s 2 ns 00 < τ 0000 s 53
Table 7/G.82 Wander generation (TDEV) for Type II, III and IV node clocks at constant temperature (within ± K) TDEV limit Observation interval τ 3.2τ -0.5 ns 0. s < τ <2.5 s 2 ns 2.5 s < τ < 40 s 0.32τ 0.5 ns 40 < τ < 000 s 0 ns 000 s < τ Table 8/G.82 Wander generation (TDEV) for Type V and VI node clocks at constant temperature (within ± K) MTIE limit Observation interval τ FFS The resultant requirements are shown in Figure 2/G.82. 0. s < τ < 0000 s 63
00 TDEV (ns) (Log scale) 2 0 3 2 TYPE I TYPE II, III, IV 0. 0. 2.5 0 25 40 00 k 0 k Observation Interval (Log scale) τ (s) Figure 2/G.82 Wander generation (TDEV) at constant temperature (within ± K) 7.2 Non-locked Wander When a clock is not locked to a synchronisation reference, the random noise components are negligible compared to a deterministic effects like initial frequency offset. Consequently the nonlocked wander effects are included in 0.2. 7.3 Jitter While most requirements in this recommendation are independent of the output interface at which they are measured, this is not the case for jitter production; jitter generation requirements utilize existing recommendations that have different limits for different interface rates. These requirements are stated separately for the interfaces identified in. To be consistent with other jitter requirements the values are in UIpp, where the UI corresponds to the reciprocal of the bit rate of the interface. Note that all filter values specified in this generation section for STM-N interfaces have been harmonised with the filter values for the network limit as specified in G.825. Note:Due to the stochastic nature of jitter, the peak-to-peak values given in this section eventually are exceeded. The requirements should therefore be fulfilled in at least 99% of all measurements made. Output Jitter at a 2048 khz and 2048 kbit/s Interfaces 73
In the absence of input jitter, the intrinsic jitter at a 2048 khz and 2048 kbit/s output interfaces as measured over a 60 seconds interval should not exceed 0.05 UI peak-peak when measured through a single pole band-pass filter with corner frequencies at 20 Hz and 00 khz. Output Jitter at a 544 kbit/s Interfaces In the absence of input jitter, the intrinsic jitter at a 544 kbit/s output interfaces should not exceed 0.05 UI peak-peak when measured through a single pole band-pass filter with corner frequencies at 0 Hz and 40 khz. Output Jitter at an STM-N Interface In the absence of input jitter at the synchronisation interface, the intrinsic jitter at optical STM-N output interfaces as measured over a 60 seconds interval should not exceed the limits given in Table 9/G.82 below. for STM- : UI = 6.43 ns for STM-4 : UI =.6 ns for STM-6 : UI = 0.40 ns Table 9/G.82 STM-N jitter generation Interface Measuring Filter peak-to-peak Amplitude STM- el. STM- opt. 8. Noise Tolerance 500 Hz to.3 MHz 65 khz to.3 MHz 0.50 UI 0.075 UI 500 Hz to.3 MHz 0.50 UI 65 khz to.3 MHz 0.0 UI STM-4 000 Hz to 5 MHz 0.50 UI 250 khz to 5 MHz 0.0 UI STM-6 5000 Hz to 20 MHz 0.50 UI MHz to 20 MHz 0.0 UI The noise tolerance of a G.82 indicates the minimum phase noise level at the input of the clock that should be accommodated whilst: Maintaining the clock within prescribed performance limits The exact performance limits are for further study. Not causing any alarms. Not causing the clock to switch reference. Not causing the clock to go into holdover. 83
In general, the noise tolerance of a G.82 clock is the same as the network limit for the synchronisation interface in order to maintain acceptable performance. However, the synchronisation interface network limit may be different according to the application. Therefore in order to determine the slave clock noise tolerance, the worst case network limit should be used. An explanation of the different network limits for acceptable payload performance is given in Appendix I/G.83 for information. The wander and jitter tolerances given in sect. 8. and sect. 8.2 represent the worst levels that a synchronisation carrying interface should exhibit. The TDEV signal used for a conformance test should be generated by adding white, gaussian noise sources, of which each has been filtered to obtain the proper type of noise process with the proper amplitude: to provide guidance in designing such filters, in Appendix I/G.82 it is shown how the power spectral density of phase can be approximately expressed in terms of the TDEV of the phase. The functional model of a suitable TDEV noise generator is described in Appendix II/G.82. MTIE and TDEV are measured through an equivalent 0 Hz, first-order, low-pass measurement filter, at a maximum sampling time τ 0 of /30 seconds. The minimum measurement period for TDEV is twelve times the integration period (T = 2τ). 8. Wander Tolerance The G.82 input wander tolerance expressed in MTIE limits is given in Table 0/G.82 for Type I node clocks and in Table /G.82 for Type II, III, IV node clocks. Table 0/G.82 Input wander tolerance (MTIE) for Type I node clock MTIE limit Observation interval τ 0.75 µs 0. s < τ <7.5 s 0.τ µs 7.5 s < τ <20 s 2 µs 20 s < τ < 400 s 0.005τ µs 400 < τ < 000 s 5 µs 000 < τ < 0000 s Table /G.82 Input wander tolerance (MTIE) for Type II, III and IV node clocks MTIE limit Observation interval τ NA τ <0.05 s (0.3 + 0.0025τ) µs 0.05 s < τ <280 s (0.997 + 0.0000τ) µs 280 s < τ The resultant requirements are shown in Figure 3/G.82. 93
00 MTIE (µs) (Log scale) 0 60 2 0.75 TYPE I TYPE II, III, IV 0.3 0. 0..0 7.5 0 20 00 280 400 k 0 k Observation Interval (Log scale) τ (s) Figure 3/G.82 Input wander tolerance (MTIE) Input wander tolerance in terms of MTIE for Type V and VI is not defined. The G.82 input wander tolerance expressed in TDEV limits is given in Table 2/G.82 for Type I node clocks and in Table 3/G82 for Type II, III, and IV node clocks. Table 2/G.82 Input wander tolerance (TDEV) for Type I node clock TDEV limit Observation interval τ 34 ns 0. s < τ <20 s.7τ ns 20 s < τ <00 s 70 ns 00 s < τ < 000 s 5.4τ 0.5 ns 000 < τ < 0000 s 03
Table 3/G.82 Input wander tolerance (TDEV) for Type II, III and IV node clocks TDEV limit FFS Observation interval τ τ <0.05 s 00 ns 0.05 s < τ <0 s 3.6τ 0.5 ns 0 s < τ < 000 s FFS The resultant requirements are shown in Figure 4/G.82. 000 s < τ 0000 TDEV (ns) (Log scale) 000 540 70 00 TYPE II, III, IV 34 TYPE I 0 0. 0 20 00 k 0 k Observation Interval (Log scale) τ (s) Figure 4/G.82 Input wander tolerance (TDEV) Input wander tolerance in terms of TDEV for Type V and VI is not defined. While suitable test signals that check conformance to the mask in Figure 3/G.82 are being studied, test signals with a sinusoidal phase variation can be used. : Thethe requirements for Type I node clock are shown in Table 4/G.82. The requirements for Type II, III, and IV node clocks are shown in Table 5/G.82. The resultant requirements are shown in Figure 5/G.82. 3
Table 4/G.82 Lower limit of maximum tolerable sinusoidal input wander for Type I node clock Peak-to-Peak Wander Amplitude Frequency Range 5 µs 2 µhz < f < 0.32 mhz 0.006 f - µs 0.32 mhz < f < 0.8 mhz 2 µs 0.8 mhz < f < 6 mhz 0.032 f - µs 6 mhz < f < 43 mhz 0.73 µs 43 mhz < f < Hz Table 5/G.82 Lower limit of maximum tolerable sinusoidal input wander for Type II, III, and IV node clocks Peak-to-Peak Wander Amplitude Frequency Range 0.997 + [ 4 0-6 / f (Hz) ] µs 3.8 µhz < f <.429 mhz 0.3 + [ 0.00 / f (Hz) ] µs.429 mhz < f < 0 Hz The resultant requirements are shown in Figure 5/G.82. 0 Peak-to-peak Wander Amplitude ( µs) (log scale) 5 2 0.73 0. 0.02 m 0. m 0.32 m m 0 m 0. 0.8 m 6 m 43 m Wander Frequency f (Hz) (log scale) 23
0 Peak-to-Peak Wander Amplitude (mu s) 0. 0 5 0 4 0 3 0.0 0. 0 Wander Frequency (Hz) Type I Types II, III, IV Figure 5/G.82s Lower limit of maximum tolerable sinusoidal input wander for Type I, II, III, and IV node clocks Maximum tolerable sinusoidal input wander requirements for Type II, III, and IV node clocks are TBD. Maximum tolerable sinusoidal input wander requirements for Type V and VI node clocks are given in Table 65/G.82 for 2048 khz (or 2048 kbit/s) input ports and in Table 6a6/G.82 for 544 khz (or 544 kbit/s) input ports. Table 65/G.82 Lower limit of maximum tolerable sinusoidal input wander for Type V and VI node clocks (2048 khz and 2048 kbit/s input ports) Peak-to-Peak Wander Amplitude Frequency Range 8 µs 2 µhz < f < 0.78 mhz 0.0032 f - µs 0.78 mhz < f <.6 mhz 2 µs.6 mhz < f < 6 mhz 0.032 f - µs 6 mhz < f < 43 mhz 0.73 µs 43 mhz < f < Hz 33
Table 6a6/G.82 Lower limit of maximum tolerable sinusoidal input wander for Type V and VI node clocks (544 khz and 544 kbit/s input ports) Peak-to-Peak Wander Amplitude Frequency Range 8 µs 2 µhz < f < 0.78 mhz 0.0032 f - µs 0.78 mhz < f < mhz 3.2 µs mhz < f < Hz The resultant requirements are shown in Figure 6/G.82. Peak-to-peak Wander Amplitude ( µs) (log scale) 00 8 0 3.2 2 0.73 544 kbit/s interface 2048 kbit/s interface 0. 0.0 m 0.02 m 0. m m 0 m 0.78 m.6 m 6 m 0. 43 m.0 Wander Frequency f (Hz) (log scale) Figure 6/G.82s Lower limit of maximum tolerable sinusoidal input wander for Type V and VI node clocks 8.2 Jitter Tolerance The lower limit of maximum tolerable sinusoidal input jitter for a Type I node clock is given in Table 7/G.82 and Figure 7/G.82. 43
Table 7/G.82 Lower limit of maximum tolerable sinusoidal input jitter for Type I node clock Peak-to-Peak Jitter Amplitude Frequency Range 750 ns Hz < f < 2.4 khz.8 0 6 f - ns 2.4 khz < f < 8 khz 00 ns 8 khz < f < 00 khz 750 Peak-to-Peak Jitter Amplitude (ns) (log scale) 00 0 00 k 0k 00k 2.4k 8k Jitter Frequency f (Hz) (log scale) M Figure 7/G.82 Lower limit of maximum tolerable input jitter for Type I node clocks The lower limit of maximum tolerable sinusoidal input jitter for Type II, III, and IV node clocks are given in Table 8/G.82 and Figure 8/G.82. 53
Table 8/G.82 Lower limit of maximum tolerable sinusoidal input jitter for Type II, III, and IVIII node clocks Peak-to-Peak Jitter Amplitude Frequency Range 5 TBD UI 0 TBD Hz < f < 500TBD Hz 5[ 500 / f(hz) ].4 TBD UI 500 TBD Hz < f < 8 khz TBD Hz 0. TBD UI 8 khz TBD Hz < f < 40 khz TBD Hz 63
0 Peak-to-Peak Jitter Amplitude (UI) (log scale) 0. 0 00 k 00k 0k M Jitter Frequency f (log scale) (Hz) 0 Peak-to-Peak Jitter Amplitude (UI) 0. 0.0 0 00 0 3 0 4 0 5 Jitter Frequency f (Hz) Figure 8/G.82 Lower limit of maximum tolerable input jitter for Type II, III, and IVIII node clocks Maximum tolerable sinusoidal input jitter requirements for Type V and VI node clocks are given in Table 9/G.82 for 2048 khz (or 2048 kbit/s) input ports and in Table 20/G.82 for 544 khz (or 544 kbit/s) input ports. 73
Table 9/G.82 Lower limit of maximum tolerable sinusoidal input jitter for Type V and VI node clocks (2048 khz and 2048 kbit/s input ports) Peak-to-Peak Jitter Amplitude Frequency Range 0.73 µs Hz < f < 2.4 khz 752 f - µs 2.4 khz < f < 8 khz 0. µs 8 khz < f < 00 khz Table 20/G.82 Lower limit of maximum tolerable sinusoidal input jitter for Type V and VI node clocks (544 khz and 544 kbit/s input ports) Peak-to-Peak Jitter Amplitude Frequency Range 3.2 µs Hz < f < 20 Hz 384 f - µs 20 Hz < f < 6 khz 0.064 µs 6 khz < f < 40 khz 83
The resultant requirements are shown in Figure 8/G.82. 0 3.2 Peak-to-Peak 0.73 Jitter Amplitude ( µs) (log scale) 2 0. 544 kbit/s interface 2048 kbit/s interface 0.0 0 00 k 0 k 00 k 20 2.4 k 6 k 8 k 40 k Jitter Frequency f (Hz) (log scale) Figure 9/G.82s Lower limit of maximum tolerable sinusoidal input jitter for Type V and VI node clocks 9. Noise Transfer The transfer characteristic of a slave clock determines its properties with regard to the transfer of excursions of the input phase relative to the phase modulation. Noise transfer can be described in two ways: a) The slave clock can be viewed as a low-pass filter for the differences between the actual input phase and the ideal input phase of the reference. The minimum and maximum allowed bandwidths for this low-pass filter behaviour are based on the considerations described in Appendix B and are reported in Table 2/G.82 below, along with the maximum allowed gain in the pass band. 93
Table 2/G.82 Noise Transfer Requirements Type I Type II Type III Type IV Type V Type VI Maximum BW 3 mhz mhz mhz 3 Hz TBD 0. Hz (*) 0. Hz (*) TBD TBD Minimum BW ND ND TBD ND TBD ND TBD ND ND Maximum Gain 0.2 db 0.2 db TBD 0.2 db TBD 0.2 db TBD 0.2 db (*) 0.2 db (*) ND = Not Defined. TBD = To Be Defined. (*) These values are taken from Recommendation Q.55. The above applies to a linear G.82 model. However, this model should not restrict implementation. b) Noise transfer describes the amount of noise impairment observed at the output, as a result of noise introduced at the input of the clock. The slave clock, when subjected to a wideband noise signal shaped as prescribed in section 8. (i.e. the TDEV wander tolerance specification), shall produce an output signal with TDEV lying within the limits specified in Table 22/G.82 for Type I and in Table 23/G.82 for Type II, III, and IV: the resultant requirements are shown in Figure 0/G.82. Wander transfer in terms of TDEV for Type V and VI node clocks are not defined. Table 22/G.82 Output Wander Mask (TDEV) for Type I node clock TDEVlimit Observation Interval τ 3 ns 0. < τ 3.3 s 0.07τ 2 ns 3.3 < τ 00 s 70 ns 00 < τ 000 s 5.4τ 0.5 ns 000 < τ 0000 s Table 23/G.82 Output Wander Mask (TDEV) for Type II and, III, and IV node clocks TDEV limit Observation Interval τ ND TBD τ < 0.05 s TBD 2 nstbd 0.05 < τ <. s TBD.82 τ nstbd. < τ < 300 s TBD 3.6 τ 0.5 nstbd 300 < τ < 000 s TBD ND τ > 000 s 203
Table 24/G.82 Output Wander Mask (TDEV) for Type IV node clocks TDEV limit Observation Interval τ ND τ < 0.05 s 000τ ns 0.05 < τ < 0. s 00 ns 0. < τ < 0 s 3.6 τ 0.5 ns 0 < τ < 000 s ND τ > 000 s 23
000 540 TDEV (ns) (log scale) 70 00 0 3 0. 0 3.3 00 k 0k Observation Interval (log scale) τ (s) 0 3 00 TDEV (ns) 0 0.0 0. 0 00 0 3 0 4 Observation Interval (s) Type I Type II, III Type IV Figure 0/G.82 Output wander mask (TDEV) Guidance on the measurement techniques for these requirements is given in Annex II/G.82. For observation intervals of 0. s to 000 s, MTIE and TDEV shall be measured through an equivalent 0 Hz, first-order, low-pass measurement filter, at a maximum sampling time τ 0 of /30 223
seconds. The minimum measurement period T for TDEV is twelve times the observation interval τ. For observation intervals of 0 s to 00000 s, MTIE and TDEV shall be measured through an equivalent 0. Hz, first-order, low-pass measurement filter, at a maximum sampling time τ 0 of 3.3 seconds. The minimum measurement period T for TDEV is twelve times the observation interval τ. 0. Transient Response and Holdover Performance The requirements in this section apply to situations where the input signal is affected by disturbances or transmission failures (e.g. short interruptions, switching between different synchronisation signals, loss of reference, etc.) that result in phase transients at the G.82 output (see sect. ). The ability to withstand disturbances is necessary to avoid transmission defects or failures. Transmission failures and disturbances are common stress conditions in the transmission environment. To ensure transmission integrity it is recommended that all the phase movements at the output of the G.82 stay within the level described in the following sections. 0. Short-term Phase Transient Response This requirement reflects the performance of the clock in cases when the (selected) input reference is lost due to a failure in the reference path and a second reference input signal, traceable to the same reference clock, is available simultaneously or shortly after the detection of the failure (e.g. in cases of autonomous restoration). Transient for Type I Node Clocks (2 048 khz and 2 048 kbits/s Interfaces) The MTIE of the phase error should not exceed the limits given in Table 253/G.82 and illustrated by the dashed curve in Figure /G.82. Table 253/G.82 Transient for Type I node clocks (2 048 khz and 2 048 kbits/s interfaces) MTIE limit Observation Interval τ 25 ns 0.00 s < τ < 0.0033 s 75007.5τ ns 0.0033 s< τ < 0.06 s (20 + 0.5τ) ns 0.06 s < τ < 240 s 2400 ns 240 s < τ < 0 000 s Transient for Type I Node Clocks (STM-N Interfaces) The MTIE of the phase error should not exceed the limits given in Table 264/G.82 and illustrated by the solid curve in Figure /G.82. 233
Table 264/G.82 Transient for Type I node clocks (STM-N interfaces) MTIE limit Observation Interval τ 39 ns 0.00 s < τ < 0.0052 s 75007.5τ ns 0.0052 s < τ < 0.06 s (20 + 0.5τ) ns 0.06 s < τ < 240 s 240 ns 240 s < τ < 0 000 s Transient for Type II and III Node Clocks ( 544 kbits/s Interfaces) The MTIE of the phase error should not exceed the limits given in Table 275/G.82 and illustrated by the dashed curve in Figure /G.82. Table 275/G.82 Transient for Type II and III node clocks ( 544 kbits/s interfaces) MTIE limit NA Observation Interval τ τ < 0.00326 s (7.6 + 885τ) ns 0.00326 s < τ < 0.6 s 50 ns 0.6 s < τ Transient for Type II and III Node Clocks (STM-N Interfaces) The MTIE of the phase error should not exceed the limits given in Table 286/G.82 and illustrated by the solid curve in Figure /G.82. 243
Table 286/G.82 Transient for Type II and III node clocks (STM-N interfaces) MTIE limit ND Observation Interval τ τ < 0.040 s 7.6 + 885τ ns 0.040 s < τ < 0.6 s 50 ns 0.6 s < τ < 280 s Transient for Type IV Node Clocks ( 544 kbits/s Interfaces) The MTIE of the phase error should not exceed the limits given in Table 297/G.82 and illustrated by the dashed curve in Figure /G.82. Table 297/G.82 Transient for Type IV node clocks ( 544 kbits/s interfaces) MTIE limit NA Observation Interval τ τ < 0.00326 s 6000τ ns 0.00326 s < τ < 0.064 s 000 ns 0.6 s < τ Transient for Type IV Node Clocks (STM-N Interfaces) The MTIE of the phase error should not exceed the limits given in Table 3028/G.82 and illustrated by the solid curve in Figure /G.82. 253
Table 3028/G.82 Transient for Type IV node clocks (STM-N interfaces) MTIE limit ND Observation Interval τ τ < 0.040 s 7.6 + 885τ ns 0.040 s < τ < 0.5 s 300 + 300τ ns 0.5 s < τ < 2.33 s 000 ns 2.33 s < τ < 280 s 000 240 MTIE (ns) 20 00 STM-N 39 25 E 0 0.00 0.0 0. 0. 0. 00 240 k 3.3 ms 5.2 ms 6 ms Observation Interval τ (s) 0k 263
0 4 0 3 MTIE (ns) 00 0 0 3 0.0 0. 0 00 0 3 0 4 Observation Interval (s) Type I, 2048 khz and kbit/s Type I, STM-N Types II and III, 544 kbit/s Types II and III, STM-N Type IV, 544 kbit/s Type IV, STM-N Figure /G.82 Short-term phase transient mask (MTIE) The output jitter limit in section 7.3 should be met. 0.2 Long-term Phase Transient Response (Holdover) This requirement bounds the maximum excursions in the output timing signal. Additionally, it restricts the accumulation of the phase movement during input signal impairments or internal disturbances. When a G.82 clock loses its reference, it is said to enter the holdover state. The Phase Error, x, at the output of the slave clock relative to the input at the moment of loss of reference should, over any period of S seconds, meet the following: x(s) {(a + a 2 )S + 0.5 b S 2 + c} ns. The derivative of x(s), the frequency, should, over any period of S seconds, meet the following: d( x(s))/ds {a + a 2 + b S} ns/s. The second derivative of x(s), the frequency drift, should, over any period of S seconds, meet the following: d 2 ( x(s))/ds 2 d ns/s 2. NOTE : a represents an initial frequency offset under constant temperature conditions (+/- K). 273
NOTE 2: NOTE 3: NOTE 4: NOTE 5: a 2 accounts for temperature variations after the clock went into holdover. If there are no temperature variations, the term a 2 S should not contribute to the phase error. b represents the average frequency drift caused by ageing. This value is derived from typical ageing characteristics after 60 days of continuous operation. It is not intended to measure this value on a per day basis, as the temperature effect will dominate. The phase offset c takes care of any additional phase shift that may arise during the transition at the entry of the holdover state. d represents the maximum temporary frequency drift rate allowed during holdover. However it is not required that d and b be equal. The permissible phase error specifications for different G.82 clock types are shown in Table 325/G.82. Table 325/G.82 Transient response specifications during holdover at constant temperature (+/- K) Type I Type II Type III Type VIIV Type IV Type VVI Applies for TBD TBD TBD S > 00 s TBD S > 00 s a (ns/s) 0.5 TBD.0TBD 0 50 TBD 0.5 a 2 (ns/s) 2 TBD 0TBD NA 280 TBD NA b (ns/s 2 ) 2.3 0-6 TBD.6 0-5 2.3 0-4 4.63 0-4.6 0-5 TBD TBD c (ns) 60 50 TBD 50 TBD 000 TBD 000 d (ns/s 2 ) NA TBD.6 0-5 TBD NA 4.63 0-4 NA = Not Applicable. TBD = To Be Defined. During the transition at the entry of holdover state, the temporary frequency offset on SDH output interfaces of Type I node clocks should not exceed 7.5 ppm. The daily frequency change for Type II node clocks should not exceed 0-0 per day (.6 0-6 ns/s 2 ). 0.3 Phase Response to Input Signal Interruptions TBD For short term interruptions on synchronisation input signals, that do not cause reference switching, the output phase variation is FFS. 0.4 Phase Discontinuity In cases of infrequent internal testing or rearrangement operations within the slave clock, phase transient at the output of G.82 clocks should meet the MTIE specifications in Table 3226/G.82 for Type I node clock, Table 3327/G.82 for Type II node clock, Table 3428/G.82 for Type III and IV node clocks. NA 283
Table 3226/G.82 Output phase transient (MTIE) for Type I node clock MTIE limit TBD TBD Observation interval τ TBD TBD TBD In case the G.82 Type I clock is built-in into an SDH equipment, the temporary frequency offset at any STM-N output interface should never exceed 7.5 ppm. TBD Table 3327/G.82 Output phase transient (MTIE) for Type II and III node clock MTIE limit NA Observation interval τ τ < 0.00326 s (7.6 + 885τ) ns 0.00326 s < τ < 0.6 s 50 ns 0.6 s < τ Table 3428/G.82 Output phase transient (MTIE) for Type III and Type IV node clocks MTIE limit NA 6000τ ns Observation interval τ τ < 0.00326 s 0.00326 s < τ < 0.6 s 000 ns 0.6 s < τ The resultant requirements are shown in Figure 2/G.82. 293
0000 MTIE (ns) (Log scale) 000 00 8 TYPE IV TYPE II, III 0 7.6 0.00 0.00326 0000 0.0 0. 0.064 0.6 Observation Interval τ (s) (Log scale) 0 000 TYPE III, IV MTIE (ns) (Log scale) 00 8 TYPE II 0 7.6 0.00 0.00326 0.0 0. 0.064 0.6 Observation Interval τ (s) (Log scale) 0 Figure 2/G.82 Output phase transient requirements (MTIE) 303
. Interfaces The requirements in this Recommendation are related to reference points internal to the equipment or Network Element (NE) in which the clock is embedded and are therefore not necessarily available for measurement or analysis by the user. Therefore the performance of the G.82 clock is not defined at these internal reference points, but rather at the external interfaces of the equipment that are used for synchronization. The input and output interfaces in which the G.82 clock may be contained are: 544 kbit/s interfaces according to ITU-T Recommendation 2/G.703. 2048 khz external interfaces according to ITU-T Recommendation 0/G.703. 2048 kbit/s interfaces according to ITU-T Recommendation 6/G.703. STM-N traffic interfaces Note that all of the above interfaces may not be implemented on all equipment. These interfaces should comply with the additional jitter and wander requirements as defined in this document. 33
APPENDIX I (to Rec. G.82) Relationship between TDEV and Power Spectral Density This appendix is provided for information and shows that the power spectral density of phase is given approximately in terms of the TDEV of the phase by 0.75 0. 3 S x ( f ) TDEV f f From Recommendation G.80, sect. II.3, 2 f TDEV( ) ( ) sin 6 ( ) h πnτ 0 f τ = Sϕ f df, 2 2 3( πν nomn) 0 sin ( πτ 0 f ) where ν nom is the nominal frequency (in Hz) of the reference with wander, and nτ 0 = τ, and S ϕ (f) is the power spectral density (PSD) of phase ϕ(t) in radians. Let : Sx( f ) = Sϕ( f ) ( 2πν ) nom be the power spectral density of the time interval error x(t) = ϕ(t) / (2πν nom ) in seconds. If the largest f is f = 0 Hz and the largest τ 0 is τ 0 = 20 ms, then πτ 0 f < 0.628, and n sin(πτ 0 f) n πτ 0 f = πτf, and 6 8 f TDEV( ) ( ) sin ( ) h πτf f h 2 τ = S f = ( ) ( τ, ), 3 0 x df S f H f df 2 ( πτf ) 0 x Eq.() where sin ( πτf ) H( τ, f ) = 8 3. 3 πτf The term S x (f) H 2 (τ,f) is the power spectral density of the phase x(t). Therefore TDEV can be seen as the rms of the phase filtered by a band-bass filter H(τ,f). Figure I. shows H(τ,f) 2 for the values τ = 0.5 s and τ =.0 s. Since H(τ,f) 2 has only 0.85% of its area beyond 20/τ in practice one can use f h = 20/τ with little effect on the calculated value of TDEV. 2 2. 323
.5 H 2 ( τ, f ).0 0.5 Area τ = 0.5 2 τ H 2 ( τ, f ) 0 0 2 3 4 5 6 7 8 0.42 f τ.5.0 τ =.0 0.5 Area 2τ 0 0 2 3 4 5 6 7 8 0.42 f τ Figure I. Frequency response of filter H(t,f) that is part of TDEV calculation Note that the response peaks at f = 0.42/τ, and the area under the curve is /(2τ). If the pass band were very narrow, we would expect 2 Sx ( f ) H( τ, f ) df (/ 2τ ) Sx( 0. 42 / τ ). But because 0 the filter has substantial bandwidth, and because phase tends to have stronger spectral components at low frequencies, a better approximation is Then TDEV is approximated by: 2 Sx ( f ) H( τ, f ) df ( / 2.5τ ) Sx ( 0. 3/ τ ). 0 TDEV( τ) Eq.(2) 0.3 S x. 25. τ τ We can get the inverse relationship the PSD from TDEV by substituting 0.3/f for τ and solving for S x (f): Eq.(3) Sx( f ) 0.75 03. TDEV f f In particular, if TDEV(τ) has a break at τ = τ break, then S x (f) has a break at f = f break, where f break 0.3/τ break. 2. 333
APPENDIX II (to G.82) Measurement Method for Noise Transfer The measurement method recommended here directly tests conformance with the noise transfer specification of Section 9 by applying the TDEV input wander tolerance limit, Figure 4/G.82, as the test signal. The output TDEV characteristic is then directly compared against the specification limit, Figure 0/G.82. Measurement Set-Up The measurement set-up is shown in figure II.. TDEV noise gen. (Calibration) Ref. clock Ref. input SSU under test SSU output Sync. TDEV meas. Figure II. Measurement set-up for TDEV noise transfer characteristics To ensure sufficiently accurate, robust and consistent measurements, the following principles should be applied:. The test signal should be deterministic, yet sufficiently noise-like over a short observation interval. 2. The noise generator should produce a test signal within ±20% of the input noise tolerance specification - Section 8, Figure 4/G.82. 3. At large values of τ, the TDEV results should match the TDEV output mask within ±2 % of the specification - Section 9, Figure 0/G.82. In order to achieve the above levels of accuracy, normalisation and calibration techniques should be applied. In general, the following procedure is recommended: 343
. Perform a calibration measurement sequence, without the slave clock under test - TDEV(cal). This obtains the raw test signal characteristics. 2. Calculate a correction factor with respect to the required input wander tolerance specification - TDEV(ref). This now represents the ideal test signal. 3. Measure TDEV(dat) of the slave clock under test under the same conditions as the calibration sequence. 4. Normalise TDEV(dat) using TDEV(ref) - obtaining TDEV(meas). 5. TDEV(meas) may now be directly compared with the noise transfer specification limit. Functional model of TDEV noise generator The noise generator shown in Figure II. can be described by the functional diagram in Figure II.2. It does not imply a specific implementation, but defines the key characteristics that should be observed in order to meet the measurement objectives above. A suitable noise generator can, for example, be constructed with a PRBS sequence of 2 3 -, generated at 6.4 khz. PRBS Generator Period >50 hrs Invert every other bit Low-pass Filter TDEV weighting filter Clock Phase Modulation Frequency spectrum 0-0 Hz +/- db Phase characteristic TDEV(t) +/- 20 % Figure II.2 Functional model of TDEV noise generator 353