CC1000 Single Chip Very Low Power RF Transceiver

Single Chip Very Low Power RF Transceiver Applications Very low power UHF wireless data transmitters and receivers 315 / 433 / 868 and 915 MHz ISM/SRD band systems RKE Two-way Remote Keyless Entry Home automation Wireless alarm and security systems AMR Automatic Meter Reading Low power telemetry Toys Product Description is a true single-chip UHF transceiver designed for very low power and very low voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-1000 MHz range. is based on Chipcon s SmartRF technology in 0.35 µm CMOS. The main operating parameters of can be programmed via an easy-tointerface serial bus, thus making a very flexible and easy to use transceiver. In a typical system will be used together with a microcontroller and a few external passive components. Features True single chip UHF RF transceiver Very low current consumption Frequency range 300 1000 MHz Integrated bit synchroniser High sensitivity (typical -110 dbm at 2.4 kbaud) Programmable output power 20 to 10 dbm Small size (TSSOP-28 package) Low supply voltage (2.1 V to 3.6 V) Very few external components required No external RF switch / IF filter required RSSI output Single port antenna connection FSK data rate up to 76.8 kbaud Complies with EN 300 220 and FCC CFR47 part 15 FSK modulation spectrum shaping Programmable frequency in 250 Hz steps makes crystal temperature drift compensation possible without TCXO Suitable for frequency hopping protocols Development kit available Easy-to-use software for generating the configuration data This document contains information on a pre-production product. Specifications and information herein are subject to change without notice. Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 1 of 48

Pin Assignment Pin no. Pin name Pin type Description 1 AVDD Power (A) Power supply (3 V) for analog modules (mixer and IF) 2 AGND Ground (A) Ground connection (0 V) for analog modules (mixer and IF) 3 RF_IN RF Input RF signal input from antenna 4 RF_OUT RF output RF signal output to antenna 5 AVDD Power (A) Power supply (3 V) for analog modules (LNA and PA) 6 AGND Ground (A) Ground connection (0 V) for analog modules (LNA and PA) 7 AGND Ground (A) Ground connection (0 V) for analog modules (PA) 8 AGND Ground (A) Ground connection (0 V) for analog modules (VCO and prescaler) 9 AVDD Power (A) Power supply (3 V) for analog modules (VCO and prescaler) 10 L1 Analog input Connection no 1 for external VCO tank inductor 11 L2 Analog input Connection no 2 for external VCO tank inductor 12 CHP_OUT (LOCK) Analog output Charge pump current output The pin can also be used as PLL Lock indicator. Output is high when PLL is in lock. 13 R_BIAS Analog output Connection for external precision bias resistor (82 kω, ± 1%) 14 AGND Ground (A) Ground connection (0 V) for analog modules (backplane) 15 AVDD Power (A) Power supply (3 V) for analog modules (general) 16 AGND Ground (A) Ground connection (0 V) for analog modules (general) 17 XOSC_Q2 Analog output Crystal, pin 2 18 XOSC_Q1 Analog input Crystal, pin 1, or external clock input 19 AGND Ground (A) Ground connection (0 V) for analog modules (guard) 20 DGND Ground (D) Ground connection (0 V) for digital modules (substrate) 21 DVDD Power (D) Power supply (3 V) for digital modules 22 DGND Ground (D) Ground connection (0 V) for digital modules 23 DIO Digital input/output Data input/output. Data input in transmit mode. Data output in receive mode 24 DCLK Digital output Data clock for data in both receive and transmit mode 25 PCLK Digital input Programming clock for 3-wire bus 26 PDATA Digital input/output Programming data for 3-wire bus. Programming data input for write operation, programming data output for read operation 27 PALE Digital input Programming address latch enable for 3-wire bus. Internal pull-up. 28 RSSI/IF Analog output The pin can be used as RSSI or 10.7 MHz IF output to optional external IF and demodulator. If not used, the pin should be left open (not connected). A=Analog, D=Digital (Top View) AVDD 1 AGND 2 RF_IN 3 RF_OUT 4 AVDD 5 AGND 6 AGND 7 AGND 8 AVDD 9 L1 10 L2 11 CHP_OUT 12 R_BIAS 13 AGND 14 15 28 RSSI/IF 27 PALE 26 PDATA 25 PCLK 24 DCLK 23 DIO 22 DGND 21 DVDD 20 DGND 19 AGND 18 XOSC_Q1 17 XOSC_Q2 16 AGND AVDD Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 2 of 48

Absolute Maximum Ratings Parameter Min. Max. Units Condition Supply voltage, VDD -0.3 5.0 V Voltage on any pin -0.3 VDD+0.3, V max 5.0 Input RF level 10 dbm Storage temperature range -50 150 C Operating ambient temperature -40 85 C range Lead temperature 260 C T = 10 s Under no circumstances the absolute maximum ratings given above should be violated. Stress exceeding one or more of the limiting s may cause permanent damage to the device. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Electrical Specifications Tc = 25 C, VDD = 3.0 V if nothing else stated Parameter Min. Typ. Max. Unit Condition / Note Overall RF Frequency Range 300 1000 MHz Programmable in steps of 250 Hz Transmit Section Transmit data rate 0.6 76.8 kbaud NRZ or Manchester encoding. 76.8 kbaud equals 76.8 kbit/s using NRZ coding. See page 14. Binary FSK frequency separation 0 65 khz The frequency corresponding to the digital "0" is denoted f 0, while f 1 corresponds to a digital "1". The frequency separation is f 1-f 0. The RF carrier frequency, f c, is then given by f c=(f 0+f 1)/2. (The frequency deviation is given by f d=+/-(f 1-f 0)/2 ) The frequency separation is programmable in 250 Hz steps. 65 khz is the minimum guaranteed separation at 1 MHz reference frequency. Larger separations can be achieved at higher reference frequencies. Output power 433 MHz 868 MHz -20-20 10 5 dbm Delivered to 50 Ω load. The output power is programmable. RF output impedance 433/868 MHz 140 / 80 Ω Transmit mode. For matching details see Input/ output matching p.28. Harmonics -20 dbc An external LC or SAW filter should be used to reduce harmonics emission to comply with SRD requirements. See p.34. Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 3 of 48

Receive Section Parameter Min. Typ. Max. Unit Condition / Note Receiver Sensitivity, 433 MHz Optimum sensitivity (9.3 ma) Low current consumption (7.4 ma) -110-109 dbm 2.4 kbaud, Manchester coded data, 64 khz frequency separation, BER = 10-3 Receiver Sensitivity, 868 MHz Optimum sensitivity (11.8 ma) Low current consumption (9.6 ma) -107-105 dbm See Table 5 and Table 6 page 19 for typical sensitivity figures at other data rates. System noise bandwidth 30 khz 2.4 kbaud, Manchester coded data Cascaded noise figure 433/868 MHz 12/13 db Saturation 10 dbm 2.4 kbaud, Manchester coded data, BER = 10-3 Input IP3-18 dbm From LNA to IF output Blocking 40 dbc At +/- 1 MHz LO leakage -57 dbm Input impedance 88-j26 70-j26 52-j7 52-j4 Ω Ω Ω Ω Receive mode, series equivalent at 315 MHz at 433 MHz at 868 MHz. at 915 MHz For matching details see Input/ output matching p. 28. Turn on time 11 128 Baud The turn-on time is determined by the demodulator settling time, which is programmable. See p. 17 IF Section Intermediate frequency (IF) 150 10.7 khz MHz Internal IF filter External IF filter IF bandwidth 175 khz RSSI dynamic range -105-50 dbm RSSI accuracy ± 6 db See p.30 for details RSSI linearity ± 2 db Frequency Synthesiser Section Crystal Oscillator Frequency 3 16 MHz Crystal frequency can be 3-4, 6-8 or 9-16 MHz. Recommended frequencies are 3.6864, 7.3728, 11.0592 and 14.7456. See page 32 for details. Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 4 of 48

Parameter Min. Typ. Max. Unit Condition / Note Crystal frequency accuracy requirement ± 50 ± 25 ppm 433 MHz 868 MHz The crystal frequency accuracy and drift (ageing and temperature dependency) will determine the frequency accuracy of the transmitted signal. Crystal operation Parallel C171 and C181 are loading capacitors, see page 32 Crystal load capacitance 12 12 12 22 16 16 30 30 16 pf pf pf 3-8 MHz, 22 pf recommended 6-8 MHz, 16 pf recommended 9-16 MHz, 16 pf recommended Crystal oscillator start-up time 5 1.5 2 ms ms ms 3.6864 MHz, 16 pf load 7.3728 MHz, 16 pf load 16 MHz, 16 pf load Output signal phase noise -85 dbc/hz At 100 khz offset from carrier PLL lock time (RX / TX turn time) 200 µs Up to 1 MHz frequency step PLL turn-on time, crystal oscillator on in power down mode 250 µs Crystal oscillator running Digital Inputs/Outputs Logic "0" input voltage 0 0.3*VDD V Logic "1" input voltage 0.7*VDD VDD V Logic "0" output voltage 0 0.4 V Output current -2.5 ma, 3.0 V supply voltage Logic "1" output voltage 2.5 VDD V Output current 2.5 ma, 3.0 V supply voltage Logic "0" input current NA -1 µa Input signal equals GND Logic "1" input current NA 1 µa Input signal equals VDD DIO setup time 20 ns TX mode, minimum time DIO must be ready before the positive edge of DCLK DIO hold time 10 ns TX mode, minimum time DIO must be held after the positive edge of DCLK Serial interface (PCLK, PDATA and PALE) timing specification See Table 2 page 12 Power Supply Supply voltage 3.0 V Recommended operation voltage 2.1 3.6 V Operating limits Power Down mode 0.2 1 µa Oscillator core off Current Consumption, receive mode 433/868 MHz Current Consumption, average in receive mode using polling 433/868 MHz 7.4/9.6 ma Current is programmable and can be increased for improved sensitivity 74/96 µa Polling controlled by microcontroller using 1:100 receive to power down ratio Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 5 of 48

Parameter Min. Typ. Max. Unit Condition / Note Current Consumption, transmit mode 433/868 MHz: P=0.01mW (-20dBm) P=0.3mW (-5dBm) 5.3/8.6 8.9/13.8 ma ma The ouput power is delivered to a 50Ω load, see also p. 29 P=1mW (0dBm) 10.4/16.5 ma P=3mW (5dBm) 14.8/25.4 ma P=10mW (10dBm) 26.7/NA ma Current Consumption, crystal osc. 30 80 105 µa 3-8 MHz, 16 pf load 9-14 MHz, 12 pf load 14-16 MHz, 16 pf load Current Consumption, crystal osc. and bias 860 µa Current Consumption, crystal osc., bias and synthesiser, RX/TX 4/5 5/6 ma ma < 500 MHz > 500 MHz Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 6 of 48

Circuit Description RSSI/IF MIXER RF_IN LNA IF STAGE DEMOD CONTROL 3 DIO DCLK PDATA, PCLK, PALE RF_OUT PA ~ /N BIAS VCO CHARGE LPF PD /R OSC PUMP R_BIAS XOSC_Q2 XOSC_Q1 L1 L2 CHP_OUT Figure 1. Simplified block diagram of the A simplified block diagram of is shown in Figure 1. Only signal pins are shown. In receive mode is configured as a traditional superheterodyne receiver. The RF input signal is amplified by the lownoise amplifier (LNA) and converted down to the intermediate frequency (IF) by the mixer (MIXER). In the intermediate frequency stage (IF STAGE) this downconverted signal is amplified and filtered before being fed to the demodulator (DEMOD). As an option a RSSI signal, or the IF signal after the mixer is available at the RSSI/IF pin. After demodulation outputs the digital demodulated data on the pin DIO. Synchronisation is done on-chip providing data clock at DCLK. In transmit mode the voltage controlled oscillator (VCO) output signal is fed directly to the power amplifier (PA). The RF output is frequency shift keyed (FSK) by the digital bit stream fed to the pin DIO. The internal T/R switch circuitry makes the antenna interface and matching very easy. The frequency synthesiser generates the local oscillator signal which is fed to the MIXER in receive mode and to the PA in transmit mode. The frequency synthesiser consists of a crystal oscillator (XOSC), phase detector (PD), charge pump (CHARGE PUMP), VCO, and frequency dividers (/R and /N). An external crystal must be connected to XOSC, and only an external inductor is required for the VCO. The 3-wire digital serial interface (CONTROL) is used for configuration. Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 7 of 48

Application Circuit Very few external components are required for the operation of. A typical application circuit is shown in Figure 2. Component s are shown in Table 1. Input / output matching C31/L32 is the input match for the receiver, and L32 is also a DC choke for biasing. C41, L41 and C42 are used to match the transmitter to 50 Ohm. An internal T/R switch circuit makes it possible to connect the input and output together and match the to 50 Ω in both RX and TX mode. See Input/output matching p.28 for details. VCO inductor The VCO is completely integrated except for the inductor L101. Component s for the matching network and VCO inductor are easily calculated using the SmartRF Studio software. Additional filtering Additional external components (e.g. RF LC or SAW-filter) may be used in order to improve the performance in specific applications. See also Optional LC filter p.34 for further information. Voltage supply decoupling C10-C16 are voltage supply de-coupling capacitors. These capacitors should be placed as close as possible to the voltage supply pins of. AVDD=3V Monopole antenna (50 Ohm) LC or SAW filter Optional C10 C11 C31 C42 C41 L41 AVDD=3V C12 C13 L32 C14 R131 L101 NC 1 28 AVDD RSSI/IF 2 27 AGND PALE 3 26 RF_IN PDATA 4 25 RF_OUT PCLK 5 24 AVDD DCLK 6 23 AGND DIO 7 22 AGND DGND 8 21 AGND DVDD 9 20 AVDD DGND 10 19 L1 AGND 11 18 L2 XOSC_Q1 12 17 CHP_OUT XOSC_Q2 13 16 R_BIAS AGND 14 15 AGND AVDD NC TO/FROM MICROCONTROLLER DVDD=3V C15 C16 XTAL C171 C181 Figure 2. Typical application circuit Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 8 of 48

Item 315 MHz 433 MHz 868 MHz 915 MHz C10 33 nf, 10%, X7R, 0805 33 nf, 10%, X7R, 0805 33 nf, 10%, X7R, 0805 33 nf, 10%, X7R, 0805 C11 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 C12 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 C13 220 pf, 10%, C0G, 0603 220 pf, 10%, C0G, 0603 220 pf, 10%, C0G, 0603 220 pf, 10%, C0G, 0603 C14 220 pf, 10%, C0G, 0603 220 pf, 10%, C0G, 0603 220 pf, 10%, C0G, 0603 220 pf, 10%, C0G, 0603 C15 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 1 nf, 10%, X7R, 0603 C16 33 nf, 10%, X7R, 0805 33 nf, 10%, X7R, 0805 33 nf, 10%, X7R, 0805 33 nf, 10%, X7R, 0805 C31 8.2 pf, 5%, C0G, 0603 15 pf, 5%, C0G, 0603 10 pf, 5%, C0G, 0603 10 pf, 5%, C0G, 0603 C41 2.2 pf, 5%, C0G, 0603 8.2 pf, 5%, C0G, 0603 Not used Not used C42 5.6 pf, 5%, C0G, 0603 5.6 pf, 5%, C0G, 0603 4.7 pf, 5%, C0G, 0603 4.7 pf, 5%, C0G, 0603 C141 18 pf, 5%, C0G, 0603 18 pf, 5%, C0G, 0603 18 pf, 5%, C0G, 0603 18 pf, 5%, C0G, 0603 C151 18 pf, 5%, C0G, 0603 18 pf, 5%, C0G, 0603 18 pf, 5%, C0G, 0603 18 pf, 5%, C0G, 0603 L32 39 nh, 10%, 0805 (Coilcraft 0805CS-390XKBC) L41 20 nh, 10%, 0805 (Coilcraft 0805HQ-20NXKBC) L101 56 nh, 5%, 0805 (Koa KL732ATE56NJ) 68 nh, 10%, 0805 (Coilcraft 0805CS-680XKBC) 6.2 nh, 10%, 0805 (Coilcraft 0805HQ-6N2XKBC) 33 nh, 5%, 0805 (Koa KL732ATE33NJ) 120 nh, 10%, 0805 (Coilcraft 0805CS-121XKBC) 2.5 nh, 10%, 0805 (Coilcraft 0805HQ-2N5XKBC) 4.7 nh, 5%, 0805 (Koa KL732ATE4N7C) 120 nh, 10%, 0805 (Coilcraft 0805CS-121XKBC) 2.5 nh, 10%, 0805 (Coilcraft 0805HQ-2N5XKBC) 4.7 nh, 5%, 0805 (Koa KL732ATE4N7C) R131 82 kω, 1%, 0603 82 kω, 1%, 0603 82 kω, 1%, 0603 82 kω, 1%, 0603 XTAL 14.7456 MHz crystal, 16 pf load 14.7456 MHz crystal, 16 pf load 14.7456 MHz crystal, 16 pf load 14.7456 MHz crystal, 16 pf load Note: Items shaded are different for different frequencies Table 1. Bill of materials for the application circuit Note that the component s for 868/915 MHz can be the same. However, it is important the layout is optimised for the selected VCO inductor in order to centre the tuning range around the operating frequency to account for inductor tolerance. The VCO inductor must be placed very close and symmetrical with respect to the pins (L1 and L2). Chipcon provide reference layouts that should be followed very closely in order to achieve the best performance. The PP Plug & Play reference design can be downloaded from the Chipcon website. Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 9 of 48

Configuration Overview can be configured to achieve the best performance for different applications. Through the programmable configuration registers the following key parameters can be programmed: Receive / transmit mode RF output power Frequency synthesiser key parameters: RF output frequency, FSK frequency separation (deviation), crystal oscillator reference frequency Power-down / power-up mode Crystal oscillator power-up / power down Data rate and data format (NRZ, Manchester coded or UART interface) Synthesiser lock indicator mode Optional RSSI or external IF Configuration Software Chipcon provides users of with a software program, SmartRF Studio (Windows interface) that generates all necessary configuration data based on the user's selections of various parameters. These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of. In addition the program will provide the user with the component s needed for the input/output matching circuit and the VCO inductor. Figure 3 shows the user interface of the configuration software. Figure 3. SmartRF Studio user interface Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 10 of 48

3-wire Serial Configuration Interface is configured via a simple 3-wire interface (PDATA, PCLK and PALE). There are 36 8-bit configuration registers, each addressed by a 7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of requires sending 29 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time needed for a full configuration depend on the PCLK frequency. With a PCLK frequency of 10 MHz the full configuration is done in less than 60 µs. Setting the device in power down mode requires sending one frame only and will in this case take less than 2 µs. All registers are also readable. In each write-cycle 16 bits are sent on the PDATA-line. The seven most significant bits of each data frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the first bit. The next bit is the R/W bit (high for write, low for read). During address and R/W bit transfer the PALE (Program Address Latch Enable) must be kept low. The 8 data-bits are then transferred (D7:0). See Figure 4. T SA T HA The timing for the programming is also shown in Figure 4 with reference to Table 2. The clocking of the data on PDATA is done on the negative edge of PCLK. When the last bit, D0, of the 8 data-bits has been loaded, the data word is loaded in the internal configuration register. The configuration data is stored in internal RAM. The data is retained during powerdown mode, but not when the powersupply is turned off. The registers can be programmed in any order. The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. then returns the data from the addressed register. PDATA is in this case used as an output and must be tri-stated (or set high n the case of an open collector pin) by the microcontroller during the data read-back (D7:0). The read operation is illustrated in Figure 5. T CH,min T CL,min T SA T HD T SD PCLK PDATA Address Write mode Data byte 6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 PALE Figure 4. Configuration registers write operation Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 11 of 48

PCLK PDATA Address Read mode Data byte 6 5 4 3 2 1 0 R 7 6 5 4 3 2 1 0 PALE Figure 5. Configuration registers read operation Parameter Symbol Min Max Units Conditions PCLK, clock frequency PCLK low pulse duration PCLK high pulse duration PALE setup time PALE hold time PDATA setup time PDATA hold time F CLOCK - 10 MHz T CL,min 50 ns The minimum time PCLK must be low. T CH,min 50 ns The minimum time PCLK must be high. T SA 10 - ns The minimum time PALE must be low before negative edge of PCLK. T HA 10 - ns The minimum time PALE must be held low after the positive edge of PCLK. T SD 10 - ns The minimum time data on PDATA must be ready before the negative edge of PCLK. T HD 10 - ns The minimum time data must be held at PDATA, after the negative edge of PCLK. Rise time T rise 100 ns The maximum rise time for PCLK and PALE Fall time T fall 100 ns The maximum fall time for PCLK and PALE Note: The set-up- and hold-times refer to 50% of VDD. Table 2. Serial interface, timing specification Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 12 of 48

Microcontroller Interface Used in a typical system, will interface to a microcontroller. This microcontroller must be able to: Program into different modes via the 3-wire serial configuration interface (PDATA, PCLK and PALE). Interface to the bi-directional synchronous data signal interface (DIO and DCLK). Optionally the microcontroller can do data encoding / decoding. Optionally the microcontroller can monitor the frequency lock status from pin CHP_OUT (LOCK). Optionally the microcontroller can monitor the RSSI output for signal strength acquisition. Connecting the microcontroller The microcontroller uses 3 output pins for the configuration interface (PDATA, PCLK and PALE). PDATA should be a bidirectional pin for data read-back. A bidirectional pin is used for data (DIO) to be transmitted and data received. DCLK providing the data timing should be connected to a microcontroller input. Optionally another pin can be used to monitor the LOCK signal (available at the CHP_OUT pin). This signal is logic level high when the PLL is in lock. See Figure 6. Also the RSSI signal can be connected to the microcontroller if it has an analogue ADC input. The microcontroller pins connected to PDATA and PCLK can be used for other purposes when the configuration interface is not used. PDATA and PCLK are high impedance inputs as long as PALE is not activated. PDATA PCLK PALE DIO DCLK CHP_OUT (LOCK) RSSI/IF (Optional) (Optional) ADC PALE has an internal pull-up resistor and should be left open (tri-stated by the microcontroller) or set to a high level during power down mode in order to prevent a trickle current flowing in the pullup. Microcontroller Figure 6. Microcontroller interface Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 13 of 48

Signal interface The signal interface consists of DIO and DCLK and is used for the data to be transmitted and data received. DIO is the bi-directional data line and DCLK provides a synchronous clock both during data transmission and data reception. The can be used with NRZ (Non- Return-to-Zero) data or Manchester (also known as bi-phase-level) encoded data. can also synchronise the data from the demodulator and provide the data clock at DCLK. can be configured for three different data formats: Synchronous NRZ mode. In transmit mode provides the data clock at DCLK, and DIO is used as data input. Data is clocked into at the rising edge of DCLK. The data is modulated at RF without encoding. can be configured for the data rates 0.6, 1.2, 2.4, 4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s. For 38.4 and 76.8 kbit/s a crystal frequency of 14.7456 MHz must be used. In receive mode does the synchronisation and provides received data clock at DCLK and data at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 7. Synchronous Manchester encoded mode. In transmit mode provides the data clock at DCLK, and DIO is used as data input. Data is clocked into at the rising edge of DCLK and should be in NRZ format. The data is modulated at RF with Manchester code. The encoding is done by. In this mode can be configured for the data rates 0.3, 0.6, 1.2, 2.4, 4.8, 9.6, 19.2 or 38.4 kbit/s. The 38.4 kbit/s rate corresponds to the maximum 76.8 kbaud due to the Manchester encoding. For 38.4 and 76.8 kbaud a crystal frequency of 14.7456 MHz must be used. In receive mode does the synchronisation and provides received data clock at DCLK and data at DIO. does the decoding and NRZ data is presented at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 8. Transparent Asynchronous UART mode. In transmit mode DIO is used as data input. The data is modulated at RF without synchronisation or encoding. In receive mode the raw data signal from the demodulator is sent to the output. No synchronisation or decoding of the signal is done in and should be done by the interfacing circuit. The DCLK pin is used as data output in this mode. Data rates in the range from 0.6 to 76.8 kbaud can be used. For 38.4 and 76.8 kbaud a crystal frequency of 14.7456 MHz must be used. See Figure 9. Manchester encoding and decoding In the Synchronous Manchester encoded mode uses Manchester coding when modulating the data. The also performs the data decoding and synchronisation. The Manchester code is based on transitions; a 0 is encoded as a low-to-high transition, a 1 is encoded as a high-to-low transition. See Figure 10. The can detect a Manchester decoding violation and will set a Manchester Violation Flag when such a violation is detected in the incoming signal. The threshold limit for the Manchester Violation can be set in the MODEM1 register. The Manchester Violation Flag can be monitored at the CHP_OUT (LOCK) pin, configured in the LOCK register. The Manchester code ensures that the signal has a constant DC component, which is necessary in some FSK demodulators. Using this mode also ensures compatibility with CC400/CC900 designs. Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 14 of 48

Transmitter side: DIO Data provided by microcontroller DCLK Clock provided by RF FSK modulating signal (NRZ), internal in Receiver side: RF DCLK Demodulated signal (NRZ), internal in Clock provided by DIO Data provided by Figure 7. Synchronous NRZ mode Transmitter side: DIO Data provided by microcontroller (NRZ) DCLK Clock provided by RF FSK modulating signal (Manchester encoded), internal in Receiver side: RF DCLK Demodulated signal (Manchester encoded), internal in Clock provided by DIO Data provided by (NRZ) Figure 8. Synchronous Manchester encoded mode Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 15 of 48

Transmitter side: DIO Data provided by UART (TXD) DCLK RF PCLK is not used in transmit mode. Used as data output in receive mode. FSK modulating signal, internal in Receiver side: RF DIO DCLK Demodulated signal, internal in DIO is not used in receive mode. Used only as data input in transmit mode. Synchronised data output provided by. Connect to UART (RXD). Figure 9. Transparent Asynchronous UART mode 1 0 1 1 0 0 0 1 1 0 1 TX data Figure 10. Manchester encoding Time Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 16 of 48

Bit synchroniser and data decision The built-in bit synchroniser extracts the data rate and performs data decision. The data decision is done using over-sampling and digital filtering of the incoming signal. This improves the reliability of the data transmission. Using the synchronous modes simplifies the data-decoding task substantially. All modes need a DC balanced preamble for the internal data slicer to acquire correct comparison level from an averaging filter. The suggested preamble is a 010101 bit pattern. The same bit pattern should also be used in Manchester mode, giving a 011001100110 chip pattern. This is necessary for the bit synchronizer to synchronize correctly. The minimum length of the preamble depends on the acquisition mode selected. The locking of the averaging filter can be done through the configuration interface, or it can be done automatically after a predefined time (LOCK_AVG_MODE in MODEM1). In a polled receiver system the automatic locking can be used. This is illustrated in Figure 11. If the receiver is operated continuously and searching for a preamble, the averaging filter should be locked manually as soon as the preamble is detected. This is shown in Figure 12. If the data is Manchester coded there is no need to lock the averaging filter as shown in Figure 13. The minimum number of balanced bauds ( chips ) depends on the settling time of the averaging filter which is set by SETTLING in MODEM1. Table 3 gives the minimum recommended number of chips for the preamble in NRZ and UART modes. In this context chips refer to the data coding. Using Manchester coding every bit consists of two chips. If Manchester coding is used, there is no need to lock the averaging filter and it can be left free-running (LOCK_AVG_IN in MODEM1). Table 4 gives the the minimum recommended number of bauds (chips) for the preamble in Manchester mode. Settling SETTLING* Manual Lock NRZ mode LOCK_AVG_MODE =1 LOCK_AVG_IN = 0 1** Manual Lock UART mode LOCK_AVG_MODE =1 LOCK_AVG_IN = 0 1** Automatic Lock NRZ mode LOCK_AVG_MODE =0 LOCK_AVG_IN = X*** Automatic Lock UART mode LOCK_AVG_MODE =0 LOCK_AVG_IN = X*** 00 14 11 16 16 01 25 22 32 32 10 46 43 64 64 11 89 86 128 128 Notes: *All configuration bits are in the MODEM1 register ** The averaging filter is locked when LOCK_AVG_IN is set to 1 *** X = Do not care. The timer for the automatic lock is started when RX mode is set in the MAIN register Table 3. Minimum number of balanced bauds (chips) in the preamble in NRZ and UART modes Settling Free-running Manchester mode SETTLING* LOCK_AVG_MODE =1 LOCK_AVG_IN = 0 00 23 01 34 10 55 11 98 Note: *All configuration bits are in the MODEM1 register Table 4. Minimum number of balanced bauds (chips) in the preamble in Manchester mode Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 17 of 48

Data package to be received Noise Preamble NRZ data Noise RX PD RX Averaging filter free-running / not used Averaging filter locked Automatically locked after a short period depending on SETTLING Figure 11. Automatic locking of the averaging filter Data package to be received Noise Preamble NRZ data Noise PD RX Averaging filter free-running Averaging filter locked Manually locked after preamble is detected Figure 12. Manual locking of the averaging filter Data package to be received Noise Preamble Manchester encoded data Noise PD RX Averaging filter always free-running Figure 13. Free-running averaging filter Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 18 of 48

Receiver sensitivity versus data rate and frequency separation The receiver sensitivity depends on the data rate, the data format, FSK frequency separation and the RF frequency. Typical figures for the receiver sensitivity (BER = 10-3 ) are shown in Table 5 for 64 khz frequency separations and Table 6 for 20 khz. Optimised sensitivity configurations are used. For best performance the frequency separation should be as high as possible especially at high data rates. Table 7 shows the sensitivity for low current settings. See page 25 for how to program different current consumption. Data rate Separation 433 MHz 868 MHz [kbaud] [khz] NRZ mode Manchester mode UART mode NRZ mode Manchester mode UART mode 0.6 64-113 -114-113 -110-111 -110 1.2 64-111 -112-111 -108-109 -108 2.4 64-109 -110-109 -106-107 -106 4.8 64-107 -108-107 -104-105 -104 9.6 64-105 -106-105 -102-103 -102 19.2 64-103 -104-103 -100-101 -100 38.4 64-102 -103-102 -98-99 -98 76.8 64-100 -101-100 -97-98 -97 Average current consumption 9.3 ma 11.8 ma Table 5. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3, frequency separation 64 khz, normal current settings Data rate Separation 433 MHz 868 MHz [kbaud] [khz] NRZ mode Manchester mode UART mode NRZ mode Manchester mode UART mode 0.6 20-109 -111-109 -106-108 -106 1.2 20-108 -110-108 -104-106 -104 2.4 20-106 -108-106 -103-105 -103 4.8 20-104 -106-104 -101-103 -101 9.6 20-103 -104-103 -100-101 -100 19.2 20-102 -103-102 -99-100 -99 38.4 20-98 -100-98 -98-99 -98 76.8 20-94 -98-94 -94-96 -94 Average current consumption 9.3 ma 11.8 ma Table 6. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3, frequency separation 20 khz, normal current settings Data rate Separation 433 MHz 868 MHz [kbaud] [khz] NRZ mode Manchester mode UART mode NRZ mode Manchester mode UART mode 0.6 64-111 -113-111 -107-109 -107 1.2 64-110 -111-110 -106-107 -106 2.4 64-108 -109-108 -104-105 -104 4.8 64-106 -107-106 -102-103 -102 9.6 64-104 -105-104 -100-101 -100 19.2 64-102 -103-102 -98-99 -98 38.4 64-101 -102-101 -96-97 -96 76.8 64-99 -100-99 -95-96 -95 Average current consumption 7.4 ma 9.6 ma Table 7. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3, frequency separation 64 khz, low current settings Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 19 of 48

Frequency programming The operation frequency is set by programming the frequency word in the configuration registers. There are two frequency words registers, termed A and B, which can be programmed to two different frequencies. One of the frequency words can be used for RX (local oscillator frequency) and other for TX (transmitting frequency) in order to be able to switch very fast between RX mode and TX mode. They can also be used for RX (or TX) at two different channels. Frequency word A or B is selected by the F_REG bit in the MAIN register. The frequency word is 24 bits (3 bytes) located in FREQ_2A:FREQ_1A:FREQ_0A and FREQ_2B:FREQ_1B:FREQ_0B for the A and B word respectively. FREQ + 8192 fvco = f ref 16384 where the reference frequency is the crystal oscillator clock divided by REFDIV (4 bits in the PLL register), a number between 2 and 15: f xosc f ref = REFDIV The equation above gives the VCO frequency, that is, f VCO is the LO frequency for receive mode, and the f 0 frequency for transmit mode (lower FSK frequency). The upper FSK frequency is given by: f 1 = f 0 + f sep where f sep is set by the separation word: The FSK frequency separation is programmed in the FSEP1:FSEP0 registers (11 bits). The frequency word FREQ is calculated by: f sep = f ref FSEP 16384 Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 20 of 48

Recommended settings for ISM frequencies Shown in Table 8 are the recommended frequency synthesiser settings for a few operating frequencies in the popular ISM bands. These settings ensure optimum configuration of the synthesiser in receive mode for best sensitivity. For some settings of the synthesiser (combinations of RF frequencies and reference frequency), the receiver sensitivity is degraded. The performance of the transmitter is not affected by the settings, but recommended transmitter settings are included for completeness. The FSK frequency separation is set to 64 khz. The SmartRF Studio can be used to generate optimised configuration data as well. Also an application note (AN011) and a spreadsheet are available from Chipcon generating configuration data for any frequency giving optimum sensitivity. ISM Frequency [MHz] Actual frequency [MHz] Crystal frequency [MHz] Low-side / high- side LO* Reference divider REFDIV Frequency word RX mode FREQ Frequency word TX mode FREQ Frequency seperation FSEP 315 315.037200 7.3728 High-side 7 4894720 4891888 995 11.0592 10 4661248 4658551 948 433.3 433.302000 3.6864 Low-side 3 5767168 5768741 853 7.3728 6 5767168 5768741 853 11.0592 9 5767168 5768741 853 433.9 433.916400 3.6864 Low-side 3 5775360 5776933 853 7.3728 6 5775360 5776933 853 11.0592 9 5775360 5776933 853 434.5 434.530800 3.6864 Low-side 3 5783552 5785125 853 7.3728 6 5783552 5785125 853 11.0592 9 5783552 5785125 853 868.3 868.297200 3.6864 Low-side 2 7708672 7709720 568 7.3728 4 7708672 7709720 568 11.0592 5 6422528 6423402 474 868.95 868.918800 3.6864 High-side 2 7716864 7715246 568 7.3728 4 7716864 7715246 568 11.0592 6 7716864 7715246 568 869.525 869.526000 3.6864 Low-side 3 11583488 11585061 853 7.3728 6 11583488 11585061 853 11.0592 9 11583488 11585061 853 869.85 869.840400 3.6864 High-side 2 7725056 7723438 568 7.3728 4 7725056 7723438 568 11.0592 6 7725056 7723438 568 915 914.998800 3.6864 High-side 2 8126464 8124846 568 7.3728 4 8126464 8124846 568 11.0592 6 8126464 8124846 568 *Note: When using low-side LO injection the data at DIO will be inverted. Table 8. Recommended settings for ISM frequencies Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 21 of 48

VCO Only one external inductor (L101) is required for the VCO. The inductor will determine the operating frequency range of the circuit. It is important to place the inductor as close to the pins as possible in order to reduce stray inductance. It is recommended to use a high Q, low tolerance inductor for best performance. Typical tuning range for the integrated varactor is 20-25%. Component s for various frequencies are given in Table 1. Component s for other frequencies can be found using the SmartRF Studio software. VCO and PLL self-calibration To compensate for supply voltage, temperature and process variations the VCO and PLL must be calibrated. The calibration is done automatically and sets maximum VCO tuning range and optimum charge pump current for PLL stability. After setting up the device at the operating frequency, the self-calibration can be initiated by setting the CAL_START bit. The calibration result is stored internally in the chip, and is valid as long as power is not turned off. If large supply voltage variations (more than 0.5 V) or temperature variations (more than 40 degrees) occur after calibration, a new calibration should be performed. The self-calibration is controlled through the CAL register (see configuration registers description p. 37). The CAL_COMPLETE bit indicates complete calibration. The user can poll this bit, or simply wait for 34 ms (calibration wait time when CAL_WAIT = 1). The wait time is proportional to the internal PLL reference frequency. The lowest permitted reference frequency (1 MHz) gives 34 ms wait time, which is therefore the worst case. Reference frequency [MHz] Calibration time [ms] 2.4 14 2.0 17 1.5 23 1.0 34 The CAL_COMPLETE bit can also be monitored at the CHP_OUT (LOCK) pin (configured by LOCK_SELECT[3:0]) and used as an interrupt input to the microcontroller. The CAL_START bit must be set to 0 by the microcontroller after the calibration is done. There are separate calibration s for the two frequency registers. If the two frequencies, A and B, differ more than 1 MHz, or different VCO currents are used (VCO_CURRENT[3:0] in the CURRENT register) the calibration should be done separately. When using a 10.7 MHz external IF the LO is 10.7 MHz below/above the transmit frequency, hence separate calibration must be done. The CAL_DUAL bit in the CAL register controls dual or separate calibration. The single calibration algorithm using separate calibration for RX and TX frequency is illustrated in Figure 14. In Figure 15 the dual calibration algorithm is shown for two RX frequencies. It could also be used for two TX frequencies, or even for one RX and one TX frequency if the same VCO current is used. Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 22 of 48

Start single calibration Write FREQ_A, FREQ_B If DR>=38kBd then write TEST4: L2KIO=3Fh Write CAL: CAL_DUAL = 0 Frequency register A is used for RX mode, register B for TX Write MAIN: RXTX = 0; F_REG = 0 RX_PD = 0; TX_PD = 1; FS_PD = 0 CORE_PD = 0; BIAS_PD = 0; RESET_N=1 Write CURRENT: VCO_CURRENT = RX current Write CAL: CAL_START=1 RX frequency register A is calibrated first RX current is the VCO current to be used in RX mode Calibration is performed in RX mode, Result is stored in TEST0 and TEST2, RX register Wait for maximum 34 ms, or Read CAL and wait until CAL_COMPLETE=1 Calibration time depend on the reference frequency, see text. Write CAL: CAL_START=0 Write MAIN: RXTX = 1; F_REG = 1 RX_PD = 1; TX_PD = 0; FS_PD = 0 CORE_PD = 0; BIAS_PD = 0; RESET_N=1 TX frequency register B is calibrated second Write CURRENT: VCO_CURRENT = TX current Write PA_POW = 00h TX current is the VCO current to be used in TX mode PA is turned off to prevent spurious emission Write CAL: CAL_START=1 Calibration is performed in TX mode, Result is stored in TEST0 and TEST2, TX registers Wait for 28 ms, or Read CAL and wait until CAL_COMPLETE=1 Write CAL: CAL_START=0 End of calibration Figure 14. Single calibration algorithm for RX and TX Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 23 of 48

Start dual calibration Write FREQ_A, FREQ_B If DR>=38kBd then write TEST4: L2KIO=3Fh Write CAL: CAL_DUAL = 1 Frequency registers A and B are both used for RX mode Write MAIN: RXTX = 0; F_REG = 0 RX_PD = 0; TX_PD = 1; FS_PD = 0 CORE_PD = 0; BIAS_PD = 0; RESET_N=1 Write CURRENT: VCO_CURRENT = RX current Either frequency register A or B is selected RX current is the VCO current to be used in RX mode Write CAL: CAL_START=1 Dual calibration is performed. Result is stored in TEST0 and TEST2, for both frequency A and B registers Wait for maximum 34 ms, or Read CAL and wait until CAL_COMPLETE=1 Calibration time depend on the reference frequency, see text. Write CAL: CAL_START=0 End of calibration Figure 15. Dual calibration algorithm for RX mode Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 24 of 48

VCO and LNA current control The VCO current is programmable and should be set according to operating frequency RX/TX mode and output power. Recommended settings for the VCO_CURRENT bits in the CURRENT register are shown in the tables on page 39. The bias current for the LNA, and the LO and PA buffers are also programmable. Table 9 shows the current consumption and receiver sensitivity for different settings (2.4 kbaud Manchester encoded data). RF frequency [MHz] Current consumption [ma] Sensitivity [dbm] VCO_ CURRENT [3:0] CURRENT register LO_DRIVE [1:0] PA_DRIVE [1:0] FRONT_END register BUF_CUR LNA_CUR RENT RENT[1:0] 433 9.3-110 0100 01 00 0 10 433 7.4-109 0100 00 00 0 00 868 11.8-107 1000 11 00 1 10 868 9.6-105 1000 10 00 0 00 Note: Current consumption and sensitivity are typical figures at 2.4 kbaud Manchester encoded data, BER 10-3 Table 9. Receiver sensitivity as function of current consumption Power management offers great flexibility for power management in order to meet strict power consumption requirements in battery operated applications. Power Down mode is controlled through the MAIN register. There are separate bits to control the RX part, the TX part, the frequency synthesiser and the crystal oscillator (see page 37). This individual control can be used to optimise for lowest possible current consumption in a certain application. A typical power-on and initialising sequence for minimum power consumption is shown in Figure 16 and Figure 17. PALE should be tri-stated or set to a high level during power down mode in order to prevent a trickle current from flowing in the internal pull-up resistor. PA_POW should be set to 00h before power down mode to ensure lowest possible leakage current. Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 25 of 48

Power Off Power turned on Initialise and reset MAIN: RXTX = 0 F_REG = 0 RX_PD = 1 TX_PD = 1 FS_PD = 1 CORE_PD = 0 BIAS_PD = 1 RESET_N = 0 Reset and turning on the crystal oscillator core MAIN: RESET_N = 1 Wait 2 ms* *Time to wait depends on the crystal frequency and the load capacitance Program all registers except MAIN Calibrate VCO and PLL Frequency register A is used for RX mode, register B for TX Calibration is performed according to single calibration algorithm for both RX and TX mode MAIN: RX_PD = 1, TX_PD = 1, FS_PD = 1, CORE_PD = 1, BIAS_PD = 1 PA_POW = 00h Power Down Figure 16. Initializing sequence Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 26 of 48

Power Down Turn on crystal oscillator core MAIN: CORE_PD = 0 Wait 2 ms* *Time to wait depends on the crystal frequency and the load capacitance Turn on bias generator BIAS_PD = 0 Wait 200 µs RX RX or TX? TX Turn on RX: MAIN: RXTX = 0, F_REG = 0 RX_PD = 0, FS_PD = 0 CURRENT = RX current Wait 250 µs Turn on TX: PA_POW = 00h MAIN: RXTX = 1, F_REG = 1 TX_PD = 0, FS_PD = 0 CURRENT = TX current Wait 250 µs RX mode Turn off RX: MAIN: RX_PD = 1, FS_PD = 1, CORE_PD=1, BIAS_PD=1 PA_POW = Output power Wait 20 µs TX mode Power Down Turn off TX: MAIN: TX_PD = 1, FS_PD = 1, CORE_PD=1, BIAS_PD=1 PA_POW = 00h Power Down Figure 17. Sequence for activating RX or TX mode Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 27 of 48

Input / Output Matching A few passive external components combined with the internal T/R switch circuitry ensures match in both RX and TX mode. The matching network is shown in Figure 18. Component s for various C31 frequencies are given in Table 1. Component s for other frequencies can be found using the configuration software. RF_IN TO ANTENNA C42 RF_OUT C41 L41 L32 AVDD=3V Figure 18. Input/output matching network Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 28 of 48

Output power programming The RF output power is programmable and controlled by the PA_POW register. Table 10 shows the closest programmable for output powers in steps of 1 db. The typical current consumption is also shown. In power down mode the PA_POW should be set to 00h for minimum leakage current. Output power RF frequency 433 MHz RF frequency 868 MHz [dbm] PA_POW Current consumption, PA_POW Current consumption, [hex] typ. [ma] [hex] typ. [ma] -20 01 5.3 02 8.6-19 01 6.9 02 8.8-18 02 7.1 03 9.0-17 02 7.1 03 9.0-16 02 7.1 04 9.1-15 03 7.4 05 9.3-14 03 7.4 05 9.3-13 03 7.4 06 9.5-12 04 7.6 07 9.7-11 04 7.6 08 9.9-10 05 7.9 09 10.1-9 05 7.9 0B 10.4-8 06 8.2 0C 10.6-7 07 8.4 0D 10.8-6 08 8.7 0F 11.1-5 09 8.9 40 13.8-4 0A 9.6 50 14.5-3 0B 9.4 50 14.5-2 0C 9.7 60 15.1-1 0E 10.2 70 15.8 0 0F 10.4 80 16.8 1 40 11.8 90 17.2 2 50 12.8 B0 18.5 3 50 12.8 C0 19.2 4 60 13.8 F0 21.3 5 70 14.8 FF 25.4 6 80 15.8 7 90 16.8 8 C0 20.0 9 E0 22.1 10 FF 26.7 Table 10. Output power settings and typical current consumption Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 29 of 48

RSSI output has a built-in RSSI (Received Signal Strength Indicator) giving an analogue output signal at the RSSI/IF pin. The IF_RSSI bits in the FRONT_END register enable the RSSI. When the RSSI function is enabled, the output current of this pin is inversely proportional to the input signal level. The output should be terminated in a resistor to convert the current output into a voltage. A capacitor is used in order to low-pass filter the signal. calculated using the following equations: P = -51.3 V RSSI 49.2 [dbm] at 433 MHz P = -50.0 V RSSI 45.5 [dbm] at 868 MHz The external network for RSSI operation is shown in Figure 19. R281 = 27 kω, C281 = 1nF. A typical plot of RSSI voltage as function of input power is shown in Figure 20. The RSSI voltage range from 0 1.2 V when using a 27 kω terminating resistor, giving approximately 50 db/v. This RSSI voltage can be measured by an A/D converter. Note that a higher voltage means a lower input signal. The RSSI measures the power referred to the RF_IN pin. The input power can be RSSI/IF C281 TO ADC R281 Voltage 1.3 1.2 1.1 433Mhz 1 0.9 868Mhz 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0-105 -100-95 -90-85 -80-75 -70-65 -60-55 -50 dbm Figure 19. RSSI circuit Figure 20. RSSI voltage vs. input power Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 30 of 48

IF output has a built-in 10.7 MHz IF output buffer. This buffer could be applied in narrow-band applications with requirements on mirror image filtering. The system is then built with, a 10.7 MHz ceramic filter and an external 10.7 MHz demodulator. The external network for IF output operation is shown in Figure 21. R281 = 470 Ω, C281 = 3.3nF. The external network provides 330 Ω source impedance for the 10.7 MHz ceramic filter. RSSI/IF C281 R281 To 10.7MHz filter and demodulator Figure 21. IF output circuit Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 31 of 48

Crystal oscillator An external clock signal or the internal crystal oscillator can be used as main frequency reference. An external clock signal should be connected to XOSC_Q1, while XOSC_Q2 should be left open. The XOSC_BYPASS bit in the FRONT_END register should be set when an external clock signal is used. The crystal frequency should be in the range 3-4, 6-8 or 9-16 MHz. Because the crystal frequency is used as reference for the data rate (as well as other internal functions), the following frequencies are recommended: 3.6864, 7.3728, 11.0592 or 14.7456 MHz. These frequencies will give accurate data rates. The crystal frequency range is selected by XOSC_FREQ1:0 in the MODEM0 register. To operate in synchronous mode at data rates different from the standards at 1.2, 2.4, 4.8 kbaud and so on, the crystal frequency can be scaled. The data rate (DR) will change proportionally to the new crystal frequency (f). To calculate the new crystal frequency: f xtal _ new = f xtal DR DR new Using the internal crystal oscillator, the crystal must be connected between XOSC_Q1 and XOSC_Q2. The oscillator is designed for parallel mode operation of the crystal. In addition loading capacitors (C171 and C181) for the crystal are required. The loading capacitor s XOSC_Q1 depend on the total load capacitance, C L, specified for the crystal. The total load capacitance seen between the crystal terminals should equal C L for the crystal to oscillate at the specified frequency. 1 C = + 1 1 + C C L C parasitic 171 181 The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Typically the total parasitic capacitance is 8 pf. A trimming capacitor may be placed across C171 for initial tuning if necessary. The crystal oscillator circuit is shown in Figure 22. Typical component s for different s of C L are given in Table 11. The initial tolerance, temperature drift, ageing and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application. By specifying the total expected frequency accuracy in SmartRF Studio together with data rate and frequency separation, the software will calculate the total bandwidth and compare to the available IF bandwidth. Any contradictions will be reported by the software and a more accurate crystal will be recommended if required. XOSC_Q2 XTAL C181 C171 Figure 22. Crystal oscillator circuit Item C L= 12 pf C L= 16 pf C L= 22 pf C171 6.8 pf 18 pf 33 pf C181 6.8 pf 18 pf 33 pf Table 11. Crystal oscillator component s Chipcon AS SmartRF PRELIMINARY Datasheet (rev. 2.1) 2002-04-19 Page 32 of 48