Analog to digital and digital to analog converters A/D converter D/A converter ADC DAC ad da Number bases Decimal, base, numbers - 9 Binary, base, numbers and Oktal, base 8, numbers - 7 Hexadecimal, base 6, numbers 9 and A - F
The structure of a decimal number Integer number 346= 3 + 3 + 4 + 6 Number with decimals 5.857= 5 8 + -+ 5 - + 7-3 Conversion between bases Decimal to hexadecimal 346 6 46 6 = 46 = 9 6 6 9 6 = 9 6 = 6 9 = 9 6 ( 346 ) = ( 9A) 6 = A 6
Conversion between bases cont. Decimal to octal 346 = 93 8 8 93 = 36 5 8 8 36 = 4 4 8 8 4 = 4 8 8 4 4 5 ( 346 ) = ( 445) 8 Conversion between bases cont. Decimal to binary 346 73 73 = = 586 586 = 93 93 = 46 46 = 73 73 = 36 36 = 8 8 = 9 9 = 4 4 = = = ( 346 ) = ( ) 3
Conversion between bases cont. Hexadecimal to binary ( 3AD ) 6 = ( ) One hexadecimal digit = four binary bits Word length 8 bits = byte (char) 6 bits = word (short, short integer, some times integer) 3 bits = long word or double word (long, long integer, some times integer) 64 bits = long long word 4
Floating point numbers IEEE754 3 3 3 S Exponent, E Mantissa, M N = S E 7 ( ) (.M) < E < 55 Sign bit Smallest number 6,8 38 Largest number 7 3 38 ( ) 3.4 Integer values Fixed point Fractional numbers 5
Negative numbers Sign bit value Two complement ( ) value = value + value Two complement ( ) = ( ) invert all bits ( ) add one to LSB 6 + ( 38) ( 6) = ( 38) + ( 6) = ( ) ( ) = ( ) + ( ) = + = ( ) 6
General A/D- and D/A-quantities n bits gives n N= different values Resolution or N max = = = N n max n nipolar and bipolar converters n/ - Out - max (- -(n-) ) max In - n/ 7
Conversion error, SQNR nipolar SQNR = unipolar = max log = max n maximal level log maximal log error level = log max = max log = max N n + ( ) = ( n+ ) log( ) = 6. ( n+ ) 6 ( n+ ) SQNR Conversion error, SQNR bipolar = = log maximal Bipolar maximal amplitude max log = max n error level log = log max = n ( ) = n log( ) = 6. n 6 n max log = max N Number of bits 8 6 4 SQNR [db] 48 7 96 44 8
Logarithmic converter compander.9.8.7 A-law, A=87.56 A- and µ-law companding µ-law, µ=55.6.5.4.3.....3.4.5.6.7.8.9 Operational amplifiers 9
Comparator + in - out ref in < ref out negative in > ref out positive Comparator cont. in < in out negative in > in out positive
Inverting amplifier in out out in R R R R I I = = = Summing amplifier in, 3 in, 3 out 3 out in, in, 3 R R R R R R R I I I = = + = +
Non-inverting amplifier out R + R = R R = + R in Buffer out = in
Buffer cont. in source load out Buffer cont. in + out 3
Integrating amplifier out in = t R C D/A-converters Resistance ladder converter MX 4
Current summing D/A One bit = max out, LSB = max Current summing D/A Two bits = max out, LSB = 4 max = max out, bit = max 5
Current summing D/A Four bits R-R ladder D/A One bit I ref = R ref + R = R ref I f I ref = = R max max = I f R f = = 6
R-R ladder D/A Two bits R-R ladder D/A Four bits 7
D/A-converted signal Smoothing filter Amplitude.8.6.4. -. -.4 -.6 -.8 -..4.6.8 Time Amplitude Smoothed DAC signal.8.6.4. -. -.4 -.6 -.8 -..4.6.8 Time A/D converters Flash converter Decoding net 8
A/D converters Flash converter cont. Interval ref 4 ref ref 4 Bits from comparators Binary word ref 3 ref 4 3 ref ref 4 p-counting ADC 9
p-counting ADC cont. p-counting ADC cont. Limitations Large variation in conversion time The conversion time depends on the level of the input voltage npredictable conversion time
p-counting ADC cont ADC using succesive approximation
ADC using succesive approximation cont. max Voltage in Time Single-slope integrating ADC S C out ( ) ref = R C ref t = t R C - ref R - Integrator + + Analog input in Clock Comparator - Control logic Stop conversion Start/stop count Counter Digital output n bits
Single-slope integrating ADC cont. ref t R C Dual-slope integrating ADC 3
Dual-slope integrating ADC cont. Voltage Variable slope Fixed slope Phase in = t R C ref in RC ref RC Phase = Phase ref t R C Time Phase Phase Fixed interval t ref Variable interval t x Aliasing H Aliased signals True signals f s / f s f 4
Sampling cont. Sampling theorem: For faithful reproduction of the sampled signal the sampling frequency has to be more than twice the highest signal frequency Sampling cont. 5
Oversampling Sample & Hold 6
Sample & Hold cont..8.6.4 Sampled signal with hold circuits Amplitude. -. -.4 -.6 -.8 -..4.6.8 Time Sample & Hold cont..8.6.4 Sampled signal with track and hold circuit Amplitude. -. -.4 -.6 -.8 -..4.6.8 Time 7
Sigma-delta modulator Sigma-delta modulators and noise Noise shaping 8
ADC with multiplexed inputs Analog inputs ADC with multiplexed inputs cont. Maximal sampling frequency with single channel f s, max Maximal sampling frequency with N channels f s, max N 9
Angle decoders Incremental decoders Angle decoders cont. Absolute decoders 3
Angle decoders cont. Absolute decoders Decimal Bit Bit Bit 3 4 5 6 7 Angle decoders cont. Absolute decoders cont. Bit Bit Bit Decimal 3 Correct/False Correct False 6 False 4 Correct 3
Angle decoders cont. Absolute decoders cont. Gray coding Decimal Bit Bit Bit 3 4 5 6 7 Voltage to frequency converters 3
Converter specifications Voltage span Resolution Accuracy Conversion time (ADC) Settling time (DAC) Offset error Amplification (scale factor) error Linearity error Converter specifications cont. Offset error n - Out -n max (- -n ) max In 33
Converter specifications cont. Amplification (scale factor) error n - Out -n max (- -n ) max In Converter specifications cont. Linearity error n - Out -n max (- -n ) max In 34
Skew in parallel communication Bit Bit Bit Skew Bit 3 35