Space Vector Pulse Density Modulation Scheme For Multilevel Inverter With 18-sided Polygonal Voltage Space Vector

Similar documents
Harmonic Reduction in Induction Motor: Multilevel Inverter

INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET)

Decoupled Space Vector PWM for Dual inverter fed Open End winding Induction motor drive

A Novel Five-level Inverter topology Applied to Four Pole Induction Motor Drive with Single DC Link

A Novel Cascaded Multilevel Inverter Using A Single DC Source

Simulation of Speed Control of Induction Motor with DTC Scheme Patel Divyaben Lalitbhai 1 Prof. C. A. Patel 2 Mr. B. R. Nanecha 3

Elimination of Harmonics using Modified Space Vector Pulse Width Modulation Algorithm in an Eleven-level Cascaded H- bridge Inverter

A Fifteen Level Cascade H-Bridge Multilevel Inverter Fed Induction Motor Drive with Open End Stator Winding

Sampled Reference Frame Algorithm Based on Space Vector Pulse Width Modulation for Five Level Cascaded H-Bridge Inverter

COMPARISON STUDY OF THREE PHASE CASCADED H-BRIDGE MULTI LEVEL INVERTER BY USING DTC INDUCTION MOTOR DRIVES

Performance Evaluation of a Cascaded Multilevel Inverter with a Single DC Source using ISCPWM

Common Mode Voltage Reduction in a Three Level Neutral Point Clamped Inverter Using Modified SVPWM

Low Order Harmonic Reduction of Three Phase Multilevel Inverter

MATLAB/SIMULINK MODEL OF FIELD ORIENTED CONTROL OF PMSM DRIVE USING SPACE VECTORS

Simulation And Comparison Of Space Vector Pulse Width Modulation For Three Phase Voltage Source Inverter

Enhanced Performance of Multilevel Inverter Fed Induction Motor Drive

SPECIFIC HARMONIC ELIMINATION SCHEME FOR NINELEVEL CASCADED H- BRIDGE INVERTER FED THREE PHASE INDUCTION MOTOR DRIVE

INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY

Five Level Output Generation for Hybrid Neutral Point Clamped Inverter using Sampled Amplitude Space Vector PWM

PERFORMANCE EVALUATION OF THREE PHASE SCALAR CONTROLLED PWM RECTIFIER USING DIFFERENT CARRIER AND MODULATING SIGNAL

CHAPTER 3 CASCADED H-BRIDGE MULTILEVEL INVERTER

Analysis of Asymmetrical Cascaded 7 Level and 9 Level Multilevel Inverter Design for Asynchronous Motor

International Journal of Advance Engineering and Research Development

International Journal of Modern Engineering and Research Technology

Space Vecor Modulated Three Level Neutral Point Clamped Inverter Using A Single Z Source Network

Modified Multilevel Inverter Topology for Driving a Single Phase Induction Motor

Space vector pulse width modulation for 3-phase matrix converter fed induction drive

Performance Analysis of modulation techniques for Induction motor fed by Diode-Clamped NPC Inverter

Analysis of Voltage Source Inverters using Space Vector PWM for Induction Motor Drive

Hybrid 5-level inverter fed induction motor drive

Speed Control of Induction Motor using Multilevel Inverter

CHAPTER 6 UNIT VECTOR GENERATION FOR DETECTING VOLTAGE ANGLE

SIMULATION AND COMPARISON OF SPWM AND SVPWM CONTROL FOR TWO LEVEL UPQC

A Three Phase Seven Level Inverter for Grid Connected Photovoltaic System by Employing PID Controller

Study of Unsymmetrical Cascade H-bridge Multilevel Inverter Design for Induction Motor

International Journal of Advance Engineering and Research Development

Three Phase 15 Level Cascaded H-Bridges Multilevel Inverter for Motor Drives

Speed Control of Induction Motor using Space Vector Modulation

Control of Induction Motor Fed with Inverter Using Direct Torque Control - Space Vector Modulation Technique

A Comparative Approachof

Space Vector PWM Voltage Source Inverter Fed to Permanent Magnet Synchronous Motor

Symmetrical Multilevel Inverter with Reduced Number of switches With Level Doubling Network

Modeling and Simulation of Induction Motor Drive with Space Vector Control

CASCADED H-BRIDGE MULTILEVEL INVERTER FOR INDUCTION MOTOR DRIVES

Australian Journal of Basic and Applied Sciences. Simulation and Analysis of Closed loop Control of Multilevel Inverter fed AC Drives

Simulation of Five Phase Voltage Source Inverter with Different Excitation for Star Connected Load

Harmonic Minimization for Cascade Multilevel Inverter based on Genetic Algorithm

Fifteen Level Hybrid Cascaded Inverter

Space Vector PWM and Model Predictive Control for Voltage Source Inverter Control

A Novel Four Switch Three Phase Inverter Controlled by Different Modulation Techniques A Comparison

Design and Development of Multi Level Inverter

ADVANCED PWM SCHEMES FOR 3-PHASE CASCADED H-BRIDGE 5- LEVEL INVERTERS

MODELING AND SIMULATION OF A THREE PHASE MULTILEVEL INVERTER FOR HARMONIC REDUCTION BASED ON MODIFIED SPACE VECTOR PULSE WIDTH MODULATION (SVPWM)

Harmonic Analysis & Filter Design for a Novel Multilevel Inverter

CARRIER BASED PWM TECHNIQUE FOR HARMONIC REDUCTION IN CASCADED MULTILEVEL INVERTERS

Compensation for Multilevel Voltage Waveform Generated by Dual Inverter System

SVPWM Based Two Level VSI for Micro Grids

REDUCTION OF ZERO SEQUENCE VOLTAGE USING MULTILEVEL INVERTER FED OPEN-END WINDING INDUCTION MOTOR DRIVE

Induction Motor Drive using SPWM Fed Five Level NPC Inverter for Electric Vehicle Application

Cascaded H-Bridge Five Level Inverter for Harmonics Mitigation and Reactive Power Control

SVPWM for two Legged Three Phase Multilevel Inverters a Simplified Approach on 16 Bit Microcontroller Platform

Keywords Cascaded Multilevel Inverter, Insulated Gate Bipolar Transistor, Pulse Width Modulation, Total Harmonic Distortion.

Effective Algorithm for Reducing DC Link Neutral Point Voltage and Total Harmonic Distortion for Five Level Inverter

Analysis of Advanced Techniques to Eliminate Harmonics in AC Drives

Design and Simulation of Three Phase Shunt Active Power Filter Using SRF Theory

A Hybrid Cascaded Multilevel Inverter for Interfacing with Renewable Energy Resources

Mathematical Analysis of SVPWM for Inverter fed DTC of Induction motor Drive

Literature Survey: Multilevel Voltage Source Inverter With Optimized Convention Of Bidirectional Switches

II. WORKING PRINCIPLE The block diagram depicting the working principle of the proposed topology is as given below in Fig.2.

SVPWM Buck-Boost VSI

Hardware Implementation of SPWM Based Diode Clamped Multilevel Invertr

Three Phase 11-Level Single Switch Cascaded Multilevel Inverter

CHAPTER 3 SINGLE SOURCE MULTILEVEL INVERTER

A Modified Apod Pulse Width Modulation Technique of Multilevel Cascaded Inverter Design

A Single Dc Source Based Cascaded H-Bridge 5- Level Inverter P. Iraianbu 1, M. Sivakumar 2,

A Predictive Control Strategy for Power Factor Correction

Modular Grid Connected Photovoltaic System with New Multilevel Inverter

ISSN: International Journal of Science, Engineering and Technology Research (IJSETR) Volume 1, Issue 5, November 2012

THD Minimization of 3-Phase Voltage in Five Level Cascaded H- Bridge Inverter

Hybrid PWM switching scheme for a three level neutral point clamped inverter

A New Transistor Clamped 5-Level H-Bridge Multilevel Inverter with voltage Boosting Capacity

Resonant Controller to Minimize THD for PWM Inverter

CHAPTER 4 CONTROL ALGORITHM FOR PROPOSED H-BRIDGE MULTILEVEL INVERTER

Timing Diagram to Generate Triggering Pulses for Cascade Multilevel Inverters

South Asian Journal of Engineering and Technology Vol.2, No.16 (2016) 21 30

Lecture Note. DC-AC PWM Inverters. Prepared by Dr. Oday A Ahmed Website:

A New Three Phase Multilevel Inverter With Reduced Number Of Switching Power Devices With Common Mode Voltage Elimination

PWM Strategies for Multilevel Inverter and DC Link Capacitor Voltage Balancing For an Induction Motor Drive

INVESTIGATION OF HARMONIC DETECTION TECHNIQUES FOR SHUNT ACTIVE POWER FILTER

MATLAB Implementation of a Various Topologies of Multilevel Inverter with Improved THD

Nine-Level Cascaded H-Bridge Multilevel Inverter Divya Subramanian, Rebiya Rasheed

THD Minimization of a Cascaded Nine Level Inverter Using Sinusoidal PWM and Space Vector Modulation

Cascaded Connection of Single-Phase & Three-Phase Multilevel Bridge Type Inverter

CHAPTER 4 MODIFIED H- BRIDGE MULTILEVEL INVERTER USING MPD-SPWM TECHNIQUE

Design of DC AC Cascaded H-Bridge Multilevel Inverter for Hybrid Electric Vehicles Using SIMULINK/MATLAB

Simulation of Cascade H-Bridge Multilevel Inverter With Equal DC Voltage Source

PF and THD Measurement for Power Electronic Converter

AN IMPROVED MODULATION STRATEGY FOR A HYBRID MULTILEVEL INVERTER

PERFORMANCE EVALUATION OF MULTILEVEL INVERTER BASED ON TOTAL HARMONIC DISTORTION (THD)

Harmonic Analysis of Sine PWM and hysteresis current controller

Transcription:

Space Vector Pulse Density Modulation Scheme For Multilevel Inverter With 18-sided Polygonal Voltage Space Vector Anilett Benny 1, Dr.T. Ruban Deva Prakash 2 PG Student, Sree Narayana Gurukulam College of Engineering, Kadayiruppu, Kerala, India 1 Professor, Sree Narayana Gurukulam College of Engineering, Kadayiruppu, Kerala, India 2 Abstract: Space Vector Based Pulse Density Modulated scheme for multilevel inverter is proposed in this paper. A two level and three level inverters with three different DC input voltages are used to produce 18 stepped output sinusoidal voltage. First order sigma delta modulator is used to obtain Pulse Density Modulation. The vector space is divided into 18 segments for spatial quantization. Sixty degree co-ordinate system is used to avoid fractional arithmetic. The proposed scheme uses only switching vectors which lie on the vertices of 18 sided polygon. The scheme uses only sector identification for selecting the switching vectors without using lookup table and timer. The proposed scheme with 18 sided polygonal multilevel inverter results in elimination of 5 th, 7 th, 11 th and 13 th order harmonics when compared to two level inverter schemes. Simulation results of the proposed scheme are compared with that of two level inverter schemes. From the results, the total harmonic distortion (THD) of the output voltage of SVPDM based 2-level inverter is 31.13% and the 18-sided multilevel inverter with SVPDM is 1.11%. From the results, the validity of the SVPDM based 18-sided multilevel inverter has been confirmed. Zero voltage switching can be incorporated in future for achieving high efficiency. Keywords: Space vector pulse density modulation, multi-level inverter, two level inverter, harmonics, sigma delta modulator. I. INTRODUCTION Pulse density modulation (PDM) control method is applied in order to reduce the switching loss of the inverter side. In this method the density and the plus/minus of the constant width pulse is controlled, and then these pulse signals are used as switching pulses [5]. In general, delta-sigma conversion is used for analog-digital conversion. These PDM signals are used to turn on/off the inverter arm in PDM inverters. Delta-sigma conversion generates the inverse voltage pulses in order to cancel the quantization error. In order to resolve this problem, the PDM based SVM is proposed [6]. In PDM based SVM, the phase error between the voltage and current does not occur rapidly, because the SVM controller can select the switching pattern and hence the phase change on the voltage becomes smaller. Space vector based pulse density modulation (SVPDM) is proposed for two-level inverters. The total harmonic distortion in 2-level inverter is large. Multilevel inverters have become more superior to conventional two level voltage inverters [1][2]. Different topologies of multilevel inverters are explained in literature [3], [7], [1]. SVPWM is commonly used [8] for generating switching pulses where the switching losses are more. Hence we propose SVPDM for multilevel inverter. Pulse density modulation scheme consists of a first order delta sigma modulator and a space vector quantizer [4]. 12-sided polygonal voltage space vector concept for PWM is proposed in [9]. In this paper, the principle of vector quantization is applied for 18 sided polygonal voltage space vector. A two level inverter and a three level inverter feeding both ends of a load are used to produce the stepped output voltage. Three level inverter is made by cascading two 2 level inverters fed with asymmetrical voltages. The advantage of using multilevel inverters is the reduction of EMI and harmonics. Also the power circuit can be realised with low voltage devices and can be operated with low switching losses. The proposed 18 sided polygonal voltage space vector Copyright to IJIRSET www.ijirset.com 934

structure gives an increased modulation range with the absence of 5 th, 7 th, 11 th and 13 th harmonics from the output voltage [7]. So this scheme can be considered as available alternative for low and medium voltage high power drive applications. II. SPACE VECTOR PULSE DENSITY MODULATION SCHEME Fig. 1 represents proposed space vector pulse density scheme for multilevel inverter with 18 sided polygonal voltage space vector. The instantaneous values of three phase voltages are converted into reference voltage space vector Vref. The instantaneous values are resolved into sixty degree (m-n) coordinate system (Fig. 2). The m-axis is placed along A phase. The transformation equations are given below: V m = 2 3 (V a 1 2 V b 1 2 V c) V n = 2 3 (1 2 V a + 1 2 V b V c ) V = 2 3 ( 1 2 V a + 1 2 V b + 1 2 V c) Each forward path consists of a first order sigma delta modulator consisting of a difference node, discrete time integrator, a quantizer and a digital to analog converter. The space vector quantizer consists of two parts, m-n to three phase voltage converter and a space vector quantizer. The difference between reference space vector Vref and analog estimate of quantizer output vector Sa is integrated to obtain error vector Ve in delta sigma modulator. The error vector is quantized to obtain switching sectors S. The m-n frame components are converted back to three phase voltages. Fig. 1 Proposed vector quantized space vector pulse density modulator Copyright to IJIRSET www.ijirset.com 935

Fig. 2 abc to mn transformation In space vector quantizer the three phase components are again converted to αβ frame components (Fig.3) to produce the reference voltage vector and angle of sector selection using the transformation equations given below: V α = 2 3 (V a 1 2 V b 1 2 V c) V β = 2 3 ( 3 2 V b 3 2 V c) V ref = V α 2 + V β 2 θ = tan 1 V β V α The sector in which the voltage space vector is located is determined (as per table-1) for finding out the multilevel inverter switching states. TABLE-1 SECTOR SELECTION θ SECTOR VOLTAGE VECTOR -19 1 V1 2-39 2 V2 4-59 3 V3 6-79 4 V4 8-99 5 V5 1-119 6 V6 12-139 7 V7 14-159 8 V8 16-179 9 V9 18-199 1 V1 2-219 11 V11 22-239 12 V12 24-259 13 V13 26-279 14 V14 Copyright to IJIRSET www.ijirset.com 936

28-299 15 V15 3-319 16 V16 32-339 17 V17 34-359 18 V18 The output voltage is fed back and converted to m-n frame components. The m and n components are added to delta sigma loop as shown in the figure. Fig. 3 abc to αβ transformation III. MULTILEVEL INVERTER WITH 18 SIDED POLYGONAL VOLTAGE SPACE VECTOR Multilevel inverter to generate 18-sided polygonal voltage space vectors is shown in Fig.4. It consists of a 2-level inverter on one side and a 3-level inverter on the other side of load. The 3-level inverter is made by cascading two conventional 2-level inverters. Asymmetrical DC link voltages are used for the inverters. For the proposed inverter we can achieve 6 different voltage levels in each winding. Therefore a total of 6 3 =216 switching states can be generated. Out of these switching states, vectors which lie on the vertices of 18 sided polygon are selected to generate 18-sided voltage space vector. Each pole A, B or C in INV1 can be independently connected either to.742v dc or to the zero voltage. The poles A 1, B 1 or C 1 of INV2 can be connected to any of three levels,.258v dc or.395v dc independently. This can be used to generate 18 polygonal voltage space vectors. The top and bottom switches in each leg of the inverter compliments to each other. The state of upper switch determines the state of lower switch. Copyright to IJIRSET www.ijirset.com 937

Fig. 4 Power circuit of inverter with 18 sided polygonal voltage space vector The 18 voltage space vectors are shown in Fig.5. The angle between two adjacent voltage vectors is 2. Resultant sum of vector OA and AB gives vector 1. In first segment INV1produces vector OA by connecting the pole A to.742vdc. Vector AB has a magnitude of.258vdc and is generated as shown in the Fig. 6. Pole voltages A 1, B 1, and C 1 of INV2 are subtracted from the pole voltages A, B, C of INV1. When B 1 is connected to.258vdc it is along the negative B-axis and when C 1 is connected to.258vdc it is along the negative C-axis. Their resultant is AB with magnitude.258vdc along A-axis. The vectors AB and OA gives vector 1 of magnitude Vdc. Fig. 5 18-polygonal voltage vectors In the second sector, pole A of INV1 is connected to.742v dc, poles B and C at zero level. Hence vector OA is produced. Pole voltages A 1 and B 1 are at zero voltage levels and C 1 at.395v dc. Vector sum of the above vectors yields vector 2 in Fig. 7. Vector-3 is generated as follows. In INV1 pole voltages A and B are maintained at.742v dc, while C is at Vdc. Hence a vector is produced along the negative C-axis with a magnitude equal to.742v dc. In INV2 pole A 1 is at zero level Copyright to IJIRSET www.ijirset.com 938

while B 1 and C 1 are at levels.395v dc. This produces a vector with magnitude of.395v dc along the positive A axis. Together the vector sum produces vector 3 in Fig.5. TABLE -2 18-SIDED POLYGONAL VECTORS Vector No. Pole A Pole B Pole C Pole A 1 Pole B 1 Pole C 1 1.742Vdc.258Vdc.258Vdc 2.742Vdc.395Vdc 3.742Vdc.742Vdc.395Vdc.395Vdc 4.742Vdc.742Vdc.258Vdc 5.742Vdc.742Vdc.395Vdc.395Vdc 6.742Vdc.395Vdc 7.742Vdc.258Vdc.258Vdc 8.742Vdc.395Vdc 9.742Vdc.742Vdc.395Vdc.395Vdc 1.742Vdc.742Vdc.258Vdc 11.742Vdc.742Vdc.395Vdc.395Vdc 12.742Vdc.395Vdc 13.742Vdc.258Vdc.258Vdc 14.742Vdc.395Vdc 15.742Vdc.742Vdc.395Vdc.395Vdc 16.742Vdc.742Vdc.258Vdc 17.742Vdc.742Vdc.395Vdc.395Vdc 18.742Vdc.395Vdc Fig. 6 Generation of voltage vector AB from INV2 Fig. 7 Generation of vector OC (OA+AC) Copyright to IJIRSET www.ijirset.com 939

IV. SECTOR IDENTIFICATION The angle calculation in space vector quantizer is used to identify the sector. Depending upon the value of angle calculated in αβ frame, one of the 18 sectors is selected and switching vector corresponding to that specific sector is applied to multilevel inverter. TABLE-3 VOLTAGE LEVELS FOR 18 VECTORS VECTOR A B C A 1 B 1 C 1 1 1 1 1 2 1 2 3 1 1 2 2 4 1 1 1 5 1 1 2 2 6 1 2 7 1 1 1 8 1 2 9 1 1 2 2 1 1 1 1 11 1 1 2 2 12 1 2 13 1 1 1 14 1 2 15 1 1 2 2 16 1 1 1 17 1 1 2 2 18 1 2 Voltage level in A, B, C: = & 1=.742V dc ; Voltage level in A 1, B 1, C 1 : =, 1=.258V dc & 2=.395V dc SECTOR AND VOLTAGE VECTOR TABLE-4 GATE PULSES FOR INVERTER SWITCHES 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 17 18 SWITCH 1 1 1 1 1 1 1 2 1 1 1 3 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 6 1 1 1 7 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 12 1 1 1 1 1 1 1 1 1 Copyright to IJIRSET www.ijirset.com 94

13 1 1 1 1 1 1 1 1 1 14 1 1 1 1 1 1 1 1 1 15 1 1 1 1 1 1 1 1 1 16 1 1 1 1 1 1 1 1 1 17 1 1 1 1 1 1 1 1 1 18 1 1 1 1 1 1 1 1 1 Gate pulses for each inverter switches are generated individually by calculating the voltage levels for each vector from table-3. Hence sector identification is performed. The switching pulses for inverter switches are shown in table-4. V. SIMULATION RESULTS The simulink model of the proposed SVPDM scheme for 18-sided multilevel inverter is shown in Fig.8. The inverter sub system is also shown in the figure. The simulink model of SVPDM for two-level inverter is shown in Fig.9. (a) Copyright to IJIRSET www.ijirset.com 941

(b) Fig. 8 Simulink model (a) Main model (b)18-sided multilevel inverter subsystem The phase voltage of 18-sided voltage space vector and its FFT analysis are shown in Fig. 1 and Fig. 11. The total harmonic distortion is found to be 1.11%. The phase voltage of two-level inverter with hexagonal quantizer and its FFT analysis are shown in Fig. 12 and Fig. 13. The total harmonic distortion is found to be 31.13% From simulation results it is found that the phase voltage for multilevel inverter with 18 sided voltage space vector produces 18 stepped output waveform. For a two level inverter with hexagonal quantizer, the phase voltage is 6- stepped waveform. When harmonic analysis is performed, the proposed scheme with multilevel inverter is found to eliminate 5 th, 7 th, 11 th and 13 th order harmonics. The Total Harmonic Distortion (THD) factor for the proposed scheme is very less when compared with the two-level inverter with hexagonal quantizer. Fig. 9 Simulink model of SVPDM for 2-level inverter Copyright to IJIRSET www.ijirset.com 942

Voltage(v) Voltage(v) ISSN: 2319-8753 1 5-5 -1 1 5-5 -1 1 5-5 -1.2.4.6.8.1.12.14.16.18.2 Time(s) Fig. 1 Phase voltage of 18-sided voltage space vector for modulation index m=1 Fig. 11 FFT analysis of voltage waveform of 18-sided voltage space vector 2-2 2-2 2-2.2.4.6.8.1.12.14.16.18.2 Time(s) Fig.12 Phase voltage across load Copyright to IJIRSET www.ijirset.com 943

Fig. 13 FFT analysis of voltage waveform V. CONCLUSION An 18-sided multilevel inverter control scheme using space vector pulse density modulation is proposed. Sigma delta modulation and vector quantization principles are used in this scheme. The vector space is divided into 18 segments for spatial quantization. Sixty degree co-ordinate system is used to avoid fractional arithmetic. The proposed scheme uses only switching vectors which lie on the vertices of 18 sided polygon. The scheme uses only sector identification for selecting the switching vectors without using lookup table and timer. Simulation studies are performed for SVPDM based 2-level and multilevel inverter with 18-sided voltage space vectors. Pulse density modulation scheme for multilevel inverter with 18 sided voltage space vector yields low switching losses and very less harmonic content as compared to pulse width modulation techniques in multilevel inverters. The proposed scheme can be implemented for multilevel inverter with 12 sided voltage space vectors. Zero voltage switching can be incorporated in future for achieving high efficiency. This scheme is simple and timing calculations for voltage vectors are eliminated. REFERENCES [1] J-S. Lai and F. Z Peng, Multi-level converters-a new breed of power converters, IEE Transaction on Industry Applications, Vol. 32, No.3,, pp: 59-517, May-June 1996. [2] K. Corzine, and Y. Familiant, A new cascad ed multilevel H Bridge drive, IEEE Transactions on power electronics. Vol.17, NO.1, pp. 125-131, January 22. [3] Sanjay Lakshminarayanan, R.S. Kanchan, P.N. Tekwani and K Gopakumar:, Multilevel inverter with 12-sided polygonal space vector locations for induction motor drive, IEE Proc.-Electr. Power Appln. Vol. 153, No.3, pp. 411-419, May 26. [4] Biji Jacob and M.R. Baiju, Spread Spectrum Scheme for Three-Level Inverters based on Space Vector Sigma-Delta Modulation, IEEE International Symposium on Industrial Electronics, ISIE 21, pp.1491-1496, July 21. [5] Biji Jacob and M.R. Baiju, Spread spectrum modulation scheme for two-level inverter using vector quantised space vector-based pulse density modulation, IET Electric Power Applications, 211 [6] Nieznanski J, Analytical Establishment of the Minimum Distortion Pulse Density Modulation, Electrical Engineering 8, pp 251-258, 1997 [7] Sanjay Lakshminarayanan, Gopal Mondal, K.Gopakumar, Multilevel Inverter with 18-sided Polygonal Voltage Space Vector for an Open-end Winding Induction Motor Drive,The International Conference on Computer as a Tool, 27. [8] Sanmin Wei, Bin Wu, Fahai Li and Congwei Liu, A General Space Vector PWM Control Algorithm for Multilevel Inverters, Proc. Applied Power Electronics Conference and Exposition, pp.562-568, 23 [9] Nagath Abdul Azeez, Anubrata Dey, K.Mathew, Jaison Mathew, K.Gopakumar, A Medium Voltage Inverter-Fed Induction Motor Drive Using Multilevel 12 Sided Polygonal Vectors With Nearly Constant Switching Frequency Current Hysteresis Controller, IEEE Transactions on Industrial Electronics, Vol. 61, No.4, 214. [1] P.P Rajeevan, K. Sivakumar, K. Gopakumar, Chintan Patel & Haritham Abu-Rub, A Nine Level Inverter Topology For Medium Voltage Induction Motor Drive With Open End Stator Winding, IEEE Transactions on Industrial Electronics, Vol. 6, No.9, 213. Copyright to IJIRSET www.ijirset.com 944