Multple Error Correcton Usng Reduced Precson Redundancy Technque Chthra V 1, Nthka Bhas 2, Janeera D A 3 1,2,3 ECE Department, Dhanalakshm Srnvasan College of Engneerng,Combatore, Tamlnadu, Inda Abstract The uses of FFTs are unavodable n communcaton systems. As most of the nformaton may be analog n ths world and as transmsson of nformaton n dgtal form s more acceptable and effcent, FFTs plays an mportant role n present communcaton scenaro. For a relable communcaton the nformaton that we transmt should be reached at the destnaton as such. But due to many factors the nformaton that we transmts get altered. One of the man problems n communcaton system s soft error. Even though soft error doesn t make any physcal damage to the communcaton system t s dangerous. It has the ablty to alter the values stored n the system. It may alter the transmtted message. A lot of technques are avalable to detect the soft error and correct t. Those nclude TMR, ECC, party SOS, and party-sos-ecc. All these assume that there can only be a sngle error n the crcut. The proposed system known as reduced precson redundancy consders Instead of usng two full precson FFTs t uses two half precson FFTs as redundant FFTs. It lmts the error, reduces area and power consumpton. Index Terms Reduced Precson Redundancy, Fast Fourer transforms (FFTs), Soft errors 1.Introducton Communcaton system s becomng more and more complex as the technology advances [17]. It s subjected to many errors. It s the man challenge an electronc system faces. Because of technology scalng and aggressve voltage scalng, the rate of these faults occurrng n a crcut s ncreasng exponentally. Scalng means the transstor used are operatng at low voltage and t has hgh tendency to affect error [10]. These faults wll reveal themselves as temporary logc upsets, such as sngle-event upsets (SEUs) [4]. It can affect the transmtted sgnals and stored values whch lead to ncorrect or undesred outcomes n crcut and systems. A lot of researches are done academcally and ndustrally to understand the presence of faults and the rate of ncrease n fault. Faults n electronc systems are dvded n two types: permanent and transent. Irreversble physcal defects n the crcut are known as permanent faults. The next type s soft error whch s also known as transent error. It appears durng the operaton of a crcut. It won t create any physcal defect n the crcut. The man reasons for soft errors are crosstalk, any permanent logcal error, power supply nose and neutron or alpha radatons durng operatonal lfetme. Number of technques can be used to protect a crcut from errors such as modfcatons n the manufacturng process of the crcuts to reduce the number of errors by addng redundancy at the logc or system level [9]. Redundancy wll ensure that errors do not affect the system functonalty [5]. Other technques ncludes redundancy, party check, checksums, hammng codes, ECC, party-sos, party-sos-ecc etc. A smple ECC technque takes a block of k bts and produces a block of n bts by addng n k party check bts. XOR combnatons of the k data bts are used as the party check bts. It s possble to detect and correct errors by properly desgnng those combnatons. In the case of party-sos and party-sos-ecc, SOS checks are used to detect and locate the errors and a smple party FFT s used for correcton. For the detecton and correcton of the errors, we can use an SOS check per FFT or alternatvely usng a set of SOS checks that form an ECC. Another technque used s trple modular redundancy whch adds redundancy to the crcut. Both these are algorthm based fault tolerant technque [1]. TMR has the ablty to trplcates the desgn and adds votng logc to correct errors. It s commonly used. TMR s very effectve at protectng FPGA crcuts from soft errors. But t s costly n terms of the crcut area, power, and crcut tmng. FFT s protecton scheme s studed and dfferent technques are mplemented [15]. The latest technque used to reduce soft errors n FFTs s party-sos and party-sos-ecc technque. These technques are formed by combnng an exstng technque known as ECC approach wth the tradtonal SOS check. To detect and locate the errors SOS checks are used and a smple party FFT s used for correcton. Error detecton can be done usng an SOS check per FFT or alternatvely usng a set of SOS checks that form an ECC. So n order to reduce error the expense of hardware a less expensve hardware mtgaton strategy for arthmetc crcuts s a technque called reduced-precson redundancy (RPR) [3]. By provdng redundant, lower precson arthmetc 210
crcuts and comparng ther results RPR can be used. It protects aganst large magntude errors n arthmetc crcuts. Its area savngs make t an attractve alternatve for protectng FPGA sgnal processng crcuts aganst SEUs, transent and soft data errors. All these are sngle error detecton and correcton. In the case of parallel FFT for multple error detecton and correcton Reduced Precson Redundancy (RPR) technque can be used. RPR s a redundancy technque smlar to TMR. It requres less hardware overhead by usng reduced-precson (RP) arthmetc n two of ts three replcas. RP arthmetc can be a good estmate of computatons that use hgher precson. TMR has the ablty to protects the entre crcut and provdes an error-free output where as RPR smply lmts the error at the output of a module. The advantage of RPR over TMR s ts ablty to suffcently lmt the magntude of the SEU-nduced nose at a lower hardware cost. RPR has been used to protect arthmetc operatons. It wll reduce overheads and also reduces the area and power consumpton of error correcton module n a crcut. RPR s a new technque. for each crcut protected by RPR there are a number of mportant desgn decsons that must be made. Precson of RP module and determnng the threshold for detectng lowmagntude errors are mportant. Whenever a path wth delay greater than the sample perod T samp s excted voltage over scalng ntroduces nput-dependent soft errors. Reduced precson module(rpr) s formed by truncatng the LSB of the nput bt. Soft errors appear frst n the most sgnfcant bts (MSBs) snce the arthmetc unts employed n DSP systems are based on least sgnfcant bt (LSB) frst computaton. It results n errors of large magntude. These errors degrade the performance. But these errors are desrable because they are easy to detect. In short a small fracton of nput combnatons excte longer paths. Ths fracton depends on the delay dstrbuton of a system, whch depends on the archtecture. In ths way the errors n the FFTs can be reduced wth fewer overheads and less area and power consumpton. It s common to fnd several flters or FFTs operatng n parallel as sgnal-processng crcuts become more complex. Ths occurs manly n flter banks or n multple-nput multple-output (MIMO) communcaton systems [2]. MIMO orthogonal frequency dvson modulaton (MIMO-OFDM) systems use parallel IFFTs/FFTs for modulaton/demodulaton. On long-term evoluton moble systems and on WMax [8] MIMO-OFDM s mplemented [12]. It s possble to take advantage of the parallel property of the flters or FFTS to mplement ABFT technques [6]. It can mplement ABFT technques for the entre group of parallel modules nstead of for each one ndependently. Intally ths s studed for dgtal flters. Reduced Precson redundancy (RPR) can be used for parallel FFTs wth fewer overheads. In ths bref, the protecton of parallel FFTs s studed. The man contrbutons n ths bref are: (1) The proposed system for the reducton of multple errors n parallel FFTs. (2) Comparson wth the exstng technque for understandng the reducton n area. (3) Comparson wth the exstng technque to understand the reducton n power consumpton. 2. Exstng System Ths work starts wth the protecton scheme based on the use of party-sos for dgtal flters. In the frst technque, orgnal module consst of 4 FFTs. Input s gven to each FFTs separately as x1,x, x3, x4. Here the dea s that each flter can be the equvalent of a bt n an ECC and party check bts can be computed usng addton. Each FFT consst of a SOS check n parallel to detect the error n the FFT. The output of the Parseval check s represented as P 1, P 2, P 3, and P4. If there s any error n the FFT then the P wll set to 1. Fg 1. Party-SOS The output of the FFT and the P outputs are gven to error detecton and correcton block. If there s any error n the FFT output then the addtonal FFT whch s gven parallel to the FFT module wll correct the error. Ths Parseval check can only detect the errors n the FFT. It can t correct t by ts own. For that an addtonal FFT s used. We can correct the error usng ts output. The SOS check can be combned wth the ECC approach to reduce the protecton overhead n frst technque for parallel FFTs. Snce the SOS check can only detect errors, the ECC part should be able to mplement the correcton. Ths s done usng the equvalent of a smple party bt for all the FFTs. The SOS check s used on each FFT to detect errors. When an error s detected then the output of the party FFT can be used to correct the 211
error. Instead of usng an SOS check per FFT we can use an ECC for the SOS checks Next technque used s party-sos-ecc. In ths technque nstead of usng parallel SOS for each orgnal module 3 SOS block s used separately whch s drven by hammng code output. If there s any error n the output then the output of the Parseval check block wll be set. the RP outputs by less than Th, then t s consdered as the error free output and the fnal output wll be FP output. The arthmetc crcuts protected by RPR may be of any sze. The crcut used may be of basc arthmetc operaton such as an adder or a more complex combnaton of operators and logcs such as an nfnte mpulse response flters, fnte mpulse response (FIR) flter etc. Ths paper refers to the combnaton of FP module and RP module. There are two parameters to be consdered before mplementng RPR on a module. They are the bt wdth of the reduced precson module (Br) and the decson threshold (Th). The two values are lnked and together greatly affect the cost and performance of RPR. Fg 2. Party SOS ECC All these are sngle error detecton and correcton method. Even though these are algorthm based error correcton technque t requre more area for mplementaton as t consst of many squarng and summng blocks. So n order to reduce the area and power consumpton new technque s ntroduced. It s an algorthmc based method. III. PROPOSED SYSTEM Ths project s detectng multple errors and corrects t wth less over heads. It s better than the tradtonal method known as trple modular redundancy. A less expensve hardware mtgaton strategy for arthmetc crcuts called reduced-precson redundancy (RPR) s the proposed project. RPR s desgned to protect aganst large magntude errors. It s used manly n arthmetc crcuts wth the help of redundant, lower precson arthmetc crcuts and comparng ther results. Usng of Reduced Precson Redundancy may ntroduce low precson errors but stll ts area reducton make t an attractve alternatve for protectng FFTs, transent and soft data errors. There are some condtons to be satsfed whle desgnng a RPR module. These choces nclude the reduced precson and threshold. RPR s mplemented by creatng two dentcal reduced-precson (RP) module of the orgnal full precson FFTs. The outputs of the two RP modules are used to determne f there s any error n the FP module than a preset threshold, Th, the FP module s assumed to be n error. When the FP module s found to be n error, then t wll dscard the FP output and use RP output wth 000 s appended at the LSB part. If the FP output dffers from Fg 3. Block dagram of RPR technque Fg 3 shows the dagrammatc descrpton of ths project. It s used to detect and correct errors n the parallel FFTs. Input gven to ths block consst of 4 nputs wth each nput sx bt long. Each block s havng the same functon. Only the nput wll be dfferent. TRUNCATE TRUNCATE FULL PRECISION MODULE HALF PRECISION MODULE HALF PRECISION MODULE Fg 4. A sngle RPR module APPEND 000 TO LSB APPEND 000 TO LSB Fg 4 shows a sngle RPR module. Same nput s gven to all these three secton. Frst part s known as full precson module because t computes the FFT output as such.e. the nput of the FFT module s same as the nput that we gve at the startng secton. Second and thrd part s known as reduced precson module because C O M P A R I S O N O 212
t uses the truncated nput as the nput to the FFT. Both full precson module and reduced precson module use four pont FFT. Snce ths project s manly ntended to fnd out the error and correct t we are not gvng much mportance to FFT desgn. We are consderng a smple radx 4 DIF FFT. RPR module conssts of three parallel paths. One conssts of full precson module. Other two consst of half precson module. Frst nput s gven. Input s four ponts..e. there wll be 4 nputs and each nput wll be sx bt long. In the frst part these four nputs are gven as such to full precson module. Full precson module wll gve a four pont DIF FFT output whch s sx bt long. In the second and thrd part also same sx bt nput s gven. Then t s gven to truncaton block. Truncaton block wll truncate the sx bt nput to three bt nput. Truncaton s done by removng 3 bts from the LSB part. So the nput to half precson module s 3bt nputs and output wll be 3 bt output whch s four pont DIF FFT output. Then output of full precson module s gven to the comparson block drectly. But n the case of half precson module the output of the FFT s gven to another block before gvng to comparson. Here n ths block three bts 000 s appended at the LSB part of the FFT output to make the output as sx bt output. All these sx bt outputs are gven to comparson block. In the comparson block comparson of each output s done. There wll be four outputs from each block. If the output of the full precson s less than a partcular threshold value, then that output s taken as the fnal output. If the output of the full precson module s greater than the threshold and f the output of both the half precson modules are equal then that value s taken as the fnal output. Threshold value s set by dong a lot of computaton. We are not comparng the outputs of all the modules drectly. Instead we are comparng t wth the help of a threshold value. It s manly because truncated output s used n two half precson modules. Thus the output wll be wth less error. The full and half precson module we use s four pont DIF FFT. Snce ths project s manly for error detecton and correcton the FFT desgn s not havng much mportance. So we are usng a smple FFT. The FFT used here s radx 4 DIF FFT. TMR and RPR are smlar n representaton. But RPR has two FFTs n effect because t uses two less précsed FFTs as redundant FFTs whch s equvalent to one full precson module. Ths approach s used to lmt the errors n parallel FFT. The development of the nformaton transmsson technologes n the computer networks and n the telecommuncaton systems s nseparably connected wth the problem of ntegrty and of ensurng hgh effectveness of error detecton and correcton of errors whch occur durng data transmsson. The dynamc ncrease n the speed of nformaton transmsson n the buses of computer systems and the channels of computer networks brngs about strngent requrements for the performance of the hardware mplementaton of the error detecton and correcton algorthm. Multple error correcton s made possble wth the help of ths approach. The man ssue wth those soft errors mtgaton technques s that they requre a large overhead n terms of crcut mplementaton. Ths overhead s excessve for many applcatons. for TMR, the overhead s >200%. Ths s because the unprotected module s replcated three tmes. But ths approach requres fewer overheads as t s usng truncated FFTs as redundant module. Another man problem of all fault tolerant system s ts excessve power consumpton. Many error correcton systems consst of squarng and summng crcuts whch consumes a lot of power. Ths approach use less power for the detecton and correcton as t s not havng much complex computatonal elements. All the exstng systems only provde sngle error detecton and correcton. It s assumed that there can only be a sngle error on the system at any gven pont n tme. Ths s a common assumpton when consderng the protecton aganst radaton-nduced soft errors. But ths approach provdes multple error detecton and correcton wth less area, overheads and power. IV. EVALUATION AND RESULT The proposed system s smulated n ModelSm SE 6.3f. A model of the communcaton channel s formed. In communcaton channels the bandwdth wll be hgh. So the FFTs wll have large nputs. Ths project s used for error detecton and correcton. So desgnng of FFT s not relevant, n order to evaluate the error correcton capablty of ths technque we are takng a smple FFT. The FFT used here s 4 pont radx FFT. Input s gven as bnary number. Sx bt nput s gven. Intally some vales are gven as nput for smulaton. After runnng the smulaton f we want to check wth other nput we can force the requred nput. Before runnng the program clock s preset to 1. ModelSm s opened and new project s created and the program s typed n the edtor. After completng the program comple the program and then start smulaton. The program for runnng s selected and then run the program. Add waves to understand the output. Frst program wthout error s smulated. After that program wth an error n FFT s smulated and ts output and ts waveform are observed. From the two cases t s clear that RPR method s best suted for error correcton. 213
Fg 7 area detal of RPR technque Fg 5. RPR output wthout error Fgure 5 shows the output of a four pont FFT wthout error. The nputs gven are 6 bt long. Each FFT s gven 4 nputs. For easy computaton all the FFT are gven same nput. It s possble to gve dfferent output for all these 4 FFTs. FFT used here s 4 pont FFT.e. radx 4 FFT. The nput gven s n the normal order. But the output s n bt reversal order. Ths s because the FFT use DIF algorthm. Twddle factor W 4 0 =1 and twddle factor W 4 1 =-I s used n ths FFT. The output obtaned wll be n bt reversal form. The output represented here s n bnary format. It s possble to represent ths n hexadecmal, decmal or any other form. Fgure shows the nput, truncated nputs and outputs of dfferent FFTs wthout error. Fg 6. RPR output wth error njected Now n order fnd out the effcency of FFT fault s njected n the second bt of frst output. Ths shows the output wth error corrected. From ths t s clear that usng less overhead error correcton technque t s possble to lmt the error more effcently. Fg 7 shows the area related detals of the RPR technque. Total number of 4 nput LUTs used by the RPR technques are 130. Number of occuped slces are 68. Total equvalent gate count for desgnng a RPR technque s 2124.. Fg 8. Area detals of party-sos-ecc technque Fg 8 shows the area related detals of the exstng technque called Party-SOS-ECC. It uses 1611 four nput LUTs. Number of occuped slces s about 946. Total number of gate count s16575. Table 1: Performance Evaluaton of Party SOS-ECC and RPR. Party-SOS- RPR ECC Number of occuped 946 68 slces Total number of 4 nput LUTs 1815 130 Total equvalent gate 16575 2124 count for desgn Total power 100.66 83.77 From the above table t s clear that RPR technque uses less area for the mplementaton of error detecton and correcton block when compared to the prevous technque. And the power consumpton s also less. V. CONCLUSION Electroncs system s subjected to dfferent 214
errors. In VLSI due to technology scalng and voltage scalng the faults occurrng n a crcut also ncreased exponentally. These faults may create temporary logc upsets and can affect the sgnal transfers and stored values leadng to ncorrect or undesred outcomes n crcut and systems. A type of error called soft errors nvolves changes to data but wont changes the physcal crcuts. In many systems t s mpossble to determne the correct data or even to dscover that an error s present at all. Ths project s used to detect and correct multple errors n FFT. The drawbacks of exstng technques are overheads, ncreased area and cost and sngle error detecton and correcton technque. Proposed system use Reduced Precson Redundancy (RPR) technque for the protecton of FFT. In RPR along wth the orgnal module 2 less precson modules are used. The outputs of the two RP modules are used to determne f there s a fault n the full-precson (FP) module. It corrects multple errors wth fewer overheads and wth less area and cost. It s clear from ths output error detecton and correcton usng RPR technque s more effcent when compared to other technques. REFERENCES [1] A. L. N. Reddy and P. Banerjee, Algorthmbased fault detecton for sgnal processng applcatons, IEEE Trans. Comput., vol. 39, no. 10 [2] A. Sblle, C. Oestges, and A. Zanella, MIMO: From Theory to Implementaton. San Francsco, CA, USA: Academc, 2010. [3] B. Shm and N. R. Shanbhag, Energy-effcent soft error-tolerant dgtal sgnal processng, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 336 348, Apr. 2006. [4] Byonghyo Shm, Srnvasa R. Srdhara, and Naresh R. Shanbhag,, Relable Low-Power Dgtal Sgnal Processng va reduced Precson Redundancy [5] E. P. Km and N. R. Shanbhag, Soft N-modular redundancy, IEEE Trans. Comput., vol. 61, no. 3, pp. 323 336, Mar. 2012. [6] G. L. Stüber, J. R. Barry, S. W. McLaughln, Y. L, M. A. Ingram, and T. G. Pratt, Broadband MIMO-OFDM wreless communcatons, Proc. IEEE, vol. 92, no. 2, pp. 271 294, Feb. 2004. [7] J. Y. Jou and J. A. Abraham, Fault-tolerant FFT networks, IEEE Trans. Comput., vol. 37, no. 5, pp. 548 561, May 1988. [8] M. Ergen, Moble Broadband Includng WMAX and LTE. New York, NY, USA: Sprnger-Verlag, 2009. [9] M.Ncolads, Desgn for soft error mtgaton, IEEE Trans. Devce Mater. Rel., vol. 5, no. 3, pp. 405 418, Sep. 2005. [10] N. Kanekawa, E. H. Ibe, T. Suga, and Y. Uematsu, Dependablty n Electronc Systems: Mtgaton of Hardware Falures, Soft Errors, and Electro-Magnetc Dsturbances. New York, NY, USA: Sprnger-Verlag, 2010. [11] S. Sesa, I. Toufk, and M. Baker, LTE The UMTS Long Term Evo-luton: From Theory to Practce, 2nd ed. New York, NY, USA: Wley, Jul. 2011. [12] T. Htana and A. K. Deb, Brdgng concurrent and non-concurrent error detecton n FIR flters, n Proc. Norchp Conf., Nov. 2004 [13] Wang and N. K. Jha, Algorthm-based fault tolerance for FFT networks, IEEE Trans. Comput., vol. 43, no. 7, pp. 849 854, Jul. 1994. [14] Z. Gao et al., Fault tolerant parallel flters based on error correcton codes, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 2, pp. 384 387, Feb. 2015. [15] Zhen Gao, Pedro Revrego, Zhan Xu, Xn Su, Mng Zhao, Jng Wang, and Juan Antono Maestro: Fault Tolerant Parallel FFTs Usng Error Correcton Codes and Parseval Checks. IEEE Transon VLSI system. June 2015. 215