EE4 - Spring 008 Advanced Digital Integrated Circuits Lecture 8: Gate delays, Variability Announcements Project proposals due today Title Team members ½ page ~5 references Post it on your EECS web page and send me the link Homework Due February 6 Warning: Long!
3 Agenda Revisit leakage Gate delays Introduction to variability 4
Input Slope Simulated vs. linear model 70 60 50 8 4 Driving gate fanout Delay [ps] 40 30 0 0 0 0 4 6 8 0 FanOut 5 Input slope We can model the delay as t p = 0.7*R ekv C When driving with non-step input, the rise/fall time is absorbed it into R ekv R ekv is different than one extracted straight from I-V The output delay is linearly dependent on input rise/fall time t p = 0.7RC + ηt S η = 0.7 in this example (~/6) The model is limited to a range of fanouts More accurate delay models propagate two quantities: delay and signal slope Both can be modeled either as linear or table lookups 6 3
Standard Cell Library Contains for each cell: Functional information: cell = a *b * c Timing information: function of input slew intrinsic delay output capacitance non-linear models used in tabular approach Physical footprint (area) Power characteristics Wire-load models - function of Block size Fan-out [from K. Keutzer] Library 7 Synopsys Delay Models Linear (CMOS) delay model 8 4
Example Cell Timing 9 Delay Dependency on Edge Rate 0 5
Transition Time Linear: Piecewise linear: Cell Characterization 6
Synopsys Nonlinear Delay Model Delay is a function of: 3 Synopsys Nonlinear Delay Model 4 7
Static Timing Analysis Combinational logic Combinational logic Combinational logic clk clk original circuit clk Combinational logic extracted block [from K. Keutzer] 5 Each Combinational Block Arrival time in 0 green A Interconnect delay in red Gate delay in blue 0 C W.0.0 B.05.05.05 X Y.0.0 Z.5 What s the right mathematical ti object to use to represent this physical object? f [from K. Keutzer] 6 8
Problem formulation - Use a labeled directed graph G = <V,E> Vertices represent gates, primary inputs and primary outputs Edges represent wires Labels represent delays Now what do we do with this? 0 C.05 X 0 W A.0.05 0.0 0 A C B B..05. 0 Y W.05.0.0 X Y Z.5.0.5 f f Z.0 [from K. Keutzer] 7 Problem formulation - Arrival Time Arrival time A(v) for a node v is time when signal arrives at node v A(X) A(Y) X Y d x z Z dy z A(Z) A( υ ) = max (A(u) + d u υ ) u FI( υ) where dυ u is delay from υ to u, FI(υ)= {X,Y}, and υ = {Z}. [from K. Keutzer] 8 9
Static Timing Analysis Computing critical (longest) path delay Longest path algorithm on DAG [Kirkpatrick, IBM Jo. R&D, 966] Used in most ASIC designs today Limitations False paths Simultaneous arrival times 9 False Paths 0 0
Signal Arrival Times NAND gate: Signal Arrival Times NAND gate:
Simultaneous Arrival Times NAND gate: 3 Impact of Arrival Times Delay A Up to 5% B A arrives early B arrives early 0 t A - t B 4
Design Variability Sources and Impact on Design Roadmap Acknowledges Variability International Technology Roadmap for Semiconductors 005 data Node year 007 00 03 06 09 DRAM ½ pitch [nm] 65 45 3 6 Total gate CD 3σ [nm].6.9.4 0.9 0.6 Lithography h 3σ [nm] 4.4 07 0.7 05 0.5 LER 3σ [nm].4 0.7 0.5 http://www.itrs.net/common/005itrs/home005.htm 6 3
Sources of Variability Technology Front-end (Devices) Systematic and random variations in Ion, Ioff, C, Back-end (Interconnect) Systematic and random variations in R, C Environment Supply (IR drop, noise) Temperature 7 Temporal vs. Spatial Variability Temporal variability/correlation Within-node scaling, Electromigration, Hot-electron effect, NBTI, self-heating, temperature, t SOI history effect, supply voltage, crosstalk Spatial variability/correlation Device parameters (CD, t ox, ) Supply voltage, temperature 8 4
Spatial Variability Global Local Fab to fab Temperature Deployed environment Metal polishing Lot to lot Transistor I on, I off Across wafer Line-edge roughness Across reticle Dopant fluctuation After Rohrer ISSCC 06 tutorial Across chip Across block Film thickness 0 6 0 3 0 0 0-3 0-6 0-9 Spatial range [m] 9 Temporal Variability Technology Environment After Rohrer ISSCC 06 tutorial Tech. node scaling Within-node scaling Electromigration NBTI Hot carrier effect Temperature Tooling changes Lot-to-lot Data stream SOI history effect Self heating Supply noise Coupling Charge 0 0 9 0 6 0 3 0 0 0-3 0-6 0 - Temporal range [s] 0-9 30 5
Systematic vs. Random Variations Systematic A systematic pattern can be traced down to lot-to-lot, wafer-to- wafer, within reticle, within die, from layout to layout, Within-die: usually spatially correlated Random Random mismatch (dopant fluctuations, line edge roughness, ) Things that are systematic, but e.g. change with a very short time constant t (for us to do anything about it). Or we don t unedrstand d it well enough to model it as systematic. Or we don t know it in advance ( How random is a coin toss? ). 3 Dealing with Systematic Variations Lin, DAC 06 tutorial 3 6