Experiment 3 3 MOSFET Drain Current Modeling 3.1 Summary In this experiment I D vs. V DS and I D vs. V GS characteristics are measured for a silicon MOSFET, and are used to determine the parameters necessary for the square law model. The device tested in this experiment is a commercially available n-channel MOSFET switching transistor. The results are compared to theoretically calculated characteristics for a device that was fabricated in the microfab of the Department of Electronics at Carleton University. 3.2 Theory A MOSFET, or Metal-Oxide-Semiconductor Field Effect Transistor, is a transconductance device constructed by depositing a layer of insulting dielectric, referred to as the oxide, on the surface of a doped semiconductor sample, referred to as the substrate. A conductive layer of aluminum or polycrystalline Silicon is then deposited on top of the dielectric, forming the gate. Diffusions of opposite type to the substrate are then formed on either side of the gate, called the source and drain. We define the width of the transistor to be the extent of the gate electrode along the line of the diffusion and the length to be the distance between the source and drain under the gate. Figure 1 below shows a typical integrated MOSFET structure. In simple terms, the MOSFET conducts current between the source and drain only when there is a conductive path between the terminals. This conductive path, often called a channel, is created by establishing a sufficient potential on the gate to attract a large concentration of minority carriers to the surface of the substrate under the gate. If the substrate is p-type, the minority carriers will be electrons, and a positive gate potential will be required to attract these electrons to the surface. Since the conductive path in this case is composed of minority electrons, the device is called n-channel. Similarly, if the substrate is n-type, the minority carriers will be holes, and a negative potential will be required on the gate to attract the holes to the surface. A device whose conductive path is formed from minority holes is called a p-channel device. In the following discussion, we will assume a p-type substrate, hence an n-channel device whose conductive path is formed by electrons.
Figure 1. Integrated MOSFET Structure Although the exact details of operation of the MOSFET are quite involved, and will be covered in detail in the lectures, it is enough for this experiment to note that there are basically three modes of operation for the MOSFET: cutoff, triode and saturation. When the gate to source potential is not sufficient to cause the conductive electron path to form, no current can flow between the source and drain regardless of the value of the drain to source potential, and the device is said to be in the cutoff region. The critical value of gate to source voltage necessary to cause conduction between the source and drain is usually referred to as the threshold voltage, and given the symbol V T. The condition for cutoff is then V GS < V T. If the gate to source potential is large enough to cause a conduction channel to form but the drain to source voltage is small, the current flowing between the source and drain will be a function of both the gate to source and drain to source voltages. This operating region, called the triode region, will persist until the drain to source voltage reaches a particular value called the saturation voltage, usually given the symbol V DSsat. This is in fact the point where the concentration of electrons in the channel at the drain end, which is affected by the drain to source potential, becomes very small. If the drain to source potential is increased past this point, the current ceases to become a strong function of the drain to source voltage, instead being mostly determined by the gate to source voltage. This device is then said to be in the saturation region of operation. However, there is a weak residual dependence of the current on the drain to source voltage, an effect known as channel length modulation because it arises from an intrusion of the drain depletion region into the channel. As the channel length of a device becomes shorter, the channel length modulation term becomes more prominent because the intrusion of the drain depletion region becomes a greater fraction of the total channel length. The simplest set of equations for the drain current is the square-law model, arrived at by considering the amount of charge under the gate as a function of bias, then integrating the expression along the channel to arrive at the final current equation. For this model, the saturation drain source voltage is given by:
V DSsat = V GS V T where: V T = the threshold voltage (V) (1) In the triode region, the current expression is: W " I D = µ n Ĉ ox $ L V V V DS GS T # ( ) V DS 2 2 % ' for V GS > V T and V DS < V DSsat & where: µ n = the suface mobility of electrons (cm 2 /V-sec) Ĉ ox = ε ox t ox = the oxide capacitance per unit area (F/cm 2 ) (2) In the saturation region, the current is only weakly dependent on the drain source voltage, modeled by the inclusion of a λv DS term, where λ is called the channel length modulation parameter. The current in saturation is modeled by ( V GS V T ) 2 ( 1+ λv DS ) for V GS > V T and V DS V DSsat W I D = µ n Ĉ ox L 2 where: λ = the channel length modulation parameter (1/V) (3) The threshold voltage, for reasons that will be described in class, is a function of the bias voltage between the substrate and source, an effect called threshold modulation. This dependence is modelled by having the threshold voltage be the sum of a zero bias value plus a term depending on the source substrate bias, specifically V T = V T 0 +γ ( V SB + 2φ F 2φ F ) where: V T 0 = the zero bias threshold voltage (V) γ = the threshold modulation coefficient ( V) V SB = the source to bulk (substrate) potential (V) φ F = the bulk potential 0.6 V (4) Extraction of the parameters in the equations (2) and (3) for I D above is accomplished as follows. First, a measurement of I D vs. V GS in the triode region (c.f. the latter equation above) with V SB = 0, is plotted as I D vs V GS will yield the term µ ˆ n C ox V DS W L as the slope of the linear portion, and V T0 as the projected intercept on the x axis, assuming that the value of the channel length modulation term, λ, is small. Measuring the same characteristic for non-zero values of substrate voltage will give the threshold modulated V T as the intercept, and allows the value of γ to be extracted.
ELEC 3908 Experiment 3 3.3 Experiment The setup in the lab has been constructed to allow MOSFET ID characteristics to be measured using the Agilent HP4145 semiconductor parameter analyzer, as used in the previous two experiments. Both ID vs VDS at fixed VGS and ID vs VGS at fixed VDS characteristics will be investigated. The bulk voltage, VB, will be adjusted to enable the extraction of the threshold modulation parameter. Appendix A gives a detailed description of the general steps required to configure the equipment for measurement this can be used to refresh your memory of the details of operation of the 4145 that you learned during Experiments 1 & 2. If you encounter difficulty in any aspect of the lab, please consult a TA. The first 4145 MOSFET measurement will be a typical active region ID vs. VDS at constant VG plot. 1. Ensure that the CD4007 MOSFET IC is inserted into the ZIF socket and that the lever is down as shown in the Figure below. Do not touch the chip as it is highly susceptible to static discharge. The test box is wired such that SMU1, SMU2, SMU3 and SMU4 connected to the source (pin 4), drain (pin 5), gate (pin 3), and bulk (substrate) (pin 7), respectively. This allows us to measure an isolated n-channel MOSFET that is part of the circuit with a separate connection to the substrate. 2. Using the CHANNEL DEFINITION menu press the soft key marked FET, VDS-ID to initialize the setup to be close to that desired for the MOSFET. Name the channels such that the voltages and currents associated with the source, drain, gate, and substrate (bulk) have been named VS, VDS, VG, VB, IS, ID, IG and IB. Now make the appropriate changes so the system will be configured so that the source (SMU1) functions as ground (MODE = COM), the drain (SMU2) functions as a sweeping voltage source (MODE = V, FCTN =VAR1), the gate (SMU3) functions as a stepping voltage source (MODE = V, FCTN = VAR2) and the bulk (SMU4) as a fixed voltage (MODE = V, FCTN = CONST).
3. Using the SOURCE SET UP menu, set the drain voltage, V DS, to sweep from 0 to 5 V, the gate voltage, V G, to sweep from 1V to 6V in steps of 1V and the bulk voltage, V B, to be set to 0 V. Be sure to set the current compliance on V DS such that the plotted curves are not current limited. 4. Using the MEAS & DISP MODE SET UP menu, set up the graphics plot to give I D vs V DS (which is identical to V D since V S = 0), with V DS from 0 to 5V and I D from 0 to 10 ma, make the measurement and observe the plot on the screen (consult a TA if you are not sure of what the plot should look like). Capture a copy of this plot for your write-up. 5. Leaving all the other configuration settings as they were use the SOURCE SET UP menu to change the bulk voltage to V B = -1V (V SB = 1V). Capture a copy of this plot for your write-up. Now the measurements in 3-5 above need to be repeated to capture numerical data to be analyzed later. 6. Using the SOURCE SET UP menu, set the drain voltage to sweep from 1V to 5V in steps of 1V, the gate voltage to step from 4V to 6V with 2 steps of 2V and the bulk voltage to be set to 0 V. 7. Using the MEAS & DISP MODE SET UP menu, change to list mode and set up to list I D and make the measurement. Capture a copy of this data to use in the analysis. 8. Again, leaving all the other configuration settings as they were use the SOURCE SET UP menu to change the bulk voltage to V B = -1V (V SB = 1V). Measure and capture a copy of the data to use in the analysis. The next step is to perform the measurements necessary to extract the MOSFET parameters in equations (2) and (4) above. To do this the I D vs. V G at constant V DS characteristics will be measured. 9. The system should be configured using the CHANNEL DEFINITION menu so that the source (SMU1) functions as ground (MODE = COM), the drain (SMU2) functions as a fixed voltage source (MODE = V, FCTN = CONST), the gate (SMU3) functions as a sweeping voltage source (MODE = V, FCTN = VAR1) and the bulk SMU (SMU4) as a sweeping voltage source (MODE = V, FCTN = VAR2). 10. Using the SOURCE SET UP menu, set the gate voltage, V G, to sweep from 1 to 6V, the bulk voltage, V B, to step by -1 V from 0V to -3V and the drain voltage, V DS, to be set to 0.1 V. 11. Using the MEAS & DISP MODE SET UP menu, set up the graphics plot to give I D vs V G, with V G from 1V to 6V and I D from 0 to 1 ma, make the measurement and observe the plot on the screen (consult a TA if you are not sure of what the plot should look like). Capture a copy of this plot for your write-up.
12. In order to accurately determine the slope and intercept of the linear triode region of the I D vs V G characteristic we will use the line function built into the 4145. Capture this plot. You will need the data to extract the MOSFET square law model parameters. 13. Skip to the next curve (the next value of V B ) using the marker skip softkey and redo the slope and intercept measurement and capture the new data. Repeat this for all the curves.
3.4 Data Analysis A photomicrograph of the device tested is shown in figure 2 below. The isolated n- channel MOSFET is shown surrounded by the dashed box. The drawn gate length of this device is about 12 µm. However, lateral diffusion of the source and drain under the gate leads to an effective gate length of about L = 10 µm for the device. The channel width is about W = 350 µm, and the gate oxide thickness is about t ox = 50 nm. Figure 2. CD4007 IC with measured n-channel Silicon MOSFET device in box 1. From the slope of the curves measured in parts 11 and 12 above at V DS = 0.1V, extract the value of the channel mobility, µ n by using Eqn. (2). Use the given values for W and L and calculate Ĉox from the value of t ox. 2. From the intercept of the linear portion of the curve with the voltage axis in parts 11 and 12, determine the threshold voltage for each value of V SB, and hence find V T0 and γ by using Eqn. (4). 3. Using the measured numerical data (from steps 6 to 8) and the extracted parameters from above, plot the theoretical prediction of the square law model on the same axis as the
ELEC 3908 Experiment 3 measured data. Note that this will involve finding the saturation drain source voltage in each case then applying Eqn. (2) and Eqn. (3) using experimental values for the parameters (in all cases assume that channel modulation can be ignored). The final plots should compare four theoretical curves of ID vs VDS for VG = 4V, 6V and VSB = 0V, 1V and the corresponding measured data. A photomicrograph of an n-mosfet device fabricated in the Carleton University Microfabrication Facility (CUMFF) is shown in figure 3 below. The drawn gate length of this device is 5 µm. However, lateral diffusion of the source and drain under the gate leads to an effective gate length of L = 3.5 µm for the device. The channel width is W = 25 µm, and the gate oxide thickness is tox = 200 nm. Figure 3. Carleton DOE Integrated Silicon MOSFET Device 4. Using your values of µn. and VT0 from above, plot the predicted of ID vs VDS curves for this device at VG = 3V, 5V and VSB = 0V by applying Eqn. (2) and Eqn. (3). 3.5 References 1. 2. 3. 4. Streetman, B. G., Solid State Electronic Devices, ed., Sections 8.3.5-8.3.9. Puifrey, D. and Tarr, N. G., Introduction to Microelectronic Devices, pp. 200-206, 216. Muller, R. S. and Kamins, T. I., Device Electronics for Integrated Circuits, pp. 422-442. Tsividis, Y. P., Operation and Modeling of the MOS Transistor, pp. 75-98, 102-117