SiC MOSFET Reliability - PDF Free Download

SiC MOSFET Reliability - Oxide lifetime / breakdown - High-energy Neutron radiation ruggedness Daniel J Lichtenwalner, Edward Van Brunt, Shadi Sabri, Jim Richmond, Brett Hull, David Grider, Scott Allen, John Palmour Wolfspeed, a Cree company Radiation testing support from Akin Akturk, Brendan Cusak, Jim McGarrity (CoolCad Electronics, LLC ) ARL MOS Workshop - August 17, 2017 A CREE COMPANY 2015 2015 Cree, Cree, Inc. Inc. All rights All rights reserved reserved

WOLFSPEED PRODUCT OVERVIEW: POWER, RF, MATERIALS 2

SiC POWER MOSFETS: devices & applications SiC power devices demonstrate performance & efficiency advantages, that lower system costs Die, Discrete devices, and Power Modules (Diodes, MOSFETs) 3 Die Discrete devices Applications: Transportation, Energy Industrial LED drivers CREE POWER PRODUCTS brochure (2015). wind solar Electric trains Power supplies Power Modules Motor drives EV chargers

WOLFSPEED POWER MOSFET (Z-FET TM ) PORTFOLIO 4 R&D Demonstrations of MOSFETs to 15 kv, IGBTs to 27 kv, & GTO Thyristors to 20 kv New! Silicon Carbide Power MOSFET C3M Planar MOSFET Technology N-Channel Enhancement Mode Wolfspeed introduces its latest breakthrough in SiC power device technology: the industry s first 900-V MOSFET platform. Optimized for high-frequency power electronics applications, including renewableenergy inverters, electric-vehicle charging systems, and three-phase industrial power supplies, the new 900-V platform enables smaller and higher-efficiency nextgeneration power conversion systems at cost parity with silicon-based solutions.

OUTLINE: Lifetime/reliability tests for MOS devices 5 Key reliability tests related to SiC MOS devices Gate Field (~V GS ) dominated failure: 1. Time-dependent dielectric breakdown (TDDB) Accelerated gate oxide lifetime testing under constant or ramped V GS bias Extrapolation to use gate field for lifetime prediction Drain Field (~V DS ) dominated failure: 1. High- Accelerated blocking tests with V DS bias near avalanche Extrapolation to use drift field for lifetime prediction 2. Cosmic radiation single-event burnout (SEB) Accelerated lifetime test under high-flux N bombardment Measured at device use fields, no field extrapolation needed!

Log (Failure Rate) DEVICE LIFETIME SCHEMATIC: HTRB, TDDB, NEUTRON SEB 6 TDDB = f(v GS ) General effects of HTRB, TDDB, and Neutron Radiation Random fail region Wear-out region HTRB = f(v DS ) Neutron-SEB = f(v DS, V GS, h, T) SEB f(v DS, V GS, h, T) HTRB f(v DS ) TDDB f(v GS ) Device design, oxide quality & oxide thickness affect slopes of HTRB & TDDB lifetime curves Log (operation time)

1.1 TIME-DEPENDENT DIELECTRIC BREAKDOWN (TDDB) 8 Many devices need to be taken to breakdown for evaluation of failure distributions Constant voltage TDDB (or HTGB) can be used to determine oxide lifetime; typically many packaged devices are stressed simultaneously in an oven at moderate V GS levels Large-area N-cap (2mmx2mm) Ramped TDDB is more amenable to on-wafer testing on a probe station, and allows testing of many devices in hours instead of days Can test Ncaps with gate area similar to MOSFETs. Results are of practical significance only if large areas are tested! 1200V 80mohm MOSFET wafer

Gate Current (A) 1.2 RAMPED TDDB: Gen2 1200V MOSFETS (20 V GS use), ~100 parts, 150 C 9 I G -V G, 100 parts, V GS ramp 2 V/s Weibull failure plot 1E+00 1E-02 1E-04 1E-06 1E-08 1E-10 1E-12 Ramped TDDB - G2 1200V MOSFET F-N tunneling Oxide breakdown 10 20 30 40 50 60 Gate Voltage (V) ln(-ln(1-f)) 2 1 0-1 -2-3 -4-5 -6 G2 MOSFET R-TDDB Gen2 oxide 150C 25 30 35 40 45 50 55 60 Failure Voltage (V) On-Wafer testing, results obtained in a few hours Sharp Weibull indicates good oxide quality for all devices 99.9% 99% 90% 50% 10% 1%

Ln(-Ln(1-F)) 1.2 RAMPED TDDB: Gen3 oxide, Ncaps (15 V GS use), ~250 parts, 150 C 10 I G -V G, 250 parts, V GS ramp 2 V/s Weibull failure plot Gate Leakage (A) 1E+00 1E-02 1E-04 1E-06 1E-08 1E-10 1E-12 250 Ncaps - G3 oxide 150 C 0 10 20 30 40 50 Gate Voltage (V) 2 1 0-1 -2-3 -4-5 -6-7 Weibull: G3 oxide, 250 Ncaps, 150 C 20 25 30 35 40 45 50 55 Breakdown Voltage (V) 99.9% 99% 90% 50% 10% 1% 0.1% Gen3 oxide, for 15 V GS use: similar breakdown field & Weibull as Gen2 oxide

Time (hrs) 1.2 Ramped TDDB lifetime extrapolation: 2x2mm 2 Ncaps (750 devices) 11 Varied sweep rates allows calculation of field acceleration factor, g~38 nm/v 3 ln(-ln(1-f)) 2 1 0-1 -2-3 -4-5 -6-7 Rrate (V/s) 2.00 Rrate (V/s) 0.67 Rrate (V/s) 0.20 42 44 46 48 50 52 54 56 Failure Voltage (V) 1 Fail time = t(0)*exp(g*(e fail -E use )) t(0) = dt/(1-exp(-g*de) dt, de = ramp step time & field Ramped TDDB extrapolation (solid blue line) & constant-v TDDB (points) lifetime extrapolations agree 10 9 1E+09 1E+08 10 7 1E+07 1E+06 10 5 1E+05 1E+04 10 3 1E+03 1E+02 10 1 1E+01 TDDB & lifetime extrapolation Ramped TDDB extrapolation constant-v TDDB (points) 15 20 25 30 35 40 45 Gate Voltage (V) 1 H.C. Cramer et al., CS MANTECH, p.91 (2006) Extrapolated TDDB mean fail time at 20 V GS >10 8 hrs

1.3 3.3kV SiC MOSFETS 13 Confocal/DIC Image of 10 µm thick SiC Epi 250 µm Confocal/DIC Image of 30 µm thick SiC Epi 250 µm 50 µm AFM Image of pit AFM Depth Profile 5 µm 5 µm 12 nm

1.3 3.3kV SiC EPITAXIAL WAFERS: LARGE Ncap R-TDDB, 150 C 14 Each capacitor: 4.31 mm 2 ; Total area tested: 334 capacitors, 14.4 cm 2 Ramped TDDB shows tight failure distribution, similar to that on thinner/smoother SiC epi

1.3 3.3kV SiC EPITAXIAL WAFERS: R-TDDB LIFETIME EXTRAPOLATION 15 R-TDDB Weibull plots with varied ramp rates Linear field accel. factor g~40nm/v Lifetime extrapolation using measured field acceleration factor 1% failure time >10 8 hrs No early failures observed within experimental population

1.3 3.3kV SiC EPI: R-TDDB LIFETIME & SiC MORPHOLOGY 16 T 1% : > 2 10 8 hours Two earliest failures do have large macroscopic defects MOSFETs fabricated on these defects will fail routine parametric electrical tests

2.3 mm 1.4 10kV SiC epi (~100um thick SiC): LARGE Ncap R-TDDB, 150 C 17 Ramped Breakdown IV curves 2.3 mm 250 MOS Capacitors Total gate area = ~10 cm 2 Tight failure distribution

1.4 10kV SiC epi: Failure voltage independent of surface texture 18 Extracted capacitor failure voltages Inset: examples of epi surface texture Tight failure distribution despite SiC surface roughness

TDDB SUMMARY 19 Breakdown extrapolations show that expected oxide lifetime is high (>1 10 8 hrs) at use voltage (20 V GS Gen2, 15 V GS Gen3) Even rough, thicker SiC epi does not impact oxide breakdown significantly Thus, oxide trap states or SiC epi defects do not observably impact oxide lifetime

Drain-Field-Related Device Lifetime: 1) High-temperature reverse-bias (HTRB) 2) Neutron-induced Single-Event Burnout (SEB) A CREE COMPANY 2015 2015 Cree, Cree, Inc. Inc. All rights All rights reserved reserved

Current (ma) 2.1 HIGH TEMPERATURE REVERSE BIAS (HTRB) 21 JEDEC HTRB Qualification 150 C, V DS = 80% of rated voltage (960V for 1200V part) 3 Lots x 25 Packaged Devices per Lot, testing for 1000hrs with no fails Guarantees part quality, but does not predict ultimate lifetime Accelerated tests (V DS >1400V) are needed to determine device lifetime Avalanche sets limit to V DS acceleration 12 10 V GS = 0V Avalanche ~1650V 8 6 4 2 0 0 500 1000 1500 2000 Drain Bias (V)

Time (hrs) 2.1 HIGH-TEMPERATURE REVERSE-BIAS (HTRB) ACCELERATED TESTING 22 1200V 20A G2 MOSFETs, V GS = 0 V Devices stressed at V DS @ 1460V, 1540V, or 1620V Extrapolation line gives predicted mean failure time at given V DS (each data point is a mean failure time) 1E+09 10 9 1E+08 10 7 1E+07 1E+06 10 5 1E+05 1E+04 10 3 1E+03 1E+02 10 1 1E+01 600 1,000 1,400 1,800 Drain Voltage (V) Extrapolated HTRB mean failure time at 800 V DS ~3x10 7 hrs (~3,400 yrs Lifetime at lower V DS cannot be directly measured (time too long)

3.1 Single-Event Effects (SEE) due to terrestrial Neutrons 24 The high energy flux of neutrons from Cosmic radiation (terrestrial neutrons) can cause burnout in devices with high drain fields Failure Mechanisms in Literature Parasitic NPN turn-on, single-event burnout (SEB) if impact is near source Single-event gate rupture (SEGR) if impact is near gate and gate field is high Either failure results in a localized device thermal runaway SEB SEGR If testing is not accelerated, would need thousands of parts monitored in blocking for many years P.C. Adell, L.Z. Scheick, IEEE TNS 60, 1929 (2013).

3.1 Single-Event Burnout (SEB) due to terrestrial Neutrons 25 Los Alamos National Lab Neutron source at LANSCE; test acceleration of ~10 9 X that at sea level (S. Wender, LANL 2013) No lifetime extrapolation required we measure actual failure rate due to N irradiation at device use fields Failure rate data fitting: we follow a simplified ABB formula (H.R. Zeller 1995; & ABB Appl. note 5SYA 2046-03): FIT = C 3 *exp(c 2 /(C 1 -V DS )) Where Test groups of devices at given V DS to failure Calculate failures in time FIT (per 10 9 device*hrs) scaled to sea level N flux C 3 A,r C 2 = V DS to reach asymptotic regime C 1 = V DS failure onset / threshold

3.1 MEASUREMENT SETUP 26 6 devices/holder (2 holders max) V DS monitored during run; failure time correlated to measured N fluence Re-load fresh devices, apply V DS, run until fail Repeat to get enough V DS points for predicting FIT vs V DS

% surviving 3.2 GENERAL FAILURE BEHAVIOR 27 For each V DS group, the failures occur at a ~constant rate with time formed in the active area due to material overheating 1200V diode: failures per V DS test group 100 90 80 70 60 50 40 30 900 20 1000 10 1100 0 0E+00 1E+10 2E+10 N fluence (N/cm 2 )

3.2 UNDERSTANDING FIT RATES: ACTIVE AREA & DRIFT DESIGN 28 FIT vs V DS for 7 different Cree SiC MOSFET device ratings All scale similarly with Active area & drift field (~avalanche breakdown) 100000 Sea level FIT/cm 2 10000 1000 100 900V MOSFET 1200V MOSFET 1700V MOSFET C3M0065090 X3M0010090 C2M0080120 C2M0025120 C2M1000170 C2M0045170 X3M0045330 10 3.3kV 1 MOSFET no fails T J = 25 C 0.1 400 1000 1600 2200 2800 3400 Drain-Source Voltage, V DS (V) Sea level FIT/cm 2 10000 1000 100 10 1 0.1 Wolfspeed MOSFETs 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V DS /V aval C3M0065090 X3M0010090 C2M0025120 C2M0080120 C2M0045170 C2M1000170 X3M0045330

3.3 FIT RATES: MOSFET vs DIODE 29 FIT vs V DS for Cree 1200V SiC MOSFET & Diode Both device types scale similarly 10000 FIT/cm 2 1000 100 10 1 Sea-level Neutron FIT/cm 2 C2M0080120 1200V MOSFET C4D020120 1200V Diode T J = 25 C 0.1 600 800 1000 1200 1400 Voltage (V) 10000 FIT/cm 2 1000 100 10 1 Sea-level Neutron FIT/cm 2 C2M0080120 1200V MOSFET C4D020120 1200V Diode T J = 25 C 0.1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 V D / V aval

3.4 SiC MOSFETS: CREE vs ROHM, MICROSEMI, STMICRO 30 Devices Compared: All devices show ~similar performance when scaled by area & field (drift field dominates) Devices V rating R rating Vaval (mohm) (approx.) Wolfspeed 1200 75 1560 Wolfspeed 1700 20 1660 Rohm 1200 160 2250 Rohm 1200 40 1900 Microsemi 1200 80 1850 STMicro 1200 240 1300 100000 10000 FIT/cm 2 1000 100 10 1 0.1 SiC MOSFET comparison STMicro 1200V 240mohm Wolfspeed 1200V 75mohm Microsemi 1200V 80mohm Wolfspeed 1700V 20mohm Rohm 1200V 160mohm Rohm Tr1200V 40mohm 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V DS / V aval

Sea level FIT/Amp 3.5 SiC vs Si: 1200V Cree MOSFET vs Infineon Si IGBT4 31 Si parts show sharper failure onset, but higher max failure rate SiC & Si parts may require derating to ~900V DS ; but SiC is best at higher V DS 100 10 Infineon Si IGBT4 1200V 60A 1 0.1 0.01 0/6 failed 0/6 failed Wolfspeed SiC MOSFET 1200V 25mohm T J = 25 C 0.001 700 800 900 1000 1100 1200 1300 Drain-Source Voltage, V DS (V) A comparison of Si versus SiC material radiation hardness is not a fair way to understand this data, as SiC parts have many orders of magnitude longer lifetime than Si at the same drift fields

SUMMARY 32 Oxide breakdown (TDDB) Intrinsic behavior shows that good oxide lifetime can be expected on SiC, despite interface traps and SiC defects Thick epi with increased roughness has virtually no impact on the MOS oxide lifetime High-energy Neutron Single-event burnout SiC diode & MOSFET lifetime is dominated by the drift field and the active area The V DS derating for Si and SiC devices may be ~similar, but this does not diminish the many performance advantages of SiC devices Device design modifications may further improve the radiation hardness of SiC devices (Si rad-hard device design is more mature)