CHAPTER 3 H BRIDGE BASED DVR SYSTEM

23 CHAPTER 3 H BRIDGE BASED DVR SYSTEM 3.1 GENERAL The power inverter is an electronic circuit for converting DC power into AC power. It has been playing an important role in our daily life, as well as in industrial fields. Power inverters are installed in a wide range of consumer products and high-power equipment, including temperature control, light control, motor control, power supplies, bulk transportation systems, HVDC systems and FACTS. And the power rating of those power devices ranges from milli-watts to several megawatts as described by Mohan (2003). Since 1975, many researchers have been dedicated to developing new control methods and new modulation techniques for power inverters. The most popular modulation technique adopted in industrial applications is sinusoidal PWM. The concept is derived from the classical PWM method, in which a modulating signal is compared with triangular carriers to generate the gate signals. Such modulating signal is derived by an error amplifier, typically a proportional-plus-integral controller, which compares the reference signal and the actual output. The error signal will then be combined with a synchronous reference frame to generate a synchronized gate signal. However, due to the limited bandwidth of the overall control mechanism, the actual output will inherently have a phase lag and magnitude error, which will increase with the disturbance frequency. Another modulation technique is the Space-Vector Modulation (SVM), which is dominantly applied to three-phase inverters. It features good utilization of dc-link voltage and low current ripple,

24 but its implementation is generally complex and computationally intensive. As the generation of the space vector table is based on considering the phase and magnitude of the steady-state vectors, the inverter output regulation, and thus the dynamic response, is governed by the output voltage or current controller. An alternative way to regulate the inverter output is to use the boundary control technique, which is based on hysteresis comparison on a well-defined switching surface to determine the switching instants of the output. Typical examples include Hysteresis Current Control (HCC) and sigma-delta modulation (SDM) methods. The concept of HCC is based on continually tracking the actual output current with the reference current within a hysteresis band to generate the gate signals. Some variant techniques use multiple hysteresis bands, with each band representing switching between two adjacent voltage levels. SDM is based on integrating the error between the actual output voltage and the reference voltage, and comparing the integral error with a hysteresis quantizer to dictate the switching states. Such boundary-control-based methods are robust and able to give fast dynamic response to large-signal disturbances, but their fundamental control philosophy relies on observing the instantaneous state variables and generating the gate signals without taking the state trajectory movement into account. 3.2 BRIDGE INVERTERS Bridge inverter can be classified into two categories, namely the half-bridge inverter and the full-bridge inverter. Half-bridge and full-bridge inverters are employed in most household appliances such as air conditioners, washing machines and refrigerators. Their circuit structures and basic operating principles are reviewed and presented below.

25 3.2.1 Half-Bridge Inverters The schematic diagram of a single-phase half-bridge VSI is shown in Figure 3.1(a). It consists of two power switches (S 1 and S 2 ), two power diodes (D 1 and D 2 ) and two cumbersome capacitors (C 1 and C 2 ). The two capacitors are connected in series across the DC input. They split the DC link voltage with a neutral point n, thus the potential across each capacitor is constant and with a value equal to V dc /2. S 1 and S 2 are on/off solid state switches such as SCR, GTO, IGBT or power MOSFET. They cannot be turned on simultaneously as a short circuit across the DC link input would be produced under such situation. D 1 and D 2 are called feedback diodes. They are connected in anti-parallel with S 1 and S 2. There are three switch modes in the single-phase half-bridge VSI. When S 1 is switched on and S 2 is switched off, the instantaneous voltage across the inverter output v o is equal to V dc /2. D 1 conducts when the load is an inductive load. The load current i o would continue to flow through D 1, load and C 1 until the current falls to zero. Likewise, when S 1 is switched off and S 2 is switched on, v o is equal to -V dc /2. i o would continue to flow through D 2, load and C 2 when an inductive load is connected. The output voltage of the inverter is undefined when both S 1 and S 2 are switched off.v o can equal to V dc /2 or -V dc /2, depending on which diode is conducted. Figure 3.1(b) shows the waveform of the inverter when an inductive load is connected. The switch states of single-phase half-bridge VSI are summarized in Table 3.1.

26 Table 3.1 Switch states of single-phase half-bridge VSI. State No Switch states Vo Components conducting 1 S 1 is on and S 2 is off V dc /2 S 1 ifi o > 0, D 1 ifi o < 0 2 S 1 is off and S 2 is on V dc /2 D 2 ifi o > 0, S 2 ifi o < 0 3 S 1 and S 2 are off V dc /2 V dc /2 D 2 ifi o > 0, D 1 ifi o < 0 Figure 3.1 Single-phase half-bridge inverter (a) Schematic diagram and (b) output waveform with highly inductive load 3.2.2 Full-bridge Inverters Figure 3.2(a) shows the schematic diagram of a single-phase fullbridge VSI (H-bridge inverter). It consists of four power switches (S 1 to S 4 ) and four power diodes (D 1 to D 4 ), which double the number of switches and diodes integrated in a single-phase half-bridge inverter. Similar to the halfbridge inverter, S 1 and S 4 in leg a (or S 2 and S 3 in leg b) should not be switched on simultaneously in order to prevent a short circuit across the DC link input.

27 Figure 3.2 Single-phase full-bridge inverter (a) Schematic diagram and (b) output waveform with highly inductive load Table 3.2 Switch states of a single-phase full-bridge VSI State No. Switch states V an V bn V o Components conducting 1 S 1 and S 2 are on and S 3 and S 4 are off V dc /2 V dc /2 V dc S 1 and S 2 ifi o > 0 D 1 and D 2 ifi o < 0 2 S 3 and S 4 are on and S 1 and S 2 are off -V dc /2 V dc /2 -V dc D 3 and D 4 ifi o > 0 S 3 and S 4 ifi o < 0 3 S 1 and S 3 are on and S 2 and S 4 are off V dc /2 V dc /2 0 S 1 and D 3 ifi o > 0 D 1 and S 3 ifi o < 0 4 S 2 and S 4 are on and S 1 and S 3 are off -V dc /2 -V dc /2 0 S 2 and D 4 ifi o > 0 D 2 and S 4 ifi o < 0 5 S 1, S 2, S 3, and S 4 are all off -V dc /2 V dc /2 V dc - V dc /2 -V dc /2 V dc 3 4 o D 1 and D 2 ifi o < 0 D 1 to D 4 are connected in anti-parallel with the switches S 1 to S 4 respectively. When an inductive load is connected, the diodes are conducted and the energy is fed back to the DC link input, hence, they are called feedback diodes. Figure 3.2.b shows the waveforms of the output voltage v and output current i o of a full-bridge VSI when a highly inductive load is connected. There are

28 five switch modes in a single-phase full-bridge VSI and they are summarized in Table 3.2. When S 1 and S 2 are switched on, and, S 3 and S 4 are switched off, the instantaneous voltage across the inverter outputv o is equal to V dc. When S 1 and S 2 are switched off, and, S 3 and S 4 are switched on,v o is equal to -V dc. When either upper switches (S 1 and S 3 ) or lower switches (S 2 and S 4 ) are switched on, v o would become zero. When all the switches (S1 to S4) are switched off,v o is undefined.v o could be V dc or V dc depending on which pair of diodes are conducted. Generally, there are two PWM schemes in full-bridge inverter, namely PWM with bipolar voltage switching and PWM with unipolar voltage switching. In PWM with bipolar voltage switching,v o changes between V dc and V dc only. The harmonic spectrum of the PWM signals and the inverter output voltage are the same. This operation is identical to half-bridge inverter. In PWM with unipolar voltage switching, the output voltage changes between zero and V dc or between zero and V dc. In comparison with the bipolar voltage switching scheme, the unipolar voltage switching scheme has the advantage of effectively doubling the switching frequency across the inverter output voltage. Besides, the voltage step across the inverter output is V dc while the bipolar PWM has a voltage step equals to 2V dc. The peak reverse blocking voltage of each switching device in both half-bridge and full-bridge inverters are the same. Although the fundamental components in full-bridge inverter are double of that in half-bridge inverter, the output power of full-bridge inverter is four times higher than the halfbridge inverter. This is the reason why the full-bridge inverters are preferred in higher voltage and higher power applications.

29 3.3 SIMULATION RESULTS In this chapter, investigations on H-bridge based DVR is done with R, RL, and non-linear loads for change in load conditions by applying different PWM techniques and the results are compared based on the better THD reduction, which is not found in the research works mentioned in the literatures review. Hence a simulation study on the same is taken up and the results are presented and the outcomes are discussed as follows. For a H-bridge based DVR, 50 Hz frequency, the pulse width works out to 10 ms as follows, T = 1/f = 1/ 50 = 20 ms For half cycle, T/2 = 10 ms Pulse width = 10 ms. Therefore the control circuit of the inverter is designed to produce a pulse of width 10ms. The circuit model for DVR system is shown in Figure 3.3. Generator impedance is shown in series with the source. Line impedance is connected in series with the generator. It also shows the line compensation circuit with additional AC source. During normal conditions, there is normal flow of current through load-1 and breaker-3 is closed.when breaker-2 is closed an extra load is added to and voltage sag occurs due to the increased drop. At this point breaker-1 closes and breaker-3 opens and allows additional AC source to inject voltage.

30 The Figure 3.4 shows the voltages across transformer primary. The voltages across loads 1 and 2 are shown in Figure 3.5. The Figure 3.6 shows the line compensation using DVR circuit. The model for DVR is shown in Figure 3.7. The DVR is represented as sub system. The DVR system has four MOSFETs. The Figure 3.8 shows the DVR circuit with LC filter. The LC filter is added with DVR to get better output. It is designed to absorb fifth order harmonics. The Figure 3.9 shows the voltage waveforms of injection and compensated voltage across load-1 and load-2. The Figure 3.10 shows the voltage waveforms of injection and compensated voltage across load-1 and load- 2 with LC filter. From this figure it can be seen that proper voltage is injected to improve the voltage profile. At t = 0.5sec, the DVR injects voltage and the receiving end voltage resumes to the normal value. Thus the voltage quality is improved by using DVR. The data used for simulation is given in appendix I. Br1 AC2 + - v Vt5 e3 1 Li 2 S1 S Br3 Br2 AC LOAD-1 + - v Vt2 e2 LOAD-2 + - v Vt1 e1 Figure 3.3 Line compensation circuit with additional AC source

31 Figure 3.4 Voltage across transformer primary Figure 3.5 Voltage across load-1 and load-2

Figure 3.6 Compensation using DVR circuit 32

Figure 3.7 H-Bridge sub system 33

Figure 3.8 DVR with LC filter 34

35 Figure 3.9 Voltage waveforms of injection, load-1 & load-2 without filter Figure 3.10 Voltage wave forms of injection, load-1 and load-2 with filter

36 PWM methods like single PWM, multiple PWM and SVM are considered to find a better modulation method to reduce the THD of DVR system with RL and non linear loads. Figure 3.11 shows the DVR system with H-bridge inverter with RL load. Figure 3.12 shows the output voltage across DVR and load-1. Here single pulse PWM method is used. Up to 0.2 sec, load-1 is connected to main circuit. At t=0.2 sec load-2 is connected to the main circuit using circuit breaker. As a result voltage sag occurs. At t=0.4 sec, the DVR is connected. As a result the voltage is compensated. Figure 3.13 shows the RMS line voltage with sag and compensation condition. Figure 3.14 shows the FFT analysis for line voltage. It has a THD of 12.9%. Percentage THD is calculated using the formula (V H /V1)*100. Where 2 2 V H = (V 3 + V 5 + V 2 7 ). Figure 3.11 DVR system with RL load

37 Figure 3.12 Voltage waveforms across DVR and Load-1 Figure 3.13 RMS output voltage across load-1

38 Figure 3.14 FFT analysis for line voltage Figure 3.15 shows the DVR system with RL load. Here sine PWM (SPWM) method is used. Figure 3.16 shows the sine PWM pulses for switches. Figure 3.17 shows the output voltage across DVR and load-1. Up to 0.2 sec load-1 is connected. At t=0.2 sec additional load (load-2) is connected. As a result voltage sag occurs. At t=0.4 sec, the DVR is connected and the voltage is compensated. Figure 3.18 shows the RMS line voltage with sag and compensation condition. Figure 3.19 shows the FFT analysis for the line voltage. It has THD of 10.18%. SPWM method has lesser harmonics compared to single pulse method.

39 Figure 3.15 DVR System with RL load Figure 3.16 PWM pulses

40 Figure 3.17 Voltage waveforms across DVR and load-1 Figure 3.18 RMS output voltage across load-1

41 Figure 3.19 FFT analysis for line voltage Figure 3.20 shows the DVR with non-linear load. Figure 3.21 shows the output voltgae waveforms across DVR and load-1. Here single pulse PWM method is used. Upto 0.2 sec, load-1 is connected. At t=0.2 sec an additional load (load-2) is connected. As a result voltage sag occurs. At t=0.4 sec, the DVR is connected and as a result the voltage is compensated. The Figure 3.22 shows the voltage across non linear load. The Figure 3.23 shows the RMS line voltage with sag and compensation across load-1. The Figure 3.24 shows the FFT analysis for line voltage. It has a THD of 12.90%.

42 Figure 3.20 DVR system with non-linear load Fig 3.21 Voltage waveforms across DVR and load-1

43 Figure 3.22 Voltage across the non-linear load Figure 3.23 RMS output voltage across load-1

44 Figure 3.24 FFT analysis of line voltage Figure 3.25 shows the DVR with non-linear load. Uncontrolled rectifier with capacitor is used as a non linear load. Figure 3.26 the output voltgae waveforms across DVR and load-1. Here sine PWM method is used. Upto 0.2 sec, load-1 is connected. At t=0.2 sec an additional load (load-2) is connected. As a result the voltage sag occurs. At t=0.4 sec the DVR is connected and as a result voltage is compensated. Figure 3.27 shows the voltage across non-linear load. Figure 3.28 shows the RMS line voltage with sag and compensation across load-1. Figure 3.29 shows the FFT analysis of line voltage. It has THD of 11.77%. SPWM has less harmonics compared to the single PWM.

45 Figure 3.25 DVR system with non-linear load Figure 3.26 Voltage waveforms across DVR and load-1

46 Figure 3.27 Voltage across the non-linear load Figure 3.28 RMS output voltage across load-1

47 Figure 3.29 FFT analysis of line voltage The THD values obtained in the results of the above mentioned simulations are summarized in the table 3.3. The THD levels are still higher to minimize the THD further SVM method is tried. Table 3.3 Comparison of THD values Type of Load RL Load Non-linear Load Type of PWM Single Single Sine PWM Sine PWM technique PWM PWM THD Values 12.9 10.18 21.2 11.77 3.4 DVR SYSTEM USING SPACE VECTOR MODULATION Figure 3.30 shows the model of DVR system. It consists of threephase source, three-phase load and three-phase DVR with SVM controller.

48 When the load is increased, the voltage sag occurs at the load side. This voltage sag is compensated with the help of DVR. The DVR system is controlled by SVM technique. The line voltage is sensed and it is converted from three-phase into two-phase. From this, reference voltage and angle are obtained. Based on this, PWM signals are generated. These signals are used to control the DVR switches. The Figure 3.31 shows the control blocks. The Figure 3.32 shows the model of DVR. Figure 3.33 shows the load voltage with disturbance. Figure 3.34 and 3.35 show the RMS voltage and current wave forms of the load. Figure 3.36 shows the FFT analysis for line voltage. The THD is 1.39% which is very less compared to the THD values attained in the previous simulation outputs of other PWM techniques, which is shown in table 3.3. Thus the SVM is best method to reduce the harmonics in the output. Figure 3.30 SVM based DVR system

49 Figure 3.31 Block diagram of SVM control Figure 3.32 DVR circuit with SVM control

50 Figure 3.33 Voltage waveforms of phase a, b and c with change in load Figure 3.34 RMS value of voltage with change in load conditions

51 Figure 3.35 RMS value of current with change in load conditions Figure 3.36 FFT analysis for voltage

52 3.5 CLOSED LOOP CONTROLLED DVR To test the performance of DVR in a closed loop condition a closed loop system is simulated and the performance of the DVR is studied. Figure 3.37 shows the closed loop controlled DVR system. It contains AC source, load, DVR and feedback circuits. Line impedance is shown in series with the source. Additional load is connected in series with the existing load to produce voltage sag. When the load increases, the voltage sag occurs in the load voltage. This voltage dip or sag is compensated using DVR. The feedback circuit is used to sense the voltage sag. At the summing point, actual value is compared with set value. This difference is given to PI controller. The comparator produces PWM pulses for DVR switches. When the sag increases, the error signal increases. This increases the output of PI controller. It results in increase of pulse width which is given to the DVR. This increases the RMS value of voltage to be injected by the DVR. Thus the load voltage is regulated. Figure 3.38 shows the model of DVR. Figure 3.39 shows the load voltage and current waveforms with change in load. The RMS voltage and current waveforms of the load are shown in Figures 3.40 and 3.41 respectively. Figure 3.42 shows the FFT analysis for line voltage. From the figures it can be seen that the voltage sag is compensated using closed loop system.

53 Figure 3.37 Closed loop system Figure 3.38 Circuit of DVR

54 Figure 3.39 Voltage and current across load-1 Figure 3.40 RMS Voltage across the load

55 Figure 3.41 RMS current through the load Figure 3.42 FFT Analysis for line voltage

56 3.6 EXPERIMENTAL RESULTS A 1 kw Laboratory model is fabricated and the hardware is tested. The hardware consists of driver board, controller board and filter board. Microcontroller based control circuit is shown in Figure 3.43. The pulses are generated using the microcontroller Atmel 89c2051. Features and descriptions of the same are given in appendix 2. The 12V DC supply required by IC IR2110 is generated by using the regulator IC7812. The 5V DC supply required by the microcontroller is fed by the IC 7805. Crystal and capacitors are connected to the microcontroller as specified in the data sheet. Reset switch is used to reset the microcontroller. These pulses are amplified to 12V using the driver IC IR2110, the features of the same is described in appendix 4. The flow chart for the controller program is shown in Figure 3.44. The corresponding delay subroutine is shown in Figure 3.45. The Assembly language program is given in appendix-7. Top view of the hardware is shown in Figure 3.46. Pulses from the microcontroller are shown in Figure 3.47. The amplified pulses from the driver are shown in Figure 3.48. The output voltage of inverter is shown in Figure 3.49. The harmonics are filtered using the LC filter and the output after the LC filter is shown in Figure 3.50. The Figure 3.51 shows the AC input voltage. PWM technique is used to generate the pulses required by rectifier and inverter. The advantage of PWM is that it reduces lower order harmonics. The filter is required only for higher order harmonics.

57 U1 1 2 VIN VOUT 12V U2 1 2 VIN VOUT 5V TX1 1 2 D1 1N4500 1 2 D2 1N4500 L7812/TO3 L7805/TO220 R1 1k VAMPL = 230V V1 FREQ = 50HZ 1 2 D4 1N4500 1 2 D5 1N4500 C1 1000E-6 D3 LED 0 C5 33E-12 C7 33E-12 R10 Y1 ZTB SW1 12 13 14 15 16 17 18 19 5 4 1 20 U4 SW C10 PUSHBUTTON P1.0/AIN0 P1.1/AIN1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 RST/VPP VCC AT89C2051 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.7 2 3 6 7 8 9 11 100E 2 1 47E-6 47E-6 100E 2 1 47E-6 47E-6 11 U3 10 12 HIN LIN SHDN 2 6 COM 3 VB 9 VCC 5 VDD 13 VS VSS 11 2 6 3 9 5 13 IR2110 U5 10 12 HIN LIN SHDN COM VB VCC VDD VS VSS IR2110 HO LO HO LO 7 1 7 1 22E 22E 22E 22E M1 M2 M3 M4 0 1k 10E-6 Figure 3.43 Microcontroller based control circuit

58 START PORT INITIALIZATION MOVE DATA 55H TO PORT1 CALL DELAY-1 MOVE DATA 00 H TO PORT1 CALL DELAY-2 MOVE DATA 55H TO PORT1 CALL DELAY-1 MOVE DATA 55H TO PORT1 CALL DELAY-2 Figure 3.44 Main routine

59 Delay Move data to Register R1 Decrement R1 Is R1 = 0 N Y RET Figure 3.45 Delay subroutine

60 Figure 3.46 Top view of the hardware Figure 3.47 Pulses from microcontroller

61 Figure 3.48 Amplified pulses from the driver IC IR2110 Figure 3.49 The output voltage of inverter without filter

62 Figure 3.50 The output voltage of inverter with LC filter Figure 3.51 AC input voltage

63 3.7 CONCLUSION In this chapter, a MATLAB Simulink model for two bus system with DVR is developed. The DVR using the H-bridge inverter is simulated using this model. The developed model is tested against R, RL, non-linear loads and the results are presented. For all the load conditions DVR successfully mitigated the voltage sags caused by the change in load conditions. Single pulse PWM and Sine PWM techniques are applied for the H-bridge based DVR with RL and non-linear loads. Comparison of THD values obtained from the above simulation results are given in table 3.3. From the table it is clear that, when sine PWM technique is used, THD value is reduced by 21% for RL load and 44% for non-linear load. Then SVM based DVR system is also modelled and simulated. This system has minimum value of THD. The THD value is 1.4%. Since SVM technique has very less THD compared to other PWM techniques it is a better suited one. Then a closed loop controlled DVR system is also modelled and simulated. The simulation results of closed loop system are presented. The corresponding results indicate that the load voltage is maintained constant and also it is proved that, DVRs can reduce the problem of harmonics caused by non-linear load machinery. A 1 kw prototype model for H-bridge is implemented using an embedded microcontroller. The results of hardware set-up are also presented. But, still the three-level H-bridge inverter based DVR contains considerable harmonics in the output. In order to reduce the harmonics further, a nine-level converter is considered for the DVR system. The investigation on nine-level inverter is presented in the next chapter.