1 A Low-Offset Latched Comparator Using Zero-Static Power Dynamic Offset Cancellation Technique Masaya Miyahara and Akira Matsuzawa Tokyo Institute of Technology, Japan
2 Outline Motivation Design Concept Proposed Comparator Measurement Results Conclusions
Motivation Comparator performance is important in comparator based ADCs. Vin +VFS Comparators 2 N N bit -VFS Comparator offset Low linearity, Low SNDR 3
Influence of the offset voltage ENOB is deteriorated by the offset voltage. ENOB = N 1 log 2 2 V off 1+ 12 V q ( σ) 2 N : Resolution [bit] V off (σ) : Offset voltage @ 1sigma V q : 1 LSB ideal voltage V q =15.6 mv @ 1Vp-p V off (σ) < 3.9 mv (ENOB > 5.6 bit) 1bit down @V off (σ) = 1/2 LSB 4
Conventional Offset Cancellation Using pre-amplifiers with offset cancellation techniques High voltage gain, wide bandwidth amplifier is needed Consume static power Digital calibration techniques [2] Dynamic circuit, no static power Accuracy is limited by the resolution of calibration DAC Calibration is executed before operation We propose the zero static power dynamic offset cancellation technique. [2] G. Van der Plas, et al., ISSCC 2006. 5
6 Outline Motivation Design Concept Proposed Comparator Measurement Results Conclusions
M.Miyahara, A-SSCC 2008. 7 Double-tail Latched Comparator V out out d L
Offset voltage contribution Each stage s contribution to the offset voltage obtained from Monte-Carlo simulation. 24 Input referred offset voltage V off (σ) [mv] 20 16 12 8 4 1st stage 2nd stage All 90nm CMOS process W/L = 1 µm / 0.1 µm V DD = 1.0 V f c = 500 MHz 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input common mode voltage V cm_i [V] 8
Offset voltage contribution Each stage s contribution to the offset voltage obtained from Monte-Carlo simulation. Input referred offset voltage V off (σ) [mv] 24 20 16 12 8 4 0 1.35 mv 1st stage 2nd stage All 8.7 mv 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input common mode voltage V cm_i [V] Mismatch of the 1st stage transistors becomes dominant The most of the offset voltage of the 1st stage is input transistor s threshold voltages (V T ) Input common mode voltage (overdrive voltage of the input transistors) should be kept low 9
10 Design Concept The V T mismatch of the input transistors must be canceled. The overdrive voltage of the input transistors should be decided without being affected by the input common mode voltage. An offset cancellation circuit must be realized without static current for low power operation.
11 Outline Motivation Design Concept Proposed Comparator Measurement Results Conclusions
Proposed Comparator V cm_i V in+ 2nd stage M8 M6 M7 M9 D i- D i+ MR1 R V DD L L V DD M14 M15 M12 M13 M10 M11 V out+ V out- M3' M4' M1' M2' V DD 1 1 2 2 1st stage V ct+ V ct- V cb C C- C C+ M5' Mb V b 1 MR2 R The 1st stage is modified to cancel the mismatch voltage. C c+, C c- : Offset canceling capacitor V b : Bias voltage to set the overdrive voltage of M1' and M2' MR1, MR2 : Switches to reset C c+ and C c- V cm_i V in- 12
Proposed Comparator Behavior V cm_i V in+ 2nd stage M8 M6 M7 M9 D i- D i+ MR1 R V DD M12 V out+ L L M14 M3' M1' M4' M2' V DD C C- C C+ M5' V DD M10 M11 Mb M15 V b 1 M13 V out- 1 1 2 2 1st stage V ct+ V ct- V cb MR2 R [V] [V] [V] [V] 0.5 0.25 0.0 1.2 0.6 0.0 1.2 0.6 0.0 1.2 0.6 0.0 2.0n 3.0n V cm_i V in- V V V V c+ c 1 od1 od2 V V V ct+ V ct- cb cb = V V off 2 D i- D i+ L R 4.0n 5.0n 6.0n Time [s] V V in = V cm_i cm_i + V in V V b + V b th1 th2 V V b b 13
Simulation Results : V cm_i Variation Proposed comparator can suppress increase of offset voltage caused by V cm_i variation. V off (σ) [mv] 14 12 10 8 6 4 2 0 2.6 mv 10.7 mv 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V cm_i [V] Proposed Conventional 90nm CMOS process V DD = 1.0 V V b = 0.1 V f c = 500 MHz All transistor channel length is minimized. Each transistor channel width is optimized for fast latching. 14
Simulation Results : V b Variation V off (σ) [mv] The bias voltage V b had better to be set low. However, too much small overdrive voltage causes a deterioration of the latch speed. 16 14 12 10 8 6 4 2 0 2.3 mv 0.0 0.2 0.4 0.6 0.8 1.0 90nm CMOS process V DD = 1.0 V V cm_i = 0.6 V f c = 500 MHz V b [V] 15
16 Outline Motivation Design Concept Proposed Comparator Measurement Results Conclusions
Layout A prototype comparator has been realized in a 90 nm 9M1P CMOS technology with a chip area of 0.0354mm 2. The core comparator size is only 152 µm 2. 27 µm 5.6 µm 361 µm Output selector & decoupling capacitor 98 µm 64 comparators with SR Latch Input switches Ground line & decoupling capacitor 27 µm 17
18 Measurement System Ramp wave, F in = 1MHz V out CLK V b V in - V cm V in + V offset V out The offset voltage is the input voltage at the point that output changes from low to high.
Measurement Results: V b Variation The offset voltage can be minimized in case of V b = 0.15 V. 12 10 V off (σ) [mv] 8 6 4 3.8 mv V DD = 1.2 V V cm_i = 0.6 V f c = 500 MHz 2 0 0.0 0.2 0.4 0.6 0.8 1.0 V b [V] 19
Measurement Results: V cm_i Variation 14 The offset voltage increases by only 0.4 mv when V cm_i changes from 0.6 V to 0.9 V. V off ( ) [mv] 12 10 8 6 4 2 Proposed (Sim) Conventional (Sim) Measurement The measured offset voltage is slightly higher than simulation result. => Dummy metals affect to mismatch 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V cm_i [V] 20
21 Performance Summary Technology 90nm, 1poly, 9metals CMOS Active Area 5.6µm x 27µm (core comparator) V offset (σ) 3.8 mv (ENOB = 5.6 bit @ 1Vp-p) Supply Voltage 1.2 V Power consumption 4.8mW @ 500 MHz * * Power consumption includes 64 comparators, I/O buffers and clock drivers. Simulated power consumption of the comparator is 68 µw/ghz.
22 Outline Motivation Design Concept Proposed Comparator Measurement Results Conclusions
23 Conclusion A low offset voltage dynamic latched comparator using a zero-static power dynamic offset cancellation technique is proposed. Features The proposed comparator consumes no static power. Measured results show the input offset voltage is improved from 12.8 mv to 3.8 mv by using proposed technique. The offset voltage of the comparator does not change by increasing the input common mode voltage.
24 Thank you for your interest! Masaya Miyahara, masaya@ssc.pe.titech.ac.jp