Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.3, JUNE, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/jsts.2017.17.3.401 ISSN(Online) 2233-4866 Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs Jin-Young Choi Abstract In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixedmode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the V DD and V SS buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements. Index Terms ESD protection, diode protection device, mixed-mode simulation, parasitic bipolar transistor, RF ICs I. INTRODUCTION CMOS chips are vulnerable to electrostatic discharge (ESD) due to the thin gate oxides used, and therefore protection devices are required at input pads. Larger size is preferable for the protection devices to reduce Manuscript received Oct. 5, 2016; accepted Mar. 27, 2017 Dept. of Electronic & Electrical Engineering, Hongik University, Sejong, Korea E-mail : jychoi@hongik.ac.kr discharge current density and thereby to protect them against thermal-related problems. However, adopting a large size tends to increase parasitic capacitances added to the input nodes generating other problems such as gain reduction and poor noise characteristics in RF ICs [1]. To reduce the added parasitics, various techniques have been suggested. However, basic approaches should be to reduce size of protection devices connected to input nodes, and protection schemes utilizing diodes are most popular in RF ICs [2-4]. In the diode input protection scheme, it is needed to include a V DD -V SS clamp device such as an NMOS transistor in an input pad structure to provide discharge paths for all possible human-body model (HBM) test modes. While a large size for the clamp NMOS device is essential to prevent thermal device failure, a small-sized pn diode with a small holding voltage is utilized as the diode protection devices connected to an input pad of RF ICs to reduce the added parasitics to the input node. Some efforts have been made to optimize diode structures [4, 5], but the efforts for optimization seems insufficient. In [4], geometric parameters of CMOS shallow-trench-isolation (STI) diodes were investigated to optimize diode structures for high-speed RF applications based on 2-dimensional (2-D) simulations. The parameters for optimization included diode length, anode & cathode width, anode-to-cathode spacing, and STI depth to suggest guidelines in designing the diode protection device structure. In this study, however, the authors made a mistake not to include nearby p-type substrate contacts in the target device structure. In the prior study in [6], 2-D mixed-mode (device and circuit) simulations were utilized to figure out that an excessive lattice heating problem in the diode device

402 JIN-YOUNG CHOI : STRUCTURE OPTIMIZATION OF ESD DIODES FOR INPUT PROTECTION OF CMOS RF ICS connected to V DD bus in the input diode protection circuit can occur due to a trigger of parasitic pnp bipolar transistor involving the p-type substrate contacts. In this work, the same simulation setup in [6] is used to show that the problem can be solved by adopting a symmetrical cathode structure in the diode device. Based on the comparison study by varying the device structure, additional guidelines in designing the protection diodes connected to the V DD and V SS buses are also provided. For this purpose, the popular diode protection scheme is recalled, which can be implemented into input pad structures of CMOS RF ICs to provide protection against HBM and MM (Machine model) ESD events. We analyze and compare in detail discharge characteristics of the protection scheme for various discharge modes in input HBM tests. A 2-D device simulator, together with a circuit simulator, is utilized as a tool for the analysis. The analysis methodology utilizing a device simulator has been widely adopted with credibility [7, 8] since it provides valuable information relating mechanisms leading to device failure, which cannot be obtained by measurements only. In section II, we introduce the simulation setup used in [6] briefly for readers convenience to read the paper. We introduce the diode input protection scheme, and explain the main discharge path for each HBM test mode. We also introduce the equivalent circuit model for a CMOS chip equipped with the input protection devices. In section III, a modified diode structure is suggested to suppress the pnp bipolar transistor action with a proper explanation for the choice. We provide mixed-mode transient simulation results showing that the excessive lattice heating problem can be solved by adopting the recipe. Based on the simulation results, we figure out weak modes in real discharge tests, and present in-depth analysis results relating critical characteristics such as peak voltages developed across gate oxides in the input buffer and lattice heating inside the protection devices, which are the origins of ESD failures. In section IV, effects of additional structure changes are examined to suggest more guidelines for device design. Section V concludes the work. II. ESD PROTECTION SCHEME AND MIXED- MODE SIMULATION SETUP Fig. 1 shows the popular diode input protection scheme, which minimizes added parasitics to input nodes in CMOS RF ICs. In Fig. 1, a CMOS inverter is assumed as an input buffer. Since HBM tests for input pins should include all possible discharge modes, tests are performed for 5 modes defined below. 1) PS mode: +V ESD at an input pin with a V SS pin grounded 2) NS mode: -V ESD at an input pin with a V SS pin grounded 3) PD mode: +V ESD at an input pin with a V DD pin grounded 4) ND mode: -V ESD at an input pin with a V DD pin grounded 5) PTP mode: +V ESD at one input pin with another input pin grounded Fig. 2 shows main discharges path for each test mode in the diode protection scheme. In a PS mode, the forward-biased D 2 and a parasitic npn bipolar transistor in M 1 in series provides a main discharge path, and in an NS mode, the forward-biased D 1 provides it. In a PD mode, the forward-biased D 2 provides a main discharge path, and in an ND mode, an npn bipolar transistor in M 1 and the forward-biased D 1 in series provides it. In a PTP mode with +V ESD applied to the PAD 1 with the PAD 2 grounded, two forward-biased pn diodes D 2 and D 3 in series with an npn bipolar transistor in M 2 provides a M 1 n + n + p PAD D 2 D 1 Pad structure R mdd R line R mss V DD V SS Input buffer Fig. 1. Diode input protection scheme.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.3, JUNE, 2017 403 Fig. 3. Equivalent circuit of an input-pin HBM test situation. capacitances of an NMOS transistor and a PMOS Fig. 2. Main discharge path for each test mode. main discharge path. Since local lattice heating is proportional to a product of current density and electric field intensity, temperature-related problems in the protection devices can occur in the NMOS device rather than in the diode device since the holding voltage of the npn bipolar transistor in the NMOS device is much larger than the diode drop in the forward-biased diode. Therefore width of the diode devices can be small, but we should assign sufficient device width for the NMOS devices considering PS, ND, and PTP modes. Fig. 3 shows the equivalent circuit of an input HBM test situation in case of a PS mode or an NS mode. The portion indicated as Test environment in Fig. 3 is an equivalent circuit for test equipment connection. C ESD and R ESD represent a human capacitance and a human contact resistance, respectively. Values for other parasitic elements are described in [9]. V ESD is a HBM test voltage, and a switch S 1 charges C ESD and then a switch S 2 initiates discharge. By utilizing time-varying resistors for the switches, the switching times of S 1 and S 2 were set short as 0.15ns. In Fig. 3, M 1, D 1, and D 2 form a protection circuit at the input pad. A CMOS inverter is assumed as an input buffer inside a chip, which is modeled by a capacitive network. C ngate and C pgate represent gate-oxide transistor in the CMOS inverter, respectively. C ds represents an n-well/p-sub junction capacitance. The reason for choosing this simple model for the inverter is based on an intention to analyze oxide failure by monitoring voltages developed across the gate oxides in the input buffer. III. DISCHARGE CHARACTERISTICS WITH THE MODIFIED DEVICE STRUCTURE Using a 2-D device simulator ATLAS [10], mixedmode transient simulations utilizing the equivalent circuit in Fig. 3 are performed. The conventional NMOS protection device shown in Fig. 2 in [6] are used as the protection device M 1 in Fig. 3. The diode device in Fig. 4 is used as the protection device D 1 in Fig. 3. Notice that the diode device in Fig. 4 was commonly used as the protection devices D 1 and D 2 in [6]. We will call this diode as the reference diode hereinafter. In this section, however, the device structure for D 2 is changed. We know from the work in [6] that, when the reference diode in Fig. 4 is used as the protection device D 2 in a PS mode, an excessive lattice heating at the p + - subr junction inside D 2 is caused by the parasitic pnp bipolar transistor action formed by the forward-biased p + anode/n-well junction in series with the reverse-biased n- well/p + -subr junction. Here the p + anode, the n well, and the p + -subr junction act as an emitter, a base, and a collector, respectively. Since the p + -subr junction is closer to the p + anode, much larger bipolar current flows to the p + -subr junction rather than to the p + -subl junction

404 JIN-YOUNG CHOI : STRUCTURE OPTIMIZATION OF ESD DIODES FOR INPUT PROTECTION OF CMOS RF ICS Fig. 4. Cross section of the reference diode. From the DC simulation results using ATLAS, it was confirmed that the breakdown voltage, the snapback voltage, and the holding voltage of the NMOS device are 9.3V, 9.4V, and 4.6V, respectively. It was also confirmed that the forward diode drop of the modified diode is 0.66V when the diode current is 0.2μA/μm, and the reverse breakdown voltage is about 11.6V, which are not much different from those for the reference diode. When a mixed-mode simulation is performed, active protection devices are solved by device and circuit simulators simultaneously. Notice that up to 6 active protection devices are included in a mixed-mode simulation, which correspond to the PTP-mode simulation in Fig. 2. For all the mixed-mode transient simulations performed for 5 test modes, V ESD =±2000V was assumed. Widths of the protection devices were adjusted to maintain peak lattice temperature inside all the protection devices below 500 K for all the mixed-mode simulations, resulting 250μm, 15μm, and 15μm for M 1, D 1, and D 2 in Fig. 3, respectively. We note that the device widths were chosen tentatively based on the experience in our previous study in [9]. 1. Voltages Across the Gate Oxides Fig. 5. Cross section of the two-cathode diode structure for D 2. resulting the excessive lattice heating at the p + -subr junction. To solve the excessive lattice heating problem at the p + -subr junction in D 2, we devised to add one more cathode contact at the right-hand side of the p + anode to get a symmetrical structure shown in Fig. 5. We expected lattice heating at the p + -subr junction to be suppressed by allowing the pnp bipolar current to flow equally to the p + -subl and p + -subr junctions resulting lower current densities at the junctions. As an example of the mixed-mode simulation results, Fig. 6 shows variations of the voltages developed on C ngate and C pgate in Fig. 3 as a function of time in a PS mode, which correspond to the voltages developed across the gate oxides of the NMOS and PMOS transistors in the input buffer. The pad voltage, which is not shown in Fig. 6, is almost same with the voltage developed on C ngate. We note here that current variation through the main discharge path formed by D 2 and M 1 in series is very similar to the one provided in Fig. 13 in [9] with peak current of 1.3A. By monitoring the simulation results in detail, we confirmed that the forward-biased diode in D 2 is triggered when the pad voltage (the voltage on C ngate ) in the early stage of discharge increases to 12.9V, which is 0.82ns after S 2 in Fig. 3 is closed. At this moment, the voltage developed across D 2 in Fig. 3 is 7.0V. We also confirmed that the npn bipolar transistor in M 1 in Fig. 3

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.3, JUNE, 2017 405 Table 1. Weak-mode peak voltages developed across the gate oxides in the later stage of discharge Weak mode Peak voltage (V) C ngate C pgate Time (ns) PS 10.65 470 ND 10.65 500 PTP 10.65 10.65 430 Fig. 6. Variations of voltages on C ngate and C pgate in a PS mode. is triggered somewhat earlier when the voltage across M 1 increases to 10.9V, which is 0.74ns after S 2 is closed. Due to this trigger time difference, the voltage (12.9V) smaller than the sum of the bipolar trigger voltage (10.9V) and the diode trigger voltage (7.0V) appears across C ngate in the early stage of discharge in Fig. 6. After that, main discharge through the forward-biased diode in D 2 and the npn bipolar transistor in M 1 in series proceeds when the pad voltage drops to a sum of the forward diode drop and the bipolar holding voltage, which is about 7V as shown in Fig. 6. This voltage decreases as the discharge current decreases with time. We can see that the pad voltage increases again and reaches to 10.6V at about 0.46 μs when M 1 conducts in a breakdown mode since the drain current of M 1 is reduced below the holding current for the bipolar transistor action. From the simulation result, it is confirmed that the peak voltage 10.65V corresponds to a sum of the forward diode drop in D 2 (1.15V) and the breakdown voltage of M 1 (9.5V). In Fig. 6, the voltage developed on C pgate is maintained low all the time after the forward diode in D 2 is triggered since it is equal to the forward diode drop in D 2. Depending on test modes, the peak voltages across the gate oxides in the early stage of discharge appear at C ngate or C pgate. The peak voltages could be regarded as excessive; however, durations of the peak voltages are very short. We confirmed that, for example, the durations for which the voltages exceed 10V are at most 0.3ns. Therefore it may be inferred that the gate oxides won t be damaged in the early stage of discharge [11]. Depending on test modes, the 2 nd peak voltages across the gate oxides in the later stage of discharge also appears at C ngate or C pgate. Differently from the peak voltages in the early stage of discharge, the 2 nd peak voltages can damage the gate oxides since they last for long time as shown in Fig. 6. If we define the test modes, which produce utmost peak voltages in the later stage of discharge in the mixedmode transient simulations performed for 5 test modes as weak modes, the results can be summarized as shown in Table 1. As shown in Table 1, the same voltages (10.65V) are developed on C ngate in a PS mode and on C pgate in an ND mode, which correspond to a sum of the breakdown voltage of M 1 and the forward diode drop in D 2 or D 1. In a PTP mode, 10.65V is also developed both on C ngate and C pgate, which corresponds to a sum of the breakdown voltage of M 2 and the forward diode drop in D 2 or D 3, which can be easily explained from Fig. 2 and 3. When judging from the peak voltages developed across the gate oxides in the later stage of discharge, weakest modes are PS, ND, and PTP modes, and therefore the NMOS and PMOS gate oxides in the input buffer are vulnerable in the same extent. 2. Location of Peak Temperature Fig. 7 shows variation of overall peak temperature inside the protection devices including M 1, D 1, and D 2 in a PS mode. The temperature variation when using the reference diode in Fig. 4 for D 2, which was previously given in [6], is also shown for comparison. When using the two-cathode diode in Fig. 5 for D 2, overall peak temperature increases up to 484 K at 34ns, and shows a 2nd peak (407 K) at 450ns, which is a lot

406 JIN-YOUNG CHOI : STRUCTURE OPTIMIZATION OF ESD DIODES FOR INPUT PROTECTION OF CMOS RF ICS Fig. 7. Overall peak temperature variation in a PS mode. reduced when compared to the result when using the reference diode. We confirmed that the overall peak temperature appears at the n+ drain junction in M1, not inside D2 this time, differently from the result when using the reference diode in [6]. Peak temperature inside M1 is 484 K at 34ns, which is not much different from that in [6]. We also confirmed that peak temperatures inside D2 appear both at the p+-subr and p+-subl junctions, and temperature peaks only up to 407 K at 450ns, which is a lot reduced compared to that (893 K at 36ns) when using the reference diode. Lattice temperature distributions inside D2 at these two situations are given in Fig. 8 and 9 to show the characteristic change when adopting the suggested two-cathode diode. While the peak temperature (893 K at 36ns) occurs at the p+-subr junction in the reference diode, the much lowered peak temperature (407 K at 450ns) occurs equally at the p+subl and p+-subr junctions in the two-cathode diode. The excessive lattice heating problem has been solved by adopting the suggested diode structure as expected. Notice that lattice heating inside D2 is suppressed below 407 K, which is much lower than 484 K inside M1. To confirm whether the pnp bipolar transistor current flows equally to the p+-subl and p+-subr junctions in the two-cathode diode as expected, terminal voltage and current values of D2 at 450ns are summarized in Table 2. Fig. 8. Lattice temperature distribution inside D2 at 36ns when using the reference diode. The peak temperature (893 K) appears at the p+-subr junction. Fig. 9. Lattice temperature distribution inside D2 at 450ns when using the two-cathode diode. The peak temperature (407 K) appears equally at the p+-subl and p+-subr junctions.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.3, JUNE, 2017 407 Table 2. Terminal voltages and currents of D 2 at 450 ns Terminal Voltage (V) Current (ma) Percentage of current (%) p + anode 10.525 63.90 100 n + cathode right 9.440 26.10 40.85 n + cathode left 9.440 26.10 40.85 p + subr 0 26.10 9.04 p + subl 0 5.777 9.04 M 1 drain 9.440 52.19 81.67 Table 3. Peak temperature locations and times Test mode PS Peak temp. ( K) 407 484 Peak temperature Location p + -subr/subl junctions in D 2 Gate-side drain junction in M 1 Time (ns) NS 432 n + -cathode junctions in D 1 35 PD 377 n + -cathode junctions in D 2 52 ND 495 Gate-side drain junction in M 1 30 PTP 430 429 396 n + -cathode junctions in D 3 p + -subr/subl junctions in D 2 Gate-side drain junction in M 2 450 34 40 140 130 We note that in the simulation using the reference diode in [6], 30.44% of the p + -anode current at 430ns flows to the p + -subr and p + -subl junctions. 2.4(15.73mA/ 6.52mA) times large pnp bipolar current flows to the p + - subr junction compared to that to the p + -subl junction. We can say that the pnp bipolar action is suppressed pretty much by making the diode current to flow more easily through the two n + cathodes. Peak temperature and its location with the corresponding discharge time for each test mode are summarized in Table 3. In Table 3, we can see that peak temperatures inside the protection devices are controlled below 500 K for all 5 test modes, which is the target maximum temperature in this work. We recall that, in the prior study [6] using the reference diode for D 2, lattice temperature at the p + -subr junction in D 2 peaks up to 1500 K at 5.2ns in the PTP mode simulation, which is the maximum temperature limit set in the simulation. By using the modified diode in Fig. 5 for D 2, the severe lattice heating problem in the PTP mode is also solved as shown in Table 3. Notice from the data summarized in Table 3 that utmost peak temperatures inside the 15μm-width diode devices are 432 K and 429 K for D 1 (NS mode) and D 2 (PTP mode), respectively, while that inside the 250μmwidth NMOS device is 495 K (ND mode). Therefore we can say that there is a small room for reducing the diode device sizes even below 15μm. In this section, we conclude that the symmetrical n + - cathode junctions in the diode device connected to a V DD bus is very effective in suppressing the excessive lattice heating problem caused by the parasitic pnp bipolar transistor action. IV. ADDITIONAL STRUCTURE OPTIMIZATION We note here that we will call the device structure used for D 1 and D 2 by the D 1 device and the D 2 device, respectively hereinafter. 1. When using the D 1 Device without an n Well To find a way to further optimize device structure for the diode protection devices, modification of the reference diode structure for D 1 is first considered. Notice that the n well in Fig. 4 is not needed for the D 1 device since the n + cathode is connected to the input pad and the p + anode is connected to the V SS bus together with the p + -subr/p + -subl contacts. Therefore we simply removed the n well in the D 1 device in Fig. 4 without changing the other structure, and run the same mixedmode simulation set. From the simulation results, we confirmed that peak temperature inside D 1 is reduced by 12 K, 14 K, and 13 K for the NS, ND, and PTP mode, respectively when compared with the results in Section III. Lattice heating seems reduced by virtue of more uniform current flows. We confirmed that lattice heating in other protection devices are not worsened at all. We also confirmed that there are little change in utmost peak voltages developed on C ngate and C pgate when compared with the results in Section III with this structure modification. Removing the n well inside the D 1 device is preferable in CMOS RF circuit design since it has an effect to reduce the junction capacitance added to the input node. Therefore it is recommended not to include the n well for the D 1 device. 2. When using the D 2 Device with Larger p + -subr and p + -subl Junctions To further optimize device structure for the diode

408 JIN-YOUNG CHOI : STRUCTURE OPTIMIZATION OF ESD DIODES FOR INPUT PROTECTION OF CMOS RF ICS protection devices, the effect of enlarging the p+-subr and p+-subl junction lengths in the D2 device to lower the current density at the junctions is next examined. We enlarged the junction length to 2 times of that (0.8μm) in Fig. 5, and run the same simulation set. We note that the D1 device without an n well was used in the simulations. From the simulation results, we confirmed that there are little change in utmost peak voltages developed on Cngate and Cpgate when compared with the results in Section IV-1, but peak temp characteristic changes are noticeable. When compared with the results in Section IV-1, while the current to the p+-subr and p+-subl junctions inside the D2 device are enhanced a little bit probably due to broader current flow, peak temperature at the p+-subr and p+-subl junctions is reduced by 13 K and 28 K in PS mode and PTP mode, respectively. Assigning larger junction area for the p+-sub junctions is beneficial as expected. We note that enlarging the p+-sub junction length in the D2 device will not increase the parasitics added to the input node since only the p+ anode is connected to it. 3. When using the D2 Device with a Larger Space between the n Well and the p+-subr/p+-subl Junctions To further optimize device structure for the diode protection devices, the effect of enlarging the spacing between the n well and the p+-subr/p+-subl junctions in the D2 device to suppress the pnp transistor action is next examined. We enlarged the spacing by 0.8μm from that (1.9μm) in Fig. 5 without changing the p+-subr and p+subl junction lengths, and run the same simulation set. We note that the D1 device without an n well was again used in the simulations. We confirmed that there are little change in utmost peak voltages developed on Cngate and Cpgate, but peak temperature characteristics changes are even more noticeable. When compared with the results in Section IV-1, the currents to the p+-subr and p+-subl junctions inside the D2 device are reduced by 20% by suppressing the pnp bipolar transistor action, and consequently peak temperature at the p+-subr and p+-subl junctions is reduced by 25 K and 41 K in the PS mode and PTP modes, respectively. Therefore we can say that locating Fig. 10. Lattice temperature distribution inside D2 at 460ns when using the two-cathode diode with a larger space between the n well and the p+-subr/p+-subl junctions. The lowered peak temperature (382 K) appears equally at the p+-subl and p+-subr junctions. the p+-sub junctions farther from the n well is important. Lattice temperature distributions inside D2 at its temperature peaking in a PS mode when using a D2 device with a larger space in this section is given in Fig. 10 to show an example of the characteristic improvements explained in Section IV. While the temperature distribution is similar to that when using the structure in Fig. 9, the peak temperature is reduced by 25 K with only a 0.8μm increase in the spacing. We note that enlarging the space between the n well and the p+-sub junctions in the D2 device will not increase the parasitics added to the input node either since only the p+ anode is connected to it. V. CONCLUSIONS We showed that the excessive lattice heating problem due to parasitic pnp transistor action in the diode ESD protection device connected to a VDD bus in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.3, JUNE, 2017 409 cathode structure. To explain how the recipe works, we constructed an equivalent circuit for input HBM test environment of a CMOS chip equipped with the diode protection circuit, and executed mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempted an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the V DD and V SS buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements. The results of the comparison study by varying the device structures to avoid the problem are certainly dependable since they are based on the characteristic changes not on the absolute numerical values. Contributions of this work can be summarized as follows. 1) We showed that locating the n + cathode junctions symmetrically around the p + anode junction inside the diode device connected to a V DD bus is essential to suppress the pnp bipolar transistor action. 2) We provided two additional important design guidelines for structure design of the diode device connected to a V DD bus to reduce lattice heating inside the device. 3) We also provided design guidelines for structure design of the diode device connected to a V SS bus to reduce the parasitics added to the input node. ACKNOWLEDGMENTS This work was supported by 2015 Hongik University Research Fund, and in part by the International Science and Business Belt Program through the Ministry of Science, ICT and Future Planning(2016K000280). REFERENCES [1] P. Leroux and M. Steyaert,. High-performance 5.2GHz LNA with On-chip Inductor to Provide ESD Protection, Electronics Letters, vol. 37, pp. 467-469, Mar. 2001. [2] C.-T. Yeh, M.-D. Ker, and Y. C. Liang, Optimization of Layout Style of ESD Protection Diode for Radio-frequency Front-end and Highspeed I/O Interface Circuits, IEEE Trans. Device and Materials Reliability, vol. 10, pp. 238-246, June 2010. [3] M.-T. Yang et al., BSIM4-based Lateral Diode Model for LNA Co-designed with ESD Protection Circuit, 11th Int. Symp. on Quality Electronic Design, 22-24, Mar. 2010, pp. 87-91. [4] T. Au and M. Syrzycki, Investigation of STI Diodes as Electrostatic Discharge (ESD) Protection Devices in Deep Submicron (DSM) CMOS Process, 26th IEEE CCECE, 5-8, May 2013, pp. 1-5. [5] K. Bhatia, N. Jack, and E. Rosenbaum, Layout Optimization of ESD Protection Diodes for Highfrequency I/Os, IEEE Trans. Device and Materials Reliability, vol. 9, no. 3, 465-475, Sept. 2009. [6] J. Y. Choi,. On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device, Circuits and Systems, vol. 7, pp. 2286-2295, July 2016. [7] H. Feng, et al., "A mixed-mode ESD Protection Circuit Simulation-design methodology," IEEE J. Soilid-State Circuits, vol. 38, pp. 995-1006, June 2003. [8] B. Fankhauser, and B. Deutschmann, Using Device Simulations to Optimize ESD Protection Circuits, IEEE EMC Symp., 9-13, Aug. 2004, pp.963-968. [9] J. Y. Choi, A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode, Communications and Network, vol. 2, pp. 11-25, Feb. 2010. [10] ATLAS II Framework, Version 5.10.2.R, Silvaco International, 2005. [11] Z. H. Liu, et al., A Comparative Study of the Effect of Dynamic Stressing on High-field Endurance and Stability of Reoxidized-nitrided, Fluorinated and Conventional Oxides, IEEE IEDM, Tech. Digest, 8-11, Dec. 1991, pp. 723-726.

410 JIN-YOUNG CHOI : STRUCTURE OPTIMIZATION OF ESD DIODES FOR INPUT PROTECTION OF CMOS RF ICS Jin-Young Choi was born in Seoul, Korea in 1956. He received the B.S. degree in electrical engineering from the Seoul National University, Korea, in 1979, and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida, USA, in 1986 and 1991, respectively. In 1992, he joined the Hongik University, Sejong, Korea, where he is now a professor. His recent research interests include the highfrequency modeling of CMOS devices and analysis & design of ESD protection circuits for RF ICs.