SINGLE PHASE 21 LEVEL ASYMMETRIC CASCADED MULTILEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES AND DC SOURCES M.M. Ganapathi 1 B.Vaikundaselvan 2 S. Kalpana 3 1 (Dept. of EEE (M.E (PED)), Kathir College of Engineering,Coimbatore, India, ganapathigana@gmail.com) 2 (Prof Dept. EEE, Kathir College of Engineering, Coimbatore, India, eeehod.kce@gmail.com) 3 (Asst Prof Dept. of EEE, Kathir College of Engineering, Coimbatore, India, kalpanasv.agl@gmail.com) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Abstract- Multilevel inverter technology has emerged as a very important alternative in the field of medium and high power industrial drive applications. The emergence of multilevel inverters has been increasing since three decades. These new types of converters are suitable for high voltage and high power application due to their ability to synthesize waveforms with better harmonic spectrum. Several multilevel converter topologies have been developed; i) diode clamped, ii) flying capacitors, and iii) cascaded or H-bridge. Cascade Multilevel Inverter (CMI) is one of the productive topology from multilevel family. By increasing the number of output voltage levels in multilevel inverter the Total Harmonic Distortion (THD) can be minimized. This project proposes a new topology of 21 level asymmetric cascaded multilevel inverter with 11 unidirectional switches and 3 diodes and 4 DC voltages sources. Several Pulse Width Modulation techniques are available, among them Level shifting SPWM techniques such as PO, POD and Space Vector PWM are used and comparison is shown on the basis of THDs obtained. MATLAB/ SIMULINK software is used for simulation -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1. INTRODUCTION Power electronic converters, especially dc/ac PWM inverters have been extending their range of use in industry because they provide reduced energy consumption, better system efficiency, improved quality of product, good maintenance, and so on. For a medium voltage grid, it is troublesome to connect only one power semiconductor switches directly. As a result, a multilevel power converter structure has been introduced as an alternative in high power and medium voltage situations such as laminators, mills, conveyors, pumps, fans, blowers, compressors, and so on. As a cost effective solution, multilevel converter not only achieves high power ratings, but also enables the use of low power application in renewable energy sources such as photovoltaic, wind, and fuel cells which can be easily interfaced to a multilevel converter system for a high power application. The most common initial application of multilevel converters has been in traction, both in locomotives and trackside static converters. More recent applications have been for power system converters for VAR compensation and stability enhancement, active filtering, high-voltage motor drive, highvoltage dc transmission and most recently for medium voltage induction motor variable speed drives. Many multilevel converter applications focus on industrial medium-voltage motor drives, utility interface for renewable energy systems, flexible AC transmission system (FACTS), and traction drive systems. The inverters in such application areas as stated above should be able to handle high voltage and large power. For this reason, two-level high-voltage and large-power inverters have been designed with series connection of switching power devices such as gate-turn-off thyristors (GTOs), integrated gate commutated transistors (IGCTs), and integrated gate bipolar transistors(igbts), because the series connection allows reaching much higher voltages. However, the series connection of switching power devices has big problems, namely, non-equal distribution of applied device voltage across series-connected devices that may make the applied voltage of individual devices much higher than blocking voltage of the devices during transient and steady-state switching operation of devices. As alternatives to effectively solve the above-mentioned problems, several circuit topologies of multilevel inverter and converter have been researched and utilized. The output voltage of the multilevel inverter has many levels synthesized from several DC voltage sources. The quality of the output voltage is improved as the number of voltage levels increases, so the quantity of output filters can be decreased. The concept of multilevel converters has been introduced since 1975. The cascade multilevel inverter was first proposed in 1975. Separate DC-sourced full-bridge cells are placed in series to synthesize a staircase AC output voltage. The term multilevel began with the three-level converter. Subsequently, several multilevel converter topologies have been developed. In 1981, diode-clamped multilevel inverter also called the Neutral-Point Clamped (NPC) inverter schemes were proposed. In 1992, capacitor-clamped (or flying capacitor) Volume: 03 Issue: 02 2016 www.researchscript.com 37
multilevel inverters, and in 1996, cascaded multilevel inverters were proposed. Although the cascade multilevel inverter was invented earlier, its application did not prevail until the mid-1990s. The advantages of cascade multilevel inverters were prominent for motor drives and utility applications. The cascade inverter has drawn great interest due to the great demand of medium-voltage high-power inverters. The cascade inverter is also used in regenerative-type motor drive applications. Recently, some new topologies of multilevel inverters have emerged. These multilevel inverters can extend rated inverter voltage and power by increasing the number of voltage levels. A multilevel converter can be implemented in many different ways. The simplest techniques involve the parallel or series connection of conventional converters to form the multilevel waveforms. More complex structures effectively insert converters within converters. The elementary concept of a multilevel converter to achieve higher power is to use a series of power semiconductor switches with several lower voltage dc sources to perform the power conversion by synthesizing a staircase voltage waveform. Capacitors, batteries, and renewable energy voltage sources can be used as the multiple dc voltage sources. A multilevel converter has several advantages over a conventional two-level converter that uses high switching frequency pulse width modulation (PWM). The attractive features of a multilevel converter can be briefly summarized as follows. 1. Staircase waveform quality: Multilevel converters not only can generate the output voltages with very low distortion, but also can reduce the dv/dt stresses; therefore electromagnetic compatibility (EMC) problems can be reduced. 2. Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage; therefore, the stress in the bearings of a motor connected to a multilevel motor drive can be reduced. Furthermore, CM voltage can be eliminated by using advanced modulation strategies. 3. Input current: Multilevel converters can draw input current with low distortion. 4. Switching frequency: Multilevel converters can operate at both fundamental switching frequency and high switching frequency PWM. It should be noted that lower switching frequency usually means lower switching loss and higher efficiency. Multilevel converters do have some disadvantages. One particular disadvantage is the greater number of power semiconductor switches needed. Although lower voltage rated switches can be utilized in a multilevel converter, each switch requires a related gate drive circuit. PWM technique. But after using SPWM techniques THD of the output can be reduced further. Three techniques of SPWM are used here and compared among themselves, to figure out the technique which gives least THD. 2. OPERATING PRINCIPLE OF THE PROPOSED CONVERTER This project proposes a new asymmetric topology for 21- level voltage output with reduced number of switches and DC sources. The THD level is reduced by using few PWM techniques namely PD, POD and Space vector modulation PWM technique. These techniques are compared among themselves, to figure out the technique which gives least THD. Few advantages of proposed system are as follows: 1) Asymmetric Multilevel Inverter with the same number of switches and DC voltage sources, the number of output voltage level obtained is more, when compared to the symmetrical topology 2) Space Vector PWM (SVPWM) offers important advantages such as a low harmonic profile, higher DC bus utilization and a wide linear operating region. DC SOURCE 21 LEVEL ASYMMETRIC MLI PWM Fig.1. Basic Block Diagram of Proposed Multilevel Inverter A. Asymmetric Cascaded Multilevel Inverter The proposed topology has been successful in significantly reducing the switch count and number of DC voltage sources. It consists of four asymmetrical DC voltage sources for 21 levels. Increments in the DC voltage sources are in the fashion n, 2n, 3n, 4n... Where n = lowest DC voltage source magnitude. Proposed topology follows one relation between number of output voltage levels and number of DC sources. LOA D This paper proposes new asymmetric topology for 21- level voltage output with reduced number of switches. The proposed topology has been also analyzed without using any Volume: 03 Issue: 02 2016 www.researchscript.com 38
Fig. 2. Proposed topology B. SWITCHING STATES OF PROPOSED TOPOLOGY The following table shows the switching sequence given to the proposed topology to generate 21 level voltage output. Table 1. Switching states of Proposed Technology Level SW1 SW2 SW3 SW4 SW5 SW6 SW7 0 OFF OFF OFF OFF OFF OFF OFF ±10 ON OFF OFF OFF OFF OFF OFF ±20 OFF OFF ON OFF OFF OFF OFF ±30 OFF OFF OFF OFF ON OFF OFF ±40 OFF OFF OFF OFF OFF OFF ON ±50 ON OFF OFF OFF OFF ON OFF ±60 OFF OFF ON OFF OFF ON OFF ±70 OFF OFF OFF OFF ON ON OFF ±80 ON OFF OFF ON OFF ON OFF ±90 OFF OFF ON ON OFF ON OFF ±100 ON ON OFF ON OFF ON OFF C. PULSE WIDTH MODULATION TECHNOLOGY Mainly the power electronic converters are operated in the switched mode. Which means the switches within the converter are always in either one of the two states - turned off (no current flows), or turned on (saturated with only a small voltage drop across the switch). Any operation in the linear region, other than for the unavoidable transition from conducting to non-conducting, incurs an undesirable loss of efficiency and an unbearable rise in switch power dissipation. To control the flow of power in the converter, the switches alternate between these two states (i.e. on and off). This happens rapidly enough that the inductors and capacitors at the input and output nodes of the converter average or filter the switched signal. The switched component is attenuated and the desired DC or low frequency AC component is retained. This process is called Pulse Width Modulation (PWM), since the desired average value is controlled by modulating the width of the pulses. D. CASCADED H-BRIDGE MULTILEVEL INVERTER Cascaded H-Bridge (CHB) configuration has recently become very popular in high-power AC supplies and adjustable-speed drive applications. A cascade multilevel inverter consists of a series of H-bridge (single-phase full bridge) inverter units in each of its three phases. Each H- bridge unit has its own dc source. Each SDC (separate D.C. source) is associated with a single-phase full-bridge inverter. The ac terminal voltages of different level inverters are connected in series. Through different combinations of the four switches, S1-S4, each converter level can generate three different voltage outputs, +Vdc, -Vdc and zero. The AC outputs of different full- bridge converters in the same phase are connected in series such that the synthesized voltage waveform is the sum of the individual converter outputs. In this topology, the number of output-phase voltage levels is defined by m= 2N+1, where N is the number of DC sources. A cascaded multilevel inverter is discussed to eliminate the excessively large number of 1) bulky transformers required by conventional multi pulse inverters, 2) clamping diodes required by multilevel diodeclamped inverters, and 3) flying capacitors required by multilevel flyingcapacitor inverters. Also, it has the following features: 1) It is much more suitable to high-voltage, high-power applications than the conventional inverters. 2) It switches each device only once per line cycle and generates a multistep staircase voltage waveform approaching a pure sinusoidal output voltage by increasing the number of levels. 3) Since the inverter structure itself consists of a cascade connection of many single-phase, fullbridge inverter (FBI) units and each bridge is fed with a separate DC source, it does not require voltage balance (sharing) circuits or voltage matching of the switching devices. 4) Packaging layout is much easier because of the simplicity of structure and lower component count. 5) Soft-switching can be used in this structure to avoid bulky and lossy resistor-capacitor-diode E. LEVEL SHIFTED PWM (LS-PWM) An m-level CHB inverter using level-shifted multicarrier modulation scheme requires (m-1) triangular carriers, all having the same frequency and amplitude. The (m-1) triangular carriers are vertically disposed such that the bands they occupy are contiguous. (i) Phase disposition (PD). (ii) Phase opposition disposition (POD). (iii) Alternate phase opposition disposition (APOD). Among these PWM methods, Phase disposition and Phase Opposition disposition methods are used. Phase Disposition (PD) Method - The phase disposition method has an equal number of carrier signals above and below the zero reference and are in phase with the same Volume: 03 Issue: 02 2016 www.researchscript.com 39
amplitude and frequency. transistor Fig. 5. Voltage Space Vector and its components in (d, q). Fig. 3. PD PWM Phase Opposition Disposition (POD) Method - All carrier signals above the zero reference are in the same phase but the carrier signals below the zero reference are phase shifted by 180 degrees. VV dd = VV aaaa VV bbbb cos 60 VV CCCC cos 60 = VV aaaa 1 2 VV bbbb 1 2 VV CCCC VV qq = 0 + VV bbbb cos 30 VV CCCC cos 30 = VV aaaa + 3 2 VV bbbb 3 2 VV CCCC VV dd VVqq = 2 1 1 2 3 3 0 2 1 VV 2 aaaa 3 VV bbbb VV CCCC 2 VV rrrrrr = VV 2 2 dd + VV qq α = tan 1 VV qq = ωss tt = 2ππff VV ss tt dd Where, ff ss = fundamental frequency Fig. 4. POD PWM F. SPACE VECTOR PULSE WIDTH MODUALTION Space vector modulation (SVM) is based on vector selection in the q-d stationary reference frame. Space vector Pulse width modulation treats the sinusoidal voltage as a constant amplitude vector rotating at constant frequency. Step -1 Determine Vd, Vq, Vref, and angle (α) Step -2 Determine time duration T1, T2, T0 Step -3 Determine the switching time of each If angle is greater than zero and less than the value (1*(360/42)), Sector 1 is selected and corresponding switching pattern is activated. For the next level, If the angle is greater than (1*(360/42)) and less than (2*(360/42)), Sector 2 is selected and corresponding switching pattern is activated and so on. In general, Sector n is selected if the angle α follows the relation, (nn 1) 360 360 < αα < (nn) 42 42 Volume: 03 Issue: 02 2016 www.researchscript.com 40
3. SIMULATION RESULTS Fig..8. Simulation result of Pulses of Switches in PD PWM Fig. 5. Simulation result of 21 level multilevel inverter using PD PWM Fig. 9.. Simulation result of Pulses of Switches in POD PWM Fig. 6. Simulation result of 21 level multilevel inverter using POD PWM Fig. 10. THD using PD PWM Fig. 7. Simulation result of 21 level multilevel inverter using SVPWM Volume: 03 Issue: 02 2016 www.researchscript.com 41
also the complexity of the circuit will reduce. From the FFT analysis, it is found that PD PWM and POD PWM techniques give least THD. It is observed that even after the reduction in switches and sources, the desired output is obtained. Table 2. THD (%) of Output Voltage of Proposed Topology S.NO PWM Technique THD (%) 1 PD 5.98 2 POD 5.98 3 SVPWM 6.73 REFERENCES Fig. 11. THD using POD PWM Fig. 12. THD using SVPWM 4. CONCLUSION In this project, a new topology for 21 levels is proposed with reduced number of switches and DC sources. The Proposed circuit is validated on MATLAB/Simulink platform. The simulation of the 21 level asymmetric cascaded multilevel inverter is successfully done using Space vector, Phase disposition and Phase Opposition disposition pulse width modulation techniques. Thus, this new circuit will require lesser hardware space, lesser cost; [1] Jannu Ramu, S.J.V. Prakash, K. Satya Srinivasu, R.N.D. Pattabhi Ram, M. Vishnu Prasad and Md. Mazhar Hussain, Comparison Between Symmetrical And Asymmetrical Single Phase Seven Level Cascade H-Bridge Multilevel Inverter With PWM Topology, International Journal of Multidisciplinary Sciences and Engineering, Vol. 3, no. 4, April 2012. [2] R.Karthikeyan, Dr.S.Chenthur Pandian, An Efficient Multilevel Inverter System For Reducing THD With Space Vector Modulation, International Journal of Computer Applications (0975 8887),Volume 23 No.2, June 2011. [3] Xiaodong Yang, Chonglin Wang, Liping Shi,Zhenglong Xia, Generalized Space Vector Pulse Width Modulation Technique For Cascaded Multilevel Inverters, International Journal of Control and Automation, Vol.7, No.1 (2014), pp.11-26 [4] Balamurugan M.,Gnana Prakash M.,Umashankar S., A New Seven Level Symmetric Inverter With Reduced Number Of Switches And Dc Sources, Advances in Electrical Engineering (ICAEE), 2014 International Conference. [5] Elyas Zamiri.,Sajjad Hamkari.,Ebrahim Babaei., A New Cascaded Multilevel Inverter Structure With Less Number Of Switches, 5th Power Electronics, Drive systems and Technologies Conference, 2014. [6] Ramirez, F.A.,Arjona, M.A., A Space Vector Modulation Algorithm For A Grid-Connected Single-Phase Seven Level Inverter, Power Electronics, Machines and Drives (PEMD 2014), 7th IET International Conference,2014. [7] Draxe, K.P.,Ranjana, M.S.B., Pandav, K.M., A Cascaded Asymmetric Multilevel Inverter With Minimum Number Of Switches For Solar Applications, Power and Energy Systems Conference:Towards Sustainable Energy, 2014. [8] Bhuvaneswari V, HariKumar M.E, ShakilAhmed A, Vinoth R, Ajith.B.Singh, Multicarrier Sinusoidal PWM Technique Based Analysis of Asymmetrical and Symmetrical 3Ф Cascaded MLI, International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 2, February 2014. Volume: 03 Issue: 02 2016 www.researchscript.com 42