30 CHAPTER 2 PHASE SHIFTED SERIES RESONANT DC TO DC CONVERTER 2.1 INTRODUCTION This chapter introduces the phase shifted series resonant converter (PSRC). Operation of the circuit is explained. Design procedure is presented. Simulation and experimental results are presented to support the design procedure. Phase shifted series resonant converter is described in section 2.2. Principle of operation is explained in section 2.3.Design procedure and factors affecting ZVS are explained in section 2.4. Simulation and experimental results are presented in section 2.5 and 2.6 respectively. 2.2 PHASE SHIFTED SERIES RESONANT CONVERTER The schematic diagram of the PSRC is shown in Figure 2.1. The basic H- bridge converter is modified by introducing soft-switching to the converter. The main components of the converter are two switching devices MOSFETs (S 1 and S 3, S 2 and S 4 ) in each leg of the H-bridge. The converter includes a resonant tank comprising a series inductor L r and series capacitor C r. A transformer is used to step down the voltage. The output rectifier consists of four diodes D 1 -D 4.
31 The control strategy of the converter is the switching devices MOSFETs, (S 1 and S 3, S 2 and S 4 ) in each leg of the converter conduct alternately in a switching cycle. It is assumed that the converter is under steady state operation and the output capacitor C H is large enough to be considered as a voltage source. The converter has four operation modes during one switching period. Figure 2.1 Circuit of the PSRC 2.3 OPERATING PRINCIPLE Phase shifted series resonant converter is shown in Figure 2.1. The operation of the circuit is divided in to four modes. Figure 2.2 Operation principle waveform of PSRC
32 Mode-1[t 0,t 1 ] The MOSFETs S 1 and S 4 are turned on. In steady state the output capacitor C H is charged. The current in the input side flows through S 1, primary, S 4 and back to the source. In the secondary side the diodes D 1 and D 4 conduct and the energy is transferred to the output capacitor. Mode-2 [t 1,t 2 ] The pulse to S 4 is withdrawn and the driving pulse is given to S 3 along with S 1.The charging started in the primary, circulates current through the MOSFETs S 1 and S 3.D 1 and D 4 continues to conduct in the secondary side. Mode-3 [t 2,t 3 ] The pulse to S 1 is withdrawn and pulse is applied to S 2 along with S 3.The diodes D 1 and D 4 continue to conduct due to the energy in the filter inductance. The diodes D 2 and D 3 conduct due to the forward bias given by the secondary of the transformer. This is called period of overlap. D 1 and D 4 gets turned off by the end of this mode. Mode-4 [t 3,t 4 ] The pulse to S 3 is withdrawn and pulse is applied to S 4.The energy in the primary circulates current through the devices S 2 and S 4. Diodes D 2 and D 3 continue to conduct. 2.4 DESIGN PROCEDURE The series capacitor functioning with the series inductor provides a resonant frequency ƒ r.
33 f r 2 1 L C r r (2.1) The switching frequency ƒ s of PSRC is always chosen to be close to the resonant frequency ƒ r, defined by the resonant inductor L r and resonant capacitor C r to make the resonant current waveform be quite sinusoidal. When the operating frequency ƒ is equal to ƒ s, the current in the resonant tank takes sine wave form. Voltage across capacitor C r is a pure sine waveform. The two switching devices (S 1 and S 3, S 2 and S 4 ) in each leg of the H-bridge are switched alternatively with almost 50% duty ratio. The switching pulses to the two legs have a phase angle of in order to change the voltage applied to the resonant tank. Unbalanced switching signal will not cause saturation to the transformer due to presence of the series resonant capacitor. The relationship between input voltage and output voltage can be expressed by V V o (2.2) n To reduce the size of the energy storage components such as inductor, capacitor and transformer, high switching frequency ƒ s is considered. The switches operate under zero voltage switching condition. T is the period of resonance. 1 T (2.3) f s The resonant current i r is regulated by changing the phase angle and rectified as the input power signal of the output filter. Thus the output voltage is controlled. The voltage across the primary side of the transformer has the same phase as the resonant current.
34 Normalized DC gain of this converter is a function of w where w is the normalized variable which is related to the parameters L r, C r of actual circuit. Design parameter calculations are as follows: Table 2.1 Design parameters of PSRC DC input voltage V i 48V DC output voltage V o 12V Resonant frequency f r 38.4KHz Resonant capacitor C r 2µF Ripple factor r 0.2% Volt/turn 4 Mean length L 0.7m Area of Secondary A 2 170mm 2 Current density 0.021A/ mm 2 Area of Primary A 1 5mm 2 Vi N 1 12 (2.4) Volt / turn Vo N2 3 (2.5) Volt / turn N L 1 r p (2.6) a p = 0.0358 milliohms N L 2 r s (2.7) a s = 25 milliohms C filter 1 r (2.8) 4 3 fcr C r = 470µF L r = 8.5 µh
35 ZVS condition The period between t 2 to t 4 is defined as dead time. During the dead time, currents in the two branches on the primary side should complete ultimate energy communication between the parasitic capacitors of the two main switches in each branch to create ZVS conditions. Similarly another dead time will be there at t 6 to t 8 after S 2 is switched off. Dead times are small compared to switching cycle. During dead time periods, the sum of primary current can be considered as the peak value of I Ls /n where n is the primary to secondary turn ratio. The PSRC has the advantage of inherent short circuit protection characteristic and high conversion efficiency. Normally the value of the load resistance and the input DC voltage are variable within a specific range, the voltage feedback and certain closed-loop control law should be employed to keep the output voltage at the desired values. Though the error can be eliminated through the algorithm of the controller, the dynamic performance may not be satisfied especially for nonlinear systems. To overcome this problem a closed loop control system for the PSRC is proposed in this chapter. By controlling the resonant current which is rectified for supplying the load, the dynamic control performance of the converter system is improved. This method is called quasi current mode because the current controlled is regulated indirectly using the resonant tank. 2.5 SIMULATION RESULTS The simulation is carried out for open loop system and closed loop system using Matlab/Simulink. Simulink model of Phase shifted series resonant converter is shown in Figure 2.3. DC input voltage and input current is shown in Figure 2.4. Simulation waveforms of PSRC are shown in Figure 2.5. In order to achieve constant frequency, variable duty cycle control, switches S 1 and S 3 are operated with approximately 50% duty cycle and
36 switches S 2 and S 4 have a duty cycle in the range from 0% to 50%duty cycle. Figure 2.6 shows Switch3 s driving signal V gs3, drain source voltage V ds3 and the current flowing through drain source I ds3. It is observed that I ds3 is negative before the arrival of the driving signal, which assures V ds3 decreases to zero before the switch turns on and achieves ZVS. Turn off loss is negligible. Figure 2.7 shows the driving pulse V gs4, drain source voltage V ds4 and the current flowing through drain source I ds4 of switch4. Figure 2.8 shows the transformer s secondary side voltage which is nearly quasi square wave. DC output voltage and output current are shown in Figure 2.9. DC output voltage is 12.2V and output current is 2.99A. The output voltage is free from ripple. Table 2.3 and 2.4 show the performance of the Phase shifted series resonant converter. Figure 2.3 Simulink model of Phase shifted Series Resonant converter Table 2.2 Simulation parameters of PSRC DC input voltage 48V Switching frequency 38.3 khz Resonant frequency 38 khz Resonant inductor 8.5µH Resonant capacitor 2µF Load resistance 4
37 Figure 2.4 (a) DC input voltage (b) Input current Figure 2.5 Simulation waveforms of PSRC
38 Figure 2.6 (a) Driving signal V gs3, (b) current I ds3 and (c) V ds3 of switch3 Figure 2.7 (a) Driving signal V gs4, (b) current I ds4 and (c) V ds4 of switch4 Figure 2.8 Secondary side voltage of the Transformer
39 Figure 2.9 DC output current and output voltage Table 2.3 Performance of the PSRC for changes in % load % of Output Output Output Input Efficiency load voltage (V) current (A) power (w) power (w) (%) 35.5 12.28 0.65 8 10.12 79 50 12.27 0.86 10.55 13.14 80.25 62.5 12.25 1.32 16.17 19.82 81.58 75 12.23 1.83 22.38 27 82.83 87.5 12.2 2.34 28.55 34 83.92 100 12.2 2.99 36.48 43.33 84.2 Table 2.4 Performance of the PSRC for changes in input voltages Input Input Input Output Output Output Efficiency voltage current power voltage current Power (%) (V) (A) (w) (V) (A) (w) 40 0.65 26.13 11 1.98 21.78 83.33 44 0.82 36.08 11.98 2.5 29.95 83 48 0.9 43.22 12.2 2.99 36.48 84.4 52 0.94 48.88 12.51 3.3 41.28 84.45
40 Figure 2.10 R- load (%) versus output voltage Figure 2.11 R- load (%) versus output power Figure 2.12 R - load (%) versus efficiency From Figure 2.10 and Figure 2.11 it is observed that the output voltage is almost constant and the output power increases with the increase in load. From Figure 2.12 it is clear that the efficiency is high at high load and is found to be 84.2 % at 100% load and reduces to 80.25 % at 50% load.
41 Figure 2.13 Input voltage versus output voltage Figure 2.14 Input voltage versus output power Figure 2.15 Input voltage versus efficiency From Figure 2.13 and Figure 2.14 it is observed that the output voltage and the output power increase with increase in input voltage. From Figure 2.15 it is clear that the efficiency increases slightly with the increase in input voltage. The value of output voltage is found to be 12.2 V at 48 V input voltage.
42 2.5.1 Comparison of Open Loop System with Closed Loop System for Step Change in Input Voltage The simulink model of open loop system is shown in Figure 2.16. A step change in voltage is applied at the input. The DC input voltage, output current, and output voltage with input step change is shown in Figure 2.17. When input voltage is increased at 0.4s to a value of 60V, the output voltage also increases and settles at a new value of 15.5V. Figure 2.16 Open loop system with step change in input Figure 2.17 Results of open loop system with step change in input (a) Input voltage (b) Output current (c) Output voltage
43 The simulink model of closed loop system is shown in Figure 2.18. In order to maintain the required output voltage level, closed loop control is used. The instantaneous voltage signal is taken from the output and given to a comparator. Other input to the comparator is the set voltage of 12V.Output of comparator is the error signal which is given to the PI controller. The output of PI controller is given to the two comparators whose outputs are quasi waves. In order to generate control pulses the output of PI controller is compared with a triangular reference wave of peak value 8 and time period of 50s, which is shown in Figure 2.20. The generated pulses are used as control signals for the gates of MOSFETs S 1 to S 4. The DC input voltage, output current, and output voltage with input step change is shown in Figure 2.19.The parameters of PI controller are shown in Table 2.5. Figure 2.18 Closed loop system with step change in input The step change is applied at 0.4 seconds for open loop system as shown in Figure 2.16. From Figure 2.17 it is observed that the open loop system has steady state error. For the closed loop system shown in Figure 2.18, when the input voltage is increased to 60V at 0.4s the control circuit takes proper action and the output voltage is maintained at 12.08V as shown in Figure 2.19. Set voltage is taken as 12V.The closed loop system reduces the steady state error. It settles at 0.75s. The settling time is 0.35s.
44 Figure 2.19 Results of closed loop system with step change in input (a) Input voltage (b) Output current (c) Output voltage Figure 2.20 (a) Output of PI controller (b) Triangular wave (c) Driving pulses Table 2.5 Parameters of PI controller Proportional gain(k p ) 0.5 Integral gain(k i ) 15 Output limits [10 10] Sample time 20 e-6
45 2.5.2 Comparison of open loop system with closed loop system for output load regulation The simulink model of open loop system without output load regulation is shown in Figure 2.21. Input voltage is 48V DC. A breaker is connected in parallel with the load. Load resistance is 4. The breaker is opened at initial state and it is closed at 0.4s. DC output voltage is shown in Figure 2.22 where the output voltage is increased at 0.4s due to change in the load. Figure 2.21 Open loop system without output load regulation Figure 2.22 DC output voltage with step change in load
46 The simulink model of closed loop system for output load regulation is shown in Figure 2.23. Input voltage is 48V DC. Set voltage is 12V DC. In order to maintain the required output voltage level, closed loop control is used. The instantaneous output voltage signal is given to a comparator. Other input to the comparator is the set voltage.output of comparator is the error signal which is given to the PI controller. The output of PI controller is given to the two comparators whose outputs are PWM waves. They are used as control signals for the gates of MOSFETs S 1 to S 4. Figure 2.23 Closed loop system with output load regulation Figure 2.24 DC output voltage of closed loop system
47 The breaker is opened at initial state and it is closed at 0.4s.When the breaker is closed, due to load side disturbance the output voltage increases to a value of 12.1V. But the closed loop system settles the output voltage to a value of 12V at 0.6s as shown in Figure 2.24.The settling time is 0.2s. 2.6 EXPERIMENTAL RESULTS The DC-DC converter was built and tested for open loop phase shifted series resonant converter at 48 V DC. The circuit parameters are as follows: Table 2.6 Experimental parameters of PSRC Switching frequency 38.3 khz Resonant capacitor C r 2µF Resonant inductor L r 8.5µH Filter capacitor C 470µF Load resistance R 4 Resonant frequency f r 38 khz Hardware layout of open loop Phase shifted series resonant converter is shown in Figure 2.25.Flow chart for generating the pulses is shown in Figure 2.26. Experimental waveform of driving pulses of switch3 and switch1 is shown in Figure 2.27. Driving pulses of switch4 and switch2 is shown in Figure 2.28. The primary side voltage of the transformer is shown in Figure 2.29. The secondary side voltage of the transformer is shown in Figure 2.30. Load voltage wave form is shown in Figure 2.31 and the output voltage is shown in Figure 2.32.
48 Figure 2.25 Hardware layout of Phase shifted series resonant converter 2.6.1 Microcontroller Program for Generation of Square wave Pulses START PORT INITIALIZATION MOVE DATA 05H TO PORT3 CALL DELAY MOVE DATA 00 H TO PORT3 MOVE DATA 0A H TO PORT3 CALL DELAY MOVE DATA 00 H TO PORT3 SJMP Figure 2.26 Flow chart for generating square pulses
49 follows: The assembly language program for generation of square pulse is as P3 EQU 90H ORG 0000H Equalizing port address 90H to port3 Initializing starting address as 0000H MOV P3, #00H Clearing the bits of Port 3 START : MOV P3, #0AH Send 0AH to P3 CALL DELAY1 CALL DELAY1 MOV P3,#00H CALL DELAY1 MOV P3,#05H CALL DELAY1 CALL DELAY1 MOV P3,#00H CALL DELAY1 SJMP START Call the subroutine delay1 Call the subroutine delay1 Send 00H to P3 Call the subroutine delay1 Send 05H to P3 Call the subroutine delay1 Call the subroutine delay1 Send 00H to P3 Call the subroutine delay1 Short jump to START DELAY1 : MOV R0,#15H Load register R0 with 15H AA : DJNZ R0,AA Decrement RO on no zero jump to AA RET Return to main program
50 Figure 2.27 Driving pulses for switch3 and switch1 Figure 2.28 Driving pulses for switch4 and switch2 X axis 1 div = 10 µs; Y axis 1div =20V Figure 2.29 Voltage across the primary of the transformer
51 X axis 1 div = 10µs. Y axis 1 div=10v Figure 2.30 Voltage across the secondary of the transformer X axis 1 div = 10µs, Y axis 1 div =10V Figure 2.31 Load voltage wave form Figure 2.32 Output voltage across the load
52 For 100% load the output voltage of the open loop experimental result is 12.1V and that of simulation is 12.2V. Hence the experimental results closely agree with the simulation result. 2.7 SUMMARY Soft switched Phase shifted series resonant DC to DC converter is analysed, simulated, tested and the results are presented. The configuration considered is the Phase shifted series resonant converter. The zero voltage switching technique is employed here in order to avoid the switching losses that are available in the circuit. Though the error can be eliminated through the algorithm of the controller, the dynamic performance may not be satisfied especially for nonlinear systems. To overcome this problem a closed loop control system for the PSRC is proposed. By controlling the resonant current which is rectified for supplying the load, the dynamic control performance of the converter system is improved. This method is called quasi current mode because the current controlled is regulated indirectly using the resonant tank. The error is eliminated through PI algorithm of the controller. The dynamic performance of the converter system is improved as compared to that of the conventional system. It is observed that the output voltage remains constant even when step disturbance is applied at the input 0.4s.Thus the output voltage is maintained constant by using a closed loop system. The open loop experimental results closely agree with the simulation results.