LSI/CSI LSN-N UL LSI Computer Systems, Inc. Walt Whitman Road, Melville, NY (6) -000 FX (6) -00 00 PROGRMMLE DIGITL DELY TIMER FETURES: -bit programmable delay from microseconds to days On chip oscillator (RC or Crystal) or external clock time base Selectable prescaler for real time delay generation based on 0Hz/60Hz time base or,6hz watch crystal Four operating modes Reset input for delay abort Low quiescent and operating current Direct relay drive +V to +V operation ( - VSS) LSN, LSN (DIP); LSN-S, LSN-S (SOIC) - See Figure - DESCRIPTION: The LSN and LSN are CMOS integrated circuits for generating digitally programmable delays. The delay is controlled by binary weighted inputs, W0 - W, in conjunction with an applied clock or oscillator frequency. The programmed time delay manifests itself in the Delay Output () as a function of the Operating Mode selected by the Mode Select inputs and : One-Shot, Delayed Operate, Delayed Release or Dual Delay. The time delay is initiated by a transition of the Trigger Input (). I/O DESCRIPTION: MODE SELECT Inputs & (Pins & ) The operating modes are selected by Inputs and according to Table TLE. MODE SELECTION MODE 0 0 One-Shot (OS) 0 Delayed Operate (DO) 0 Delayed Release (DR) Dual Delay (DD) Each input has an internal pull-up resistor of about 00kΩ. One-Shot Mode (OS) positive transition at the input causes to switch low without delay and starts the delay timer. t the end of the programmed delay timeout, switches high. If a delay timeout is in progress when a positive transition occurs at the input, the delay timer will be restarted. negative transition at the input has no effect. Delayed Operate Mode (DO) positive transition at the input starts the delay timer. t the end of the delay timeout, switches low. negative transition at the input causes to switch high without delay. is high when is low. N-00- () RC/ RCS/CLKS PSCLS VSS (-V) () XTLI/ XTLO PSCLS VSS (-V) PIN SSIGNMENT - TOP VIEW 6 6 LSI 9 0 LSI Feb 0 Delayed Release Mode (DR) negative transition at the input starts the delay timer. t the end of the delay timeout, switches high. postive transition at the input causes to switch low without delay. is low when is high. Dual Delay Mode (DD) positive or negative transition at the input starts the delay timer. t the end of the delay timeout, switches to the logic state which is the inverse of the input. If a delay timeout is in progress when a transition occurs at the input, the delay timer is restarted. LSN LSN 6 6 9 0 FIGURE W0 W W W W W W6 W W0 W W W W W W6 W
GER Input (, Pin ) transition at the input causes to switch with or without delay, depending on the selected mode. The input to transition relation is always opposite in polarity, with the exception of One-Shot mode. (See Mode definitions above.) input has an internal pull-down resistor of about 00kΩ and is buffered by a Schmitt trigger to provide input hysteresis. LSN TIME SE Input (RC/, Pin ) For LSN, the basic timing signal is applied at the RC/ input. The clock can be provided from either an external source or generated by an internal oscillator by connecting an R-C network to this input. The frequency of oscillation is given by ƒ /RC. Chip-tochip oscillation tolerance is ± % for a fixed value of RC. The minimum resistance, R MIN = 000Ω, = + V = 00Ω, = +0V = 600Ω, = +V The external clock mode is selected by applying a logic low to the RCS/CLKS input (Pin ); the internal oscillator mode is selected by applying a high level to the RCS/CLKS input. LSN TIME SE Input (XTLI/, Pin ) For LSN, the basic timing clock is applied to the XLTI/ input from either an external clock source or generated by an internal crystal oscillator by connecting a crystal between XTLI/ input and the XTLO output (Pin ). LSN TIME SE SELECT Input (RCS/CLKS, Pin ) For LSN, the external clock operation at Pin is selected by applying a logic low to the RCS/CLKS input. The internal oscillator option with RC timer at Pin is selected by applying a logic high at the RCS/CLKS input. RCS/CLKS input has an internal pull-down resistor of about 00kΩ. LSN TIME SE Output (XTLO, Pin ) For LSN, when a crystal is used for generating the time base oscillation, the crystal is connected between XTLI/ and XTLO pins. PRESCLER SELECT Input (PSCLS, Pin 6) The PSCLS input is a -state input, which selects one of three prescale factors according to Table. TIMER Input (, Pin ) When input switches high, any timeout in progress is aborted and switches high without delay. With RE- SET high, remains high. When switches low with low in any mode, remains high. When RE- SET switches low with high in Delayed Operate and Dual Delay modes, the delay timer is started and switches low at the end of the delay timeout. When RE- SET switches low with high in Delayed Release mode, switches low without delay. When switches low with high in One-Shot mode, remains high. input has an internal pull-down resistor of about 00kΩ, and is buffered by a Schmitt Trigger to provide input hysteresis. VSS (-V, Pin ) Supply voltage negative terminal or GND. DELY Output (, Pin 9) Except in One-Shot mode, switches with or without delay (depending on mode) in inverse relation to the logic level of the input. In One-Shot mode, a timed low level is produced at, in response to a positive transition of the input. WEIGHTING IT Inputs (W to W0, Pins 0 - ) Inputs W0 through W are binary weighted delay bits used to program the delay according to the following relations: One-Shot Mode: Pulse width = SW ƒ ll other Modes: Delay = SW + 0. ƒ Where: S = Prescale factor (See Table ) ƒ = Time base frequency at Pin W = W0 + W +... W The weighting factor W is calculated by substituting in the equation above for W, the weighted values for all the W inputs that are at logic high. The weighted values for the W inputs are shown in Table. Each W input has an internal pull-down resistor of about 00kΩ. TLE. PRESCLE FCTOR SELECTION TLE. IT WEIGHTS PSCLS Input S (Prescale Factor ) Logic Level LSN LSN Float VSS,000,6,600,6x60 Using prescale factors of 000 and 600, delays in units of minutes can be produced from 0Hz and 60Hz line sources. Prescale factors of,6 and,6 x 60 can be used to generate accurate delays in units of seconds and minutes, respectively, from a khz watch crystal. N-0609- ITS VLUE W0 W W W W 6 W W6 6 W (, Pin ) Supply voltage positive terminal.
SOLUTE MXIMUM RTINGS: (ll voltages referenced to VSS) SYMOL VLUE UNIT DC Supply Voltage +9 V Voltage (ny Pin) VIN VSS - 0. to + 0. V Operating Temperature T -0 to + C Storage Temperature TSTG -6 to +0 C ELECTRICL CHRCTERISTICS (Voltages referenced to Vss) Characteristic SYMOL -0 C + C + C Unit Condition Min Max Min Max Min Max Supply Voltage -.0.0.0.0.0.0 V -.0-66 - - µ Supply Current IDD 0.0 - - 0-6 µ with the clock off and.0-0 - 0-60 µ all inputs floating. Input Voltages:.0-0. - 0. - 0. V Reset, Trigger Low VTL 0.0 -. -. -. V -.0 -.9 -. -. V.0. -. -.0 - V Reset, Trigger High VTH 0.0 6. - 6.0 -.9 - V -.0 9. - 0. -.0 - V.0 0. - 0. - 0. - V Reset, Trigger Hysteresis 0.0. -. -. - V -.0.9 -.9 -.9 - V.0 -. -. -. V ll other inputs, Low VIL 0.0 -. -. -. V -.0-0.6-0.6-0.6 V.0.9 -.9 -.9 - V ll other inputs, High VIH 0.0 6. - 6. - 6. - V -.0. -. -. - V Input Currents:.0 -. -. -.9 µ PSCLS Low IPL 0.0 - - - µ Input at VSS.0 - - 6-9 µ.0-9. -. -. µ PSCLS High IPH 0.0 - - -. µ Input at.0 - - 6-9 µ.0-6.0 -.0 -.0 µ, Low IML 0.0-9 - - µ Input at VSS.0 - - - 9 µ, High IMH - - 00-00 - 00 n Input at ll other inputs, Low IIL - - 00-00 - 00 n Input at VSS.0 - - - µ ll other inputs, High IIH 0.0-0 - 0 - µ Input at.0 - - 0 - µ Output Current:.0. - 0. -.0 - m Sink IOSNK 0.0 6-9. - - m Vo = +0.V.0 0. -.6 - - m.0. -. -. - m Source IOSRC 0.0. -. -. - m Vo = - 0.V.0. - 6. -.6 - m N-0009-
ELECTRICL CHRCTERISTICS (Voltages referenced to Vss) (Con t) Characteristic SYMOL Unit Condition Min Max Min Max Min Max Switching Characteristics (See Fig. ).0 -. -. -.0 MHz RC Oscillator Frequency fosc 0.0 -. -. -.6 MHz -.0 -.0 -.0 -.0 MHz.0 -.6 -.0 -. MHz For prescale External Clock or fext 0.0 -. -.0 -.0 MHz factor S = 6 Crystal Oscillator.0 -.9 -. -. MHz or 6 x 60 Frequency.0 -. -. -. MHz S = or 000 fext 0.0-6.0 -. - 9. MHz or 600.0 -.9 -.0-9. MHz Set-Up Time t - 9-0 - 66 - ns -, Set-Up Time t - 0-0 - 0 - ns - W0 - W Set-Up Time t - 0-0 - 0 - ns -.0 - - - 9 ns Clock to Out Delay t 0.0-9 - 0 - ns CL = 0pF.0 - - - ns 00k MODE REG 00k EDGE DETECT LTCH CONTROL LOGIC UF 9 00k /RC/XTLI 00k LTCH/TIMER 0- W-W0 00k () OSC MUX XTLO (LSN) PRESCLER RCS/CLKS (LSN) 00k PSCLS 6 M M -STTE DECODER -V (Gnd) VSS FIGURE. LSN / LSN LOCK DIGRM N-00-
t0 Clock t t, W0-W t t = 0, =, Delayed Operate Programmed Delay t Immediate Release Note. input is clocked in by the negative edge of external clock. Note. Inputs, and W0 - W are sampled only at a input transition and ignored at all other times. Note. is switched by the positive edge of the external clock. FIGURE. INPUT/PUT TIMING (OS) C F (DO) (DR) D (DD) E G H. Turn-on delay in DO and DD modes; Pulse-width in OS mode.. Turn-off delay in DR and DD modes. C. Pulse-width extended by re-trigger in OS mode. No effect in DO and DD modes because switches back low before turn-on delay has timed out. D. Turn-off delay in DR mode. E. Turn-on delay in DO and DD modes; pulse-width in OS mode. F. No effect in DO, DR and DD modes because of s switching back to opposite levels. G. Time-outs aborted and forces high by. H. fter the removal of, switches to the inverse polarity of immediately (DR) or after the timeout (DO, DD). No effect in OS. FIGURE. MODE ILLUSTRTION WITH, ND N-06906-
RCS/CLKS pf 0k CRYSTL 0M XTLO LSN XTLI LSN 0k ƒ 0.µF RC LSN pf LSN FIGURE 6. MULTI-TIMER WITH SINGLE CRYSTL TIME-SE V SS V DD ƒ = - -6 0 x 0 x 0. x 0 = khz 0VC M LSN FIGURE. RC- Oscillator Connection 00pF V SS FIGURE. DRIVING INPUT FROM THE C LINE * * 0-, W0-W, LSN * * 0-, W0-W, LSN GER ƒ 9 9 Vss Vss * Connect for desired delay and mode FIGURE. DELY EXTENSION Y CSCDING N-0609-6
GER IN pf ƒ pf 0k S 0M 6 XTLI XTLO PSCLS W0 W W W W W W6 W 6 0 s/m s/m s/m s/m 6s/6m s/m 6s/6m s/m Vss LSN s = seconds m = minutes PUT 9 NOTE : Crystal Frequency, ƒ =,6Hz Switch: S low: Delay increment = s; Maximum Delay = s S high: Delay increment = m; Maximum Delay = m FIGURE 9. PROGRMMLE CCURTE REL-TIME DELY GENERTION The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. N-0606-
V DD W0 W 6 ƒi LSN W W W W ƒo 9 Vss W6 W 0 CSE. MODE = DO or DR; PRESCLE FCTOR, S = In this setup a frequency division of the input clock, ƒi by a factor of to, in increments of can be obtained according to the equation: ƒo = ƒi where W (weighting factor) = 0 to W + The ƒo pulse width is non-symmetrical (non-0% duty -cycle) CSE. MODE = DD; PRESCLE FCTOR, S = In this setup a frequency division of the input clock, ƒi by a factor of to, in increments of can be obtained according to the equation: ƒi ƒo = where W (weighting factor) = 0 to (W + ) The ƒo pulse widths are symmetrical with 0% duty -cycle EXMPLES OF CSE and CSE FREQUENCY DIVISIONS WITH W = ƒi ƒo Case, Mode = DO; ƒo Case, Mode = DD; 6 N-0606- FIGURE 0. PROGRMMLE FREQUENCY DIVIDER