How to Improve Power Integrity on Analog-to-Digital Converter (ADC) with Chip-PCB Hierarchical Structure

DesignCon 2013 How to Improve Power Integrity on Analog-to-Digital Converter (ADC) with Chip-PCB Hierarchical Structure Bumhee Bae, Korea Advanced Institute of Science and Technology (KAIST) bhbae@kaist.ac.kr, +82-42-351-9868 Jonghyun Cho, KAIST jonghyun.cho@kaist.ac.kr, +82-42-351-9869 Sunkyu Kong, KAIST sunkyu84@kaist.ac.kr, +82-42-351-9870 Jonghoon J. Kim, KAIST jonghoonk@kaist.ac.kr, +82-42-351-9867 Yujeong Shim, Altera Corporation yshim@altera.com, (408) 616-0529 Joungho Kim, KAIST joungho@ee.kaist.ac.kr, +82-42-351-5458

Abstract Both analog devices, sensitive to noises, and another device, such as digital devices, power circuits, and antennas which could be noise sources, have been integrated into the latest electric system. Due to its complexity derived from the integration of analog devices and noise source, it is hard to achieve high performance of analog or mixed-mode system. We will model and analyze power integrity on mixed-mode system in this study. For verifying the model and the analysis on mixed-mode system, we use 4bit flash-type Analog-to-Digital Converter (ADC) as a targeted system application, because ADC is one of the essential mixed-mode device, and flash-type ADC is one of the common high speed ADC. To validate the model and analysis, a 4bit flash-type ADC was fabricated by a 0.13 µm CMOS process and interconnected to the designed PCB. Author(s) Biography Bumhee Bae received B.S and M.S degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently pursuing the Ph.D. degree in electrical engineering. His research interest includes EMI/EMC susceptibility of mixed-mode system with chip-package-pcb hierarchical structures. Jonghyun Cho received B.S. and M.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2008 and 2010, respectively. He is now a Ph.D. candidate in electrical engineering from KAIST. His research interests include Si-interposer design, TSV noise coupling, and TSV depletion effects in TSV-based 3D IC. Sunkyu Kong received the B.S. degree in electrical and electronic engineering from Chungnam National University, Daejeon, Korea. He received the M.S. degree from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently pursuing the Ph.D. degree in electrical engineering. His research interest includes EMI/EMC issues in analog-digital mixed-mode system with chip-package hierarchical structures. Jonghoon J. Kim received B.S in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently pursuing the M.S. degree in electrical engineering. His research interest includes current probing and wafer testing structures using inductive coupling in multi-layer PCBs, as well as on chip level. Yujeong Shim is a senior signal integrity engineer at Altera Corporation. Her responsibility includes jitter modeling on high speed serial links and power distribution network design on system level. She received the B.S, the M.S and the Ph.D degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2005, 2007, and 2011 respectively. She worked as a visiting

researcher at Silicon Image, Inc., Sunnyvale, California, US in 2008. In 2009, she was involved as an internship in RF and mm-wave modeling and characterization team at IMEC, Leuven, Belgium. She is an author/a co-author of 32 IEEE SCI journal /conference, and received the best paper awards at the 2007 Electromagnetic Compatibility (EMC) Compo, Torino, Italy and 2011 DesignCon, Santa Clara, US. Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. He is currently a Professor at Electrical Engineering and Computer Science Department. Since joining KAIST, his research centers on modeling, design, and measurement methodologies of hierarchical semiconductor systems including high-speed chip, package, interconnection, and multi-layer PCB. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3D semiconductor packages, systemin-package(system-in-package), and SoP(System-on-package). He was on a sabbatical leave during academic year from 2001 to 2002 at Silicon Image Inc., Sunnyvale CA, as a staff engineer. He was responsible for low noise package design of SATA, FC, HDMI, and Panel Link SerDes devices. Currently, he is the director of Satellite Research Laboratory of Hyundai Motors for EMI/EMC modeling of automotive RF, power electronic and cabling systems. He has more than 210 publications in refereed journals and conferences. Dr. Joungho Kim has been the chair or the co-chair of the EDAPS workshop since 2002. Currently, he is an Associated Editor of the IEEE Transactions of Electromagnetic Compatibility.

1. Introduction Both analog devices, sensitive to noises, and another device, such as digital devices, power circuits, and radiated field source which could be noise sources, have been integrated into the latest electric system, which is called mixed-mode system [1]. Due to its complexity derived from the integration of analog devices and noise source, it is hard to achieve high performance of mixed-mode system. To achieve high performance system, the mixed-mode system has to be designed with the consideration of noise effects. However, it has not been sufficiently studied of which noise source plays the most significant impact on the analog devices and the overall mixed-mode system and how the noise affects to performance of the system with the hierarchical structure. Therefore, it is needed to analyze the performance variation by several noises. In mixed mode system, digital devices generate Simultaneous Switching Noise (SSN) [2] and the power devices generate radiated strong Electro-Magnetic Interference (EMI) [3]. Both noises are critical Power Supply Noise (PSN) source, so we will model and analyze power supply noise effects from each noise source on mixed-mode system in this study. For verifying the model and the analysis of mixed-mode system, we use 4bit flash-type Analog-to-Digital Converter (ADC) as a targeted system application, because ADC is one of the essential mixed-mode device, and flash-type ADC is one of the common high speed ADC. The system of 4bit flash-type ADC consists of chip and PCB hierarchical structure, and they affect each other. The noise coupling path from noise source to noise victim circuit of ADC also includes the elements of chip and PCB. Therefore, it is needed to determine which ADC part is noise victim circuit and analyze how much noise is reached to the noise victim via hierarchical structure. First of all, we have to determine which ADC part is noise victim circuit. The chip of 4bit flash-type ADC consists of reference ladder, comparators, digital blocks, encoder, and output buffers. Among these components, the comparator is analog component and the most noise sensitive circuit on 4bit flash-type ADC. This type of ADC has 15 comparators, and each comparator has two inputs, which are Vin+ and Vin-, respectively. The reference voltage is assigned as Vin+, and the input signal to be compared with the reference voltage is given as Vin-. Fifteen-stepped reference voltages reach Vin+ of each comparator in ADC. Each comparator in ADC has two output conditions, determined by the differential input obtained when comparing the reference voltage with the voltage of the input signal. When the level of the input signal is larger than that of the reference voltage, the output voltage of the comparator ADC remains at low. The 16 results convert to 4-bit digital outputs. Consequently, the different voltage between two inputs of comparator directly affects ADC outputs, so it is dominant noise victim of ADC. Second step is that how much noise is reached to the noise victim. We use noise coupling ratio, which is one of the key factor to analyze noise effects, from noise source to noise victim. The trend of noise coupling is different between noise sources; SSN and EMI. For accurate analysis, we will model and analyze the coupling path of each noise. There are PCB power/ground plane, bonding-wire, on-chip power/ground ring, on-chip decoupling capacitor, and etc on noise coupling path. The reached noise at victim circuit is changed by the structure of noise coupling path; chip, package, and PCB elements. We consider various chip-pcb hierarchical structures, such as the structure with bonding wire, with TSV, or with decoupling capacitor, and it affects to noise coupling ratio. In according to

noise source or hierarchical structure, we analyze which frequency noise is well coupled to noise victim. To validate the model and analysis, a 4bit flash-type ADC was fabricated by a 0.13 µm CMOS process and interconnected to the designed PCB. SSN which is assumed as a single tone noise from 1 MHz to 3 GHz is injected into the PCB board, and Wireless Power Transfer (WPT) coil, as a low frequency EMI source, is placed near the system of ADC. The model and analysis of noise coupling ratio will be derived by co-simulation or measurement of designed ADC system, and it will be co-related with the performance of ADC. This study will let the chip, package, and PCB designers save time and effort to achieve high quality analog devices or mixed mode systems by getting intuition of noise effect. 2. ADC, the Important Device on Mixed-Mode System 2-1. The Flash-type ADC as an Targeted Mixed-mode Application As recently designed systems can achieve high density and capability at a low cost with a high manufacturing yield, the mixed-mode system is a common technology in the industrial field. Therefore, it is strongly needed to investigate internal and external noise effects on mixed-mode system for guarantying high reliability of recently systems, because the mixed-mode system integrates both various noise sources and noise victims on the tiny board. In this paper, we investigate various EMC problems on mixed-mode system and propose its multiple solutions based on the analysis with measurements, simulations, and models. Among various mixed-mode devices, we choose ADC, especially flash-type ADC which is representing high speed ADCs, as a targeted mixed-mode application. There are several reasons we choose the ADC as a targeted mixed-mode device. First, the ADC is essentially needed to mixed-mode systems, because it is the bridge device between the part of analog and that of digital. Second, the characteristics of ADC can cover wide characteristics of mixed-mode system. The ADC includes both typical analog circuits, such as the comparator, and typical digital circuits, such as the logic gate, the encoder, the latch, and the I/O buffer, etc. It means only ADC itself is a mixed-mode system. Therefore, the analysis methodology of ADC can be applied to that of other mixed-mode systems. The designed 4bit flash type ADC consists of reference ladder, comparators, digital blocks, encoder, and output buffers, shown in Figure 1. This type of ADC has 15 comparators, and each comparator has two inputs, one is the reference input, and the other is analog input. There are fifteen-stepped reference-voltages reach to 15comparators for comparing with the analog input voltage. The comparator outputs include the 16 results, and these convert to 4-bit digital outputs. The Figure 2 shows the layout of the designed ADC fabricated by 0.13um CMOS process. For defining ADC performance against the noise, we use the ENOB (Effective Number of Bits) the parameter directly derived from SNDR (Signal-to-Noise Distortion Ratio), the commonly used performance factor which is the ratio of input signal amplitude to the output noise level plus harmonics, and expressed by the bits of the ideal ADC.

Figure 1. The conceptual diagram of 4bit flash type ADC Figure 2. The layout of designed 4-bit flash type of ADC for this research 2-2. Design Techniques for Preventing EMC Problems There are several expected EMC problems on mixed-mode system. By recent design technologies of mixed-mode system, some EMC problems are effectively prevented, and the other EMC problems still let the system designers build the system with further EMC consideration. In this part, we introduce the applied recent technologies for preventing EMC problems on ADC, one of the mixed-mode devices, and discuss which EMC issues are further considerable on ADC design.

Figure 3. The Expected EMC Problems on ADC in Mixed-Mode System Figure 3 shows multiple EMC issues which can be generated on ADC system. Both digital and analog problems can be occurred on ADC system. When we design the chip of ADC, we have to consider all of expected EMC issues. For preventing EMC problems, we insert de-skew latches, on-chip decoupling capacitors, guard-rings, and deep N-well, for on-chip ADC design. Among these applied EMC protection methods, Figure 4 shows the de-skew latch which is one of the on-chip level design technologies for decreasing skew. Figure 4(a) is the schematic of de-skew latch and Figure 4(b) displays the output waveforms with or without de-skew latch. Nevertheless, some issues, such as PSN effects, affected by SSN and EMI, are hard to protect perfectly, and needed to further consideration. (a)

(b) Figure 4. The On-chip Level Design for Decreasing Skew (a) The Schematic of De-skew Latch (b) The Output Waveforms with or without De-skew Latch 2-3. Further Issues which We Consider PSN effects are difficult to define on mixed-mode system, because the noise coupling path from a source to a victim is greatly complex. Therefore, we focus on the analysis method of Power Integrity (PI) issues on mixed-mode system. First of all, we have to define which part become a noise source and a noise victim. There are two critical aggressors in mixed mode system, one is digital circuit, and the other is WPT coil. Digital circuits generate SSN (Simultaneous Switching Noise), and WPT coil generate EMI (Electro Magnetic Interference). Both noises couple to the PDN (Power Distribution Network), and these become critical PSN source. AVDD with PSN(f) DVDD with PSN(f) ENOB (f=10m) 3.9838 3.9992 ENOB (f=20m) 3.8513 3.9992 ENOB (f=26m) 3.8293 3.9992 ENOB (f=50m) 3.9389 3.9992 ENOB (f=1000m) 3.9992 3.9992 Comment The performance of ADC is sensitive to AVDD noise The performance of ADC is not sensitive to DVDD noise Table 1: Comparison with Performance Variations when AVDD (Analog Power) or DVDD (Digital Power) is fluctuated with PSN (100mV, multiple frequencies) Among AVDD (Analog power) and DVDD (Digital power), we have to determine which part is sensitive to PSN. Table 1 is the simulated result and it lets us know analog part is sensitive to PSN. So, we focus on PSN effect on analog part of ADC. 3. PSN Effects on ADC The analysis of PSN effects is essentially needed to guarantee the reliability on the mixed-mode system, because there are multiple PSN sources and PSN cause critical harm to mixed-mode circuit, referred by Table 1 and Figure 5. There are three steps to analyze

PSN effects on ADC. First step is that we determine which ADC part is noise victim circuit. Second step is that how much noise is reached to the noise victim from each noise source and how much ADC performance degradation is occurred by coupled noise. Third step is the understanding the PSN waveform from each noise sources and decision making by previous results. Among multiple PSN sources, we choose two critical noise sources, one is SSN source, and the other is EMI source. Figure 5. The comparative results of an output bit of the ADC with the PSN and without the PSN. The code-missing and code-generating errors are due to the PSN. 3-1. Differential Input of Comparator, Noise Victim on ADC Among the circuits on ADC, the comparator and reference ladder are the analog circuit which is sensitive to noise. The designed ADC has 15 comparators, and each comparator has two inputs, which are Vin+ and Vin-, respectively. The reference voltage, induced by reference ladder, is assigned as Vin+, and the input signal to be compared with the reference voltage is given as Vin-. Each comparator in ADC has two output conditions, determined by the differential input obtained when comparing the reference voltage with the voltage of the input signal. When the level of the input signal is larger than that of the reference voltage, the output voltage of the comparator ADC remains at low. The 16 results convert to 4-bit digital outputs. Consequently, the different voltage between two inputs of comparator directly affects ADC outputs, so the differential input of comparator is dominant noise victim of ADC. In further chapters, we discuss how much noise is reached to the noise victim from SSN or EMI source and how much ADC performance degradation is occurred by coupled noise. 3-2. Estimation SSN Effects on ADC Figure 6 shows the measurement setup, which consists of an oscilloscope, pulse pattern generators (PPGs), signal generators, power suppliers, and bias tees. The PSN with a power supply voltage is induced to the corner on the PCB substrate using a power supplier, a signal generator, and a bias tee. The ADC outputs are measured by an oscilloscope. We use an analog input that has a 600 mv peak-to-peak voltage, a 1 MHz frequency, and a sine waveform. The power supply at the PSN source has a 200 mv peak-to-peak AC voltage with a 1.2 V DC voltage.

Figure 6. The measurement setup with the vehicle for experimental verification. The SSN source is imported at the corner on the PCB substrate using a signal generator and a bias-tee. The CMOS ADC chip is fabricated using a 0.13 µm CMOS process. The measured ENOB of designed ADC is 3bit, when no SSN is induced. When the SSN is induced, the ADC performance is degraded up to 2bit. To analyze why the performance is degraded by SSN and the degraded level depends on frequency of SSN, the analysis of noise coupling path is essentially needed. However, the noise coupling path is greatly complex, because it includes both on-chip and off-chip elements. To estimate the noise coupling from noise source to noise victim, we can measure it from the on-chip and off-chip integrated system. However, there are several issues which make the system designers find replaced method instead of measurement. First, the additional measurement element of on-chip design can cause unwanted behavior of ADC. Second, there are cost issues, because the additional pattern of design has to be induced for measuring. Lastly, when some problems of design are discovered by the measurement, re-design is needed to fix it and additional time and cost is needed to re-design. Therefore, we propose the co-simulation and the modeling estimation method for replacing measurement. The co-simulation involves the following three steps. First, we assume the SSN source. We use the ideal voltage source defined for the SSN source, and we directly connect it to the power/ground input node of the PCB with a DC voltage. Second, we consider the noise-coupling ratio via the hierarchical Power Distribution Network (PDN). We can estimate the noise-coupling ratio based on the field solver. Third, we simulate the ADC circuit with the formulated SSN on the power/ground of the comparator using Hspice. Also, we propose a model of hierarchical structure for simple, fast, and accurate estimation of SSN coupling on mixed-mode systems. The proposed model can overcome several limitations of measurement and simulation. For example, much transient time is needed to accurately predict the simulated and measured results. Furthermore, greatly

large computational resources are required for the simulation or sometimes the cosimulation is impossible caused by dimensional contrast of PDNs in an on-chip/off-chip hierarchical system. Therefore, the proposed model is a good alternative that can overcome these limitations. 3-3. Modeling for Estimating SSN Effects on ADC Figure 7. The model blocks of the ADC with the hierarchical chip-pcb PDN and the PSN coupling path. To understand and estimate the SSN effects on the ADC, we propose model blocks of SSN coupling path, as described in Figure 7. Node 1 is defined as a power/ground node of the PSN source, and Node 2 is the on-chip power supply node of the ADC. Node 3 is designated as the differential input nodes of the ADC, and the performance factor of the ADC sets the effective number of bits (ENOB), which is a representative performance factor of the ADC [4]. Model block 1 describes the hierarchical PDN, which includes the off-chip PDN and the on-chip PDN, whereas model block 2 describes the on-chip circuit of the ADC. Model block 3 is the ADC behavior model between Node 3 and the ENOB. We use the segmentation method [5], typically used to calculate the impedance, to estimate and analyze the PDN PSN coupling ratio, HPDN(f), from a power/ground of the PSN source (Node 1) to the power/ground of the ADC (Node 2). We use a small-signal model to estimate and analyze the on-chip PSN coupling ratio, HCIN(f), from the power/ground of the ADC (Node 2) to the effective input of the ADC (Node 3). Finally, we use the ENOB parameter for the ADC behavior model, which is expressed as the coupled effective input noise of the ADC (Node 3).

Figure 8. A conceptual model diagram and cross-sectional view of PSN coupling path on a hierarchical PDN (Model 1). Figure 8 describes the Model 1, which is for estimating PSN coupling ratio via hierarchical PDN. To construct Model 1 for estimating the PDN PSN coupling ratio, HPDN, from a noise source (Node 1) to the power/ground of the ADC (Node 2), we use the segmentation method, a modeling method used to calculate the impedance, where the impedances of certain structures the power/ground plane of the PCB, the power/ground bonding wire, the on-chip power/ground rings, and the on-chip decoupling capacitor can be derived from the impedance matrices of partial structures. Using the segmentation method, the calculation time of the proposed model can be effectively reduced, and the limitations imposed by time and computational resources can be overcome. The first segment that we modeled is the power/ground plane of the PCB. The PCB substrate, which consists of 4 layers, measures 3.75 cm by 10 cm. To model the multilayer cavity of the PCB substrate, we used a balanced TLM method. The size of the unit cell for the balanced TLM modeling of the power/ground plane pair is 1.25 mm 1.25 mm, and the maximum targeted sweeping frequency is 3 GHz. The RLGC model parameters are calculated using the dimensions of the unit cell and the material constants referred to in [6]. The second segment is a bonding wire; the PCB PDN and on-chip PDN are interconnected by the bonding wires. The bonding wires are modeled as an inductor and its inductance is related to the wires diameters, lengths, pitches, and heights, as described in [7]. The last segment that we modeled is the on-chip PDN. The model of the on-chip PDN is divided into three model sections: a power/ground ring pair, an on-chip decoupling capacitor, and a MOSFET. The 4th metal layer and 5th metal layer of the chip are used for the power/ground ring. There are several parasitic elements on the on-chip power/ground ring pair. Among them, the dominant RLC elements are the metal resistance and the on-chip decoupling capacitance. The metal inductance is also one of the important parasitic elements; however, it is not considered in this paper since metal

inductance becomes considerable at high frequency analysis, while our target frequency for PSN analysis is under 3 GHz, where inductance is negligible. Also, we designed and modeled an NMOS-type 2.13 nf on-chip decoupling capacitor for the ADC. The model of the unit NMOScap (25 pf) is composed of an oxide capacitor and a series resistor (ESR); the ESR of the unit NMOScap is 10 ohm. In addition, equivalent-circuit models of the CMOS transistor used in the ADC circuit are needed because the on-chip power supply is connected to the nodes of the CMOS transistor; therefore, we use the CMOS equivalent-circuit model [8]. Figure 9. The plots of self-impedance (Z11) extracted by model and measurement. Figure 9 illustrates the self-impedance (Z11) of the hierarchical PDN structure (Model 1) of the Device Under Test (DUT) in this research. These plots illustrate the correlation between the impedance profile estimated by model and measurement. The impedance profile has several resonant points. Resonant point 1 (fr1) is due to the capacitance of the decoupling capacitor and the inductance of the bonding wire. Resonant point 2 (fr2) is due to the plane capacitance of the PCB and the plane inductance of the PCB; the other resonant points are the mode frequencies of the cavity resonance (fm) [9]. The noise coupling ratio can be extracted by impedance profile, referred on equation (1). H V V / I Z CPDN 2 1 21 PDN - (1) VPSN V1 / 1 I Z 11 To construct Model 2 for estimating the SSN coupling ratio, HCIN, from a power/ground of the ADC (Node 2) to the differential input of comparator (Node 3), we use the small signal analysis for comparator circuit. Actually, to design a comparator that is not sensitive to the SSN, the fully balanced impedance between the two input nodes (in+ and in-) of the comparator in the ADC is needed. However, the two input impedances of the comparator cannot be fully matched in a flash-type ADC; one of the comparator inputs

has to be connected to the reference ladder (in+) to determine the level of the analog input, and the other comparator input has to be connected to the analog input line (in-), as shown in Figure 10. Thus, the noise voltage of each comparator input is coupled differently by the SSN, because Zref Zin. Equations (2) to (3) describe the physical parameters of a MOSFET that are defined by circuit theory; Cgs is the gate-to-source capacitance, Cgd is the gate-to-drain capacitance, gm is the transconductance, and ro is the drain resistance of the saturation region [9]. To analyze the PSN coupling in the comparator, we use a small-signal analysis. The coupled noise of the two input nodes in the comparator determine the differential input (Node 3) noise of the comparator in the ADC, which is the difference of the two comparator input noise values, as described by equation (2). We can estimate the on-circuit noise comparator ratio using small-signal analysis referred by equation (3). Figure 10. A model diagram of the on-circuit PSN coupling path (Model 2). V V V - (2) CIN in in

H CIN V V CIN CPDN Z ref Z ref (( ) ( 1/ jwc Z 1/ jwc Z gs 3 Z in Z in ( ) ( 1/ jwc Z 1/ jwc Z gs 2 in ref gd 2 in )*g gd 3 m2 (r o2 //r ref o4 1 )*gm 3(ro 3//ro 5// jwc 1 // jwc gd 2 1 // g m4 )) gd 3 1 // g The previous discussion described the amount of coupling noise relative to the comparator differential noise (VCIN) from the SSN. Thus, we should know the variation in the ADC performance caused by the differential input noise. Therefore, we propose a behavior model (Model 3) of a practical ADC. To construct Model 3 for estimating ENOB of ADC degraded by the differential input noise of comparator (Node 3), we use the definition of ENOB, referred by equation (4). This model is programmed in MATLAB. For a known analog input, clock frequency, and input-coupled noise, determined by the noise-coupling ratio (HPDN and HCIN), the ADC behavior model directly determines the ENOB of the ADC. The ENOB determines the performance level of a practical ADC matched to the performance level of an ideal ADC that has only quantization error, which an ideal ADC also has. The ENOB is directly derived by the signal-to-noise distortion ratio (SNDR), which is a commonly used performance factor. The SNDR is the ratio of the input signal amplitude to the output noise level plus harmonics. m5 - (3) ) 10 log ENOB(bit) 10 ( n V k 1 ana log 2 (akt)/ 6 02. n V CIN k 1 2 (akt)) 176. - (4) 3-4 Analysis of SSN Effects Measurement Simulation Model Estimation Time for 400sample points (Inter Core i7-2600/16gram) Long Time (Need Fabrication) Long Time (200 hours) Short Time (50 mins) Cost High Medium Low Accurate Extremely High High High Table 2: Resource Comparison of Estimation Methods for SSN Effects on ADC (Measurement, Simulation, and Model Estimation) In previous mentions, we discuss how the SSN coupling ratio and ENOB can be measured, simulated, and extracted by proposed model. Table 2 and Figure 11 verify proposed model is good options for estimating SSN effects on ADC. Figure 11 shows the SSN coupling ratio and decreased ENOB. We are certain that the high SSN coupling ratio degrades performance of ADC. There are two remarkable SSN frequency ranges, fr1 and fr2, which degrade badly the performance of ADC. The fr1 and fr2 is the resonant point which is from the impedance profile of hierarchical PDN. The dominant element on Region 1 is the on-chip decoupling capacitance on comparator circuit. The fr1 frequency is determined by the resonant between the capacitance of onchip decoupling capacitor and inductance of bonding wire. Therefore, the dominant elements of Region 2 are inductance of bonding wire and capacitance of PCB. The fr2 frequency is determined by the resonant between the capacitance of PCB and inductance

of PCB. There are some peak points on Region 3, which is generated by the cavity resonance of PCB. Figure 11. Noise coupling ratio and decreased ENOB. Upper plot shows the simulated SSN coupling ratio. Lower plot shows that the measured, simulated, and model extraction results of the decreased ENOB depend on the PSN frequencies. The ENOB is measured by sweeping the single tone SSN from 1 MHz to 3 GHz.

3-5. Estimation of EMI Effects on ADC from WPT There are many possible EMI sources in mixed-mode system, including WPT. Whereas WPT is being considered as a promising power transfer technology option, it can become a critical EMI source in a mixed-mode system. Figure 12 is the conceptual diagram which illustrates the EMI coupling to mixed-mode system. We consider WPT transmitter coil as an EMI source, which is designed with the following specifications summarized in Table 3. Figure 12. Conceptual diagram of radiated field coupling path between WPT and mixed-mode circuit with hierarchical structure. Size Coil Turn Layer Line width Line space Line thickness Inductance Capacitance Resonance Frequency 3cm by 3cm 10 Turns 4 Layers 0.5mm 0.2mm 1/2 oz 56uH 3.55nF 360kHz Table 3: The specification of designed WPT coil (10 turns, 4layers, and spiral type) Even though the resonance frequency is 360 khz, we consider wide frequency s EMI coupling for considering wide band Electro-Magnetic Fields (EMF). EMF is generated at the mode terms of the WPT operating frequency, as is depicted in Figure 13 In order to measure the EMI effects of WPT on the operation of ADC, we assume that a single-tone sine wave, swept from 30 khz to 3 GHz, is supplied to the transmitter coil using a signal generator. Furthermore, we use an analog input that has 600 mv peak-topeak voltage, 1 MHz frequency, and a sine waveform. We use an oscilloscope, pulse pattern generators, signal generators, and power suppliers for measurement. Also, the co-simulation method, which consists of 3D filled solving and spice simulation, can efficiently substitute the actual measurement, while saving cost and time. The cosimulation for estimating the EMI effects on ADC from WPT involves the following

three steps. First, we assume a possible EMI source. In this paper, we design a WPT coil for this step, and convert it as a 3D model (ex. HFSS model). Second, we consider the amount of noise coupled via the radiated path of hierarchical PDN, as well as via the reference voltage plane. The noise-coupling ratio can be estimated by the 3D field solver. Third, we simulate the ADC circuit with the formulated coupled noise on the power/ground or reference input of the comparator using Hspice. Figure 13. The EMF measurement when the WPT coil is operating on the resonant operating frequency of WPT. There is EMF on mode resonances of WPT operating frequency. 3-6 Analysis of EMI Effects on ADC with WPT Figure 14. The path of EMI coupling from WPT on the ADC with the hierarchical chip-pcb-wpt.

We focus on the two EMI coupling paths: one is the path via PDN, and the other is path via reference voltage plane, as described in Figure 14. Through these paths, the coupled noise on victim circuit, the differential input of comparator, can affect the performance of the ADC. For investigating which noise path is dominant in EMI coupling, we compare the amount of noise coupled via each path one by one. First, we consider the EMI coupling effects on ADC via PDN. The WPT input is coupled to power/ground plane, which is shown in Figure 15. The frequency, where the coupling ratio is high, is related to the LC resonant points of the WPT coil and the plane cavity resonances. This coupled noise is transferred to on-chip victim components via bonding wire, on-chip PDN, and MOSFET miller capacitance. Among these paths, the bonding wire restricts the noise coupling of high frequency EMI, whereas the MOSFET miller capacitance blocks the low frequency EMI. When we simulate the performance degradation of ADC, only considering EMI coupling via PDN, the ENOB is decreased down to 0.01 bit with 1kV WPT input (extremely large). Consequently, the EMI coupling effects on ADC via PDN is found to be negligible. Figure 15. Noise coupling ratio from WPT source to power/ground plane of PCB. Second, we consider the EMI coupling via reference voltage plane of PCB. The trend of noise coupling ratio via reference voltage plane (VREF_EMI/Vin_WPT) is similar to that via power/ground plane (VPDN_EMI/Vin_WPT), only difference is the cavity resonance caused by different plane size. This coupled noise is transferred to differential input of comparator, which is the noise victim of comparator, via bonding wire and on-chip interconnection. The bonding wire can restrict the high frequency noise coupling, as was the case for power/ground coupling path. However, unlike power/ground path, there is no series capacitance on this coupling path; in other words, the coupling path via reference

voltage plane is the dominant EMI coupling path on ADC. Via reference voltage plane, the differential input of comparator is fluctuated by the EMI, as shown in Figure 16. Noise coupling ratio and decreased ENOB in Figure 16 is the result when the input to the transmitter coil of WPT is connected to 10 Vpp, swept from 100 khz to 3 GHz. The peak points, which indicate the high sensitivity of ADC to EMI of WPT, are related to the LC resonance of WPT coil, as well as the cavity resonance of reference voltage plane. Figure 16. Noise coupling ratio and decreased ENOB. Upper plot shows the simulated EMI coupling ratio. Lower plot shows that the model extraction results of the decreased ENOB depend on the EMI frequencies. The ENOB is extracted by sweeping the single tone 10Vpp WPT input from 100 khz to 3 GHz.

4. Design Guide for Mixed-mode System for PI We propose the methods for preventing SSN effects and EMI effects on ADC. Some are quite traditional, whereas the others are novel and considerable option for improving PI on mixed-mode system. 4-1. Preventing SSN Effects Most SSN is generated on the operating frequency of the digital circuit and its mode frequencies, as depicted in Figure 17. Therefore, the designer has to concentrate on the noise coupling ratio at the frequencies, at which high noise can be generated by digital circuit. For preventing SSN coupling via PDN, we propose three methods to improve power integrity on ADC. First, if we use bonding wire instead of TSV, low SSN coupling via hierarchical PDN is guaranteed, because bonding wire has inductance value, and it blocks out high frequency noise coupling. However, the high inductance component in bonding wire is detrimental to signal integrity (SI), so the designer has to determine which one is more important to the targeted design among SI and PI. Second, we can insert decoupling capacitor to reduce noise coupling on mid and high frequency. The Figure 18 shows the noise coupling ratio when the proposed methods are applied. From this figure, we can conclude that the structure interconnected by bonding wire and integrated with off-chip decoupling capacitor is the best option, but for more thorough and accurate analysis of ADC performance, consideration of on-chip model is required. Figure 17. The waveform of simultaneous switching current (the operating frequency is 1GHz or 500MHz)

Figure 18. The noise coupling ratio via PDN (HPDN) when the chip and PCB is interconnected to die using boning wire or TSV, and off-chip design includes decoupling capacitor (100nF, 0.9nH, 70mOhm) Previously proposed methods are the ones which decrease the noise coupling ratio via PDN, but it is much more complex and we have to consider both on-chip and off-chip side for applying these methods. So, there is another method that cap be applied which only considers on-chip design for solving PI issue. As we mentioned in the previous chapters, the differential input is the critical node which directly affects the performance of ADC. By its nature, differential input subtracts vin- voltage from vin+ voltage and can act as a good noise isolator. In other words, when the noise is equally coupled to the two input nodes of the comparator, the differential input noise is ideally zero, when Zref = Zin. For adopting impedance balancing technique, additional impedance elements have to be inserted in the circuit design for reducing differential input noise, as shown in Figure 19. Figure 19. Schematic of the comparator used in designed ADC with proposed impedance balancing technique for reducing differential input noise. 4-2. Preventing EMI Effects To prevent the EMI effects, such as the ones generated from EMF, there are several methods we propose. First, the bonding wire interconnection is good for reducing EMI effects on ADC, as the series inductance from bonding wire effectively reduces the high frequency noise coupling. Second, we have to avoid the plane cavity resonances of the reference voltage plane, since they are the critical frequency range at which high noise can be coupled. Therefore, the size of the reference voltage plane has to be determined

for thorough analysis of its cavity resonance frequency, in order to avoid large EMI field. Lastly, we have to consider the resonant frequency of WPT source. The interaction between large L source and copper plane change the resonant frequency of the source. This effect is generated by the eddy current on PCB plane and it reduces the effective inductance value of the source coil, which is the main reason the operating frequency of WPT is increased from 380 khz to 630 khz, as shown in Figure 20. Figure 20. The self-impedance of WPT coil on the normal condition or the condition with PCB copper plane (distance: 1mm) 5. Conclusion In this paper, we discussed how we can analyze the PI issues on ADC with hierarchical structure, and how we can improve PI characteristic. The problems of PI are more complex than that of SI, because there are many noise sources and the noise coupling path is much more complex. When we focus on each noise source and noise path, we can simplify the analysis of PI problems. Therefore, we focused on the SSN and EMI coupling, and we proposed the estimation method of external noise coupling on ADC with hierarchical structure. Furthermore, we proposed several methods that can be adopted to improve PI characteristic. The proposed methods were successfully verified using simulation and measurements. 6. Reference [1] Tummala, R.R.; Swaminathan, M.; Tentzeris, M.M.; Laskar, J.; Gee-Kung Chang; Sitaraman, S.; Keezer, D.; Guidotti, D.; Zhaoran Huang; Kyutae Lim; Lixi Wan; Bhattacharya, S.K.; Sundaram, V.; Fuhan Liu; Raj, P.M.;, "The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade," Advanced Packaging, IEEE Transactions on, vol.27, no.2, pp. 250-267, May 2004

[2] Swaminathan, M.; Joungho Kim; Novak, I.; Libous, J.P.;, "Power distribution networks for system-on-package: status and challenges," Advanced Packaging, IEEE Transactions on, vol.27, no.2, pp. 286-300, May 2004 [3] Kyoungchoul Koo, Myunghoi Kim, Joungho Kim, Vertical Noise Coupling from On-chip Switching-Mode Power Supply in a Mixed-Signal Stacked 3D-IC, IEC DesignCon 2012, Santa Clara, February 2012. [4] Platonov, A.; Malkiewicz, L.;, "Particularities of the Cyclic A/D Converters ENOB Definition and Measurement," Instrumentation and Measurement Technology Conference, 2006. IMTC 2006. Proceedings of the IEEE, vol., no., pp.894-899, 24-27 April 2006 [5] Jaemin Kim; Woojin Lee; Yujeong Shim; Jongjoo Shim; Kiyeong Kim; Jun So Pak; Joungho Kim;, "Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method," Advanced Packaging, IEEE Transactions on, vol.33, no.3, pp.647-659, Aug. 2010 [6] Joong-Ho Kim; Swaminathan, M.;, "Modeling of multilayered power distribution planes using transmission matrix method," Advanced Packaging, IEEE Transactions on, vol.25, no.2, pp. 189-199, May 2002 [7] Stephen H. Hall, Garrett W. Hall, and James A. McCall, High Speed Digital System Design. New York: Wiley [8] Villar, G.; Alarcon, E.; Guinjoan, F.; Poveda, A.;, "Optimized design of MOS capacitors in standard CMOS technology and evaluation of their Equivalent Series Resistance for power applications," Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, vol.3, no., pp. III-451- III-454 vol.3, 25-28 May 2003 [9] Yujeong Shim; Jongbae Park; Jaemin Kim; Eakhwan Song; Jeongsik Yoo; Junso Pak; Joungho Kim;, "Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package," Electromagnetic Compatibility, IEEE Transactions on, vol.51, no.3, pp.763-773, Aug. 2009 [10]Bumhee Bae; Yujeong Shim; Woojin Lee; Kyoungchoul Koo; Woojin Ahn; Joungho Kim;, "Hybrid modeling and analysis of power supply noise effects on analog-todigital converter considering hierarchical PDNs," Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010