A 15.5 db, Wide Signal Swing, Dynamic Amplifier Using a Common- Mode Voltage Detection Technique James Lin, Masaya Miyahara and Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada Laḃ
Outline Motivation Background Design Concept Circuit Implementation Conclusion 2
Supply voltage (V) Roadmap ITRS s roadmap for future supply voltage [1] What are some foreseeable difficulties? [2] 1.2 1.0 0.8 0.6 2010 2015 2020 2025 Year [1] ITRS, 2010 [2] A. Matsuzawa, ISSCC 2011 Forum 3
Output voltage swing (V P-P ) Conventional Amplifier Amplifier design becomes increasingly difficult with supply voltage lowering 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Supply voltage (V) 4
Conventional Signal Swing and Linearity Stacked architecture limits signal swing V DD PMOS 0.15 V (V effp ) V DD (1.2 V) V OUTN V INP R L R L V OUTP V INN Bias Voltage Maximum Voltage Swing 0.375 V 0.375 V V b 2 X NMOS 0.3 V (V effn ) [3] B. Razavi, McGraw-Hill V eff = V GS -V T Gnd 5
Motivation Ultra low voltage operation (0.5 V) Minimally stacked architecture Scalable power dissipation with speed Dynamic operation for mixed-signal applications Dynamic amplifier A minimally stacked amplifier with variable power consumption is proposed 6
Conventional Applications Conventional applications: Pre-amplifiers for dynamic comparators [4] Receiver amplifiers for DRAM circuits [5] V DD Pre-charge Phase Amplification Phase V INP CLK CLK V 1 V 2 Latches V INN V OUTP V OUTN Voltage Clock V 2 V 1 Time [4] B. Razavi, IEEE Press [5] H. Fujisawa et al., ESSCIRC 2000 7
Proposed Waveform If discharging can be terminated A single stage amplifier can be realized Pre-charge Phase Amplification Phase Pre-charge Phase Amplification Phase Pre-charge Phase Amplification Phase V 2 Voltage Clock V 2 Voltage Clock V 2 Voltage VOUT Clock V oc V 1 VOUT V 1 V 1 V oc Time Time Time 8
Proposed Architecture A common-mode voltage detector with sampling switches realize dynamic amplification V DD M5 CLK M6 C L V 1 V INP M3 I D1 Common- Mode Voltage Detector I D2 V INN M4 V 2 C L M2 CLK M1 9
Conventional @ 0.5 V Proposed @ 0.5 V Conventional @ 1.2 V Proposed @ 1.2 V Signal Swing and Linearity Minimally stacked architecture gives extra margin for signal swing Drain-Source Current, IDS Drain-Source Current, IDS Linear Region 2 X V effn 0.3 V Linear Region 2 X V effn 0.3 V Saturation Region Maximum Voltage Swing 0.75 V Drain-Source Voltage, V DS Saturation Region 0.05 V V effp 0.15 V V DD (0.5 V) Drain-Source Voltage, V DS V effp 0.15 V V b V DD (1.2 V) Drain-Source Current, IDS Drain-Source Current, IDS Linear Region V effn 0.15 V Linear Region V effn 0.15 V Saturation Region 0.3 V Saturation Region Drain-Source Voltage, V DS V oc Maximum Voltage Swing 1 V V oc V DD (1.2 V) V DD (0.5 V) Drain-Source Voltage, V DS 10
Gain (V/V) Gain G = diff 2 V -V DD V eff oc 6 5 Clipping G diff : V DD : V oc : V eff : differential gain supply voltage common-mode (CM) output voltage effective gate voltage, which is gate-source voltage minus threshold voltage V DD = 1.2 V V eff = V DD /2 - V thn 4 3 2 1 0 0.0 0.2 0.4 0.6 0.8 1.0 V DD -V oc (V) C L =50 ff C L =100 ff C L =150 ff C L =200 ff 11
Gain (db) Signal Swing and Linearity Wider signal swing, especially in low voltage operation 18 16 14 12 10 8 6 4 2 0-2 -4-6 -1 0 1 Output voltage (V) (V) Proposed, 1.2 V Conv., 1.2 V Proposed, 0.7 V Conv., 0.7 V Proposed, 0.5 V Conv., 0.5 V f s = 50 MHz V ic = V DD /2 12
Gain (db) 17 16 15 14 13 12 11 10 9 8 7 Speed Key applications: Mixed-signal circuits C L = 50 ff (1.2 V) C L = 100 ff (1.2 V) C L = 150 ff (1.2 V) C L = 200 ff (1.2 V) 100M 1G 10G f = S V ic = V DD /2 2 IDCM V -V C +C DD oc L P C L = 100 ff (0.5 V) f S : operating/clock frequency I DCM : CM drain current C L : load capacitance C P : parasitic capacitance V id : diff.-mode (DM) input voltage Frequency (Hz) V ic : CM input voltage V id = 0.1 V 13
Power dissipation (mw) Power Dissipation Scalable power dissipation due to dynamic operation 1 0.1 0.01 1E-3 Conv. (1.2 V) Conv. (0.7 V) Proposed (1.2 V) Proposed (0.7 V) Proposed (0.5 V) 10M 100M 1G Frequency (Hz) Incomplete amplification P (f ) = T S P (f )+ P (f ) Amp S CMD S P T : total power dissipation P Amp : power dissipation in amplifier circuit P CMD : power dissipation in logic circuit 14
Power Dissipation, cont d V DD Φ1 Φ 2 V oc A dynamic amplifier can save energy V DD Voltage Pre-charge Phase Clock Time C L +C P1 Amplification Phase V oc P 2 CMD S L2 DD P = Amp 2 = f C V C L +CP1fSΔV VDD - ΔV 2 C P1 : parasitic capacitance C L2 : common-mode detector s load capacitance ΔV: V DD -V oc 15
Voltage (V) Effects of Delay Delay causes a gain error and a CM output voltage shiftc 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Clock t 1 t 2 Δt -0.2 0.0 100.0p 200.0p 300.0p 400.0p Time (s) V OUT1 V OUT2 I D1 - ID2 V = V -V IDCM OUT DD oc + I - I D1 CL V oc shift D2 t d 16
Circuit Implementation Parasitic capacitance causes a commonvoltage error V OUTN CLK C L V INP M3 CLK V DD M5 M7 M6 V C 0 V C 0 1 X V 2 M2 M1 C PX V INN M4 V OUTP C L C 0 : C PX : V = X 1 C 1+ 2C PX 0 0 PX V +V 2 1 2 C + PX V 2C +C DD common-mode detector s sampling capacitor parasitic capacitance at node X 17
Sampling Capacitor Mismatch Capacitor mismatch causes a gain error C 0 -ΔC/2 C 0 +ΔC/2 V X V 1 V 2 C PX Pre-charge phase: V = V = V = V 1 2 X DD Q = C V X PX DD ' Q X = QX ΔC C V +C V +V - V -V V = 2 X 2C +C Amplification phase: PX DD 0 1 2 1 2 0 PX 1 V 1 +V2 CPX ΔC V1-V2 V X = + VDD - C PX 1+ 2 2C 0 +CPX 2C 0 +CPX 2 2C 0 18
Input-referred offset voltage (mv) Mismatch Calibration 5.59 mv (s 1.27 mv (s V DD CLK M5 M7 M6 20 15 V OUTN C V 0 C 1 V 0 X V 2 V OUTP 10 C L C L 5 0 inv_b -5-10 Counter V INP M3 DAC DAC M8 inv_b CLK V C M9 M2 M1 V INN M4 Uncalibrated -15 Calibrated -20 0 20 40 60 80 Number 19
Gain Control 3 db gain control Gain (db) CLK V DD M5 M7 M6 15 V OUTN C V 0 C 1 V 0 X V 2 V OUTP 14 C L C L 13 12 inv_b 11 V INP M8 V C M9 V INN 10 0.4 0.6 0.8 1.0 1.2 Bias voltage for gain control, Vc (V) Counter M3 DAC DAC inv_b CLK M2 M1 M4 20
Output voltage swing (V P-P ) Conclusion A dynamic amplifier realizes 0.5 V ultra low voltage operation Wider signal swing Variable power dissipation for clock scalable circuits 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 Dynamic amplifier 0.5 V P-P Conv. amplifier 0.4 0.2 0.0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Supply voltage (V) 21
Future Work Low-voltage ADC using dynamic amplifiers Other RF applications such as sampling mixers 22
References [1] International Technology Roadmap for Semiconductors, 2010 update RF and analog mixed-signal CMOS technology requirements, Dec. 2009. [2] A. Matsuzawa, An ultra low power analog and ADC design, ISSCC Forum, Feb. 2011. [3]B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, 2001. [4]B. Razavi, Principle of data conversion system design, IEEE Press, 1994. [5]H. Fujisawa, T. Takahashi, M. Nakamura, and K. Kajigaya, A dual phase-controlled dynamic latched (DDL) amplifier for high-speed and low-power DRAMs, Proc. 26 th Eur. Solid-State Circuits Conf., pp. 184-187, Sept. 2000. 23
Thank you for your interest! James Lin, james@ssc.pe.titech.ac.jp 24