Digital PWM controller with one-bit noise-shaping interface

Analog Integr Circ Sig Process (2006) 49:11 17 DOI 10.1007/s10470-006-8698-0 Digital PWM controller with one-bit noise-shaping interface Jeongjin Roh Received: 24 August 2005 / Revised: 27 March 2006 / Accepted: 6 April 2006 / Published online: 27 June 2006 C Science + Business Media, LLC 2006 Abstract Conventionally, pulse width modulation (PWM) controllers for DC-DC switching power converters have been implemented in pure analog circuits. However, recent research showed the possibility of digital controllers with several advantages such as robustness, fast design time, and high flexibility. Since DC-DC converted output voltage is analog in nature, an analog-to-digital interface circuit is always essential even in digital PWM controllers. A simple and efficient delta-sigma modulator is used as a conversion circuit in our silicon implementation. Measurement results show good voltage regulations. Keywords DC-DC converter. Pulse width modulation. Buck converter. Delta-sigma modulation. Noise shaping 1. Introduction Switching power converters are becoming more important because of the popularity of battery-operated systems. Conventional analog PWM controllers have been used for a long time, and they have been successfully used in more than millions of commercial products. However, analog circuits are known to be difficult to design with a long design time. Also, analog circuits are sensitive to noise and component variations. Recently, in order to overcome these drawbacks, the possibility of digital PWM controllers are studied and demonstrated [1 10]. The digital controllers can be designed using a hardware description language (HDL), and can be ported to new processes without too much difficulty. Even J. Roh ( ) Department of Electrical and Computer Engineering, Hanyang University, Ansan, Korea e-mail: jroh@hanyang.ac.kr for the digital controllers, however, an essential analog block is the analog-to-digital converter (ADC), which interfaces the DC-DC converted analog output voltage with the digital controller. In this paper, we demonstrate an efficient interface technique to reduce the complexity of conventional ADCs. Figure 1 shows architecture of general digital controllers with a power output stage and a LC filter, which is commonly called as a buck converter. The resistor R models the load of the buck converter. Compared to conventional analog controllers [12], most blocks are replaced by their digital counterparts. However, the digital controller requires an ADC to interface the analog output voltage with digital control logics. In order to have accurate control of output voltage, we need a high resolution ADC with complex analog circuitry. When supply voltage is very low and power consumption has to be minimized, design of ADC becomes even more troublesome. In general, 6 8 bit ADCs are commonly used for digital controllers as a trade-off between the control accuracy and the hardware complexity. A comparator, which is one-bit ADC, is the simplest circuit to convert the analog voltage to digital signal. Dancy et al. [5] had tried a comparator for the digital controller, but the oscillation problem occurred and the comparator was not used anymore in their later work. Their solution to the oscillation problem was to use the 7 bit charge redistribution ADC instead of a comparator. The ADCs are typical analog circuit, and ADC design would be the major bottleneck in digital controller development. A deadzone comparator [10] was proposed as an interface circuit without the oscillation problem of the comparator. Theoretical analysis was provided for the required size of deadzone in stable operation. However, it also showed that the size of deadzone should be proportional to the output load. Therefore, design of controller for wide output load variation would not be simple.

12 Analog Integr Circ Sig Process (2006) 49:11 17 Fig. 1 Digitally controlled DC-DC converter In this paper, we demonstrate one-bit noise-shaping interface circuit by using a delta-sigma modulator (DSM). Traditionally, the DSM has been used for high resolution ADCs with relatively low analog complexity but with complex digital lowpass filters [14]. The advantage of low analog complexity makes it a good interface circuit for digital controllers. 2. Digital controller with one-bit interface The design of ADC would be a major bottleneck in the integrated circuit (IC) development of controllers since analog circuit design heavily depends on circuit designers while digital design is highly automated. The delta-sigma modulation has been widely used in high resolution ADC circuits. The DSM technique is well known for the simplicity of analog circuits at the cost of higher digital complexity. Figures 2 and 3 show block diagrams of a DSM and its linearized model, respectively. It is a first-order modulator with a single integrator. If more integrators are implemented, higher-order modulators can be designed at the cost of more power, a larger area, and a longer design time. The simple first-order modulator is sufficient in our application. Figure 4 shows a switched-capacitor circuit example. In addition to an op amp, extra analog components are switches, capacitors, and a comparator. Since the non-overlapping clocks, φ1 and φ2, and the switched-capacitor circuits are commonly used in circuit designs, details of them are not discussed here. The hardware complexity of a DSM is significantly less than that of flash ADCs used in conventional digital controllers. The analysis of a delta-sigma modulator is straightforward from Fig. 3 [14], and summarized below, where E(z) is the quantization noise of the comparator. input signal except a simple delay. The noise transfer function (NTF) in Eq. (2) can be evaluated in frequency domain by setting z = e j2π f/f s, where f s is the sampling frequency. This gives [14] ( ) π f NTF( f ) = 2sin (3) f s The quantization noise will be noise-shaped by NTF(f), so in low frequency signal band, large attenuation of quantization noise can be achieved. However, the quantization noise attenuation is only effective at low frequency band in DSM, and high frequency noise is increased according to Eq. (3). Therefore, in most DSM applications, especially in high resolution DSM analog-to-digital converters, digital filtering is essential to remove high frequency noise. High frequency noise is removed by digital filters that follow the modulator. Y 1 (z) = 1 M ( 1 + z 1 + z 2 + +z (M 1)) V (z) (4) Fig. 2 ( = 1 M 1 M i=0 z i ) V (z) (5) First-order delta-sigma modulator STF(z) = V (z) U(z) = z 1 (1) Fig. 3 Linearized Z-domain model of a DSM NTF(z) = V (z) E(z) = 1 z 1 (2) Equation (1) is called a signal transfer function (STF), and it shows that the output of the modulator is same as the Fig. 4 Switched-capacitor circuit implementation of a DSM

Analog Integr Circ Sig Process (2006) 49:11 17 13 Fig. 5 Digital filters in general DSM applications Fig. 8 Mathematical model of a digitally controlled DC-DC converter Fig. 6 Sinc filter response Fig. 7 Filtering functions in digitally controlled DC-DC converters Fig. 9 Differential amplifier to sense output voltage error The two-stage digital filter implementation in Fig. 5 is widely used in audio and voice codec applications. A single stage digital filter can be designed, but because of hardware complexity, sinc filter is almost always used as a first stage filter [14]. The equation for sinc filter is in Eq. (5) and its frequency response is in Fig. 6. As we can see from Fig. 6, sinc filter is a crude lowpass filter. Even though the characteristic of the lowpass filter is far from ideal one, the main advantage is that it does not require any multiplier as we can see from Eq. (5). If we select M as a power of two, the division operation can be a simple shift right operation in binary digital logic. In DSM applications for DC-DC converters, the signal band is limited only to DC. Therefore, digital filtering scheme can be further optimized in this case. As the signal band in DC-DC converter is very narrow, we can use digital integrator as a lowpass filter. The digital integrator can be easily implemented as an accumulator as in Eq. (7). The overall noise-shaping and filtering architecture is shown in Fig. 7. We can observe that there is no extra need for digital filters in DC-DC applications because the digital integrator is already an essential block in the digital controller as it will be described below. The analog LC filter is also a part of the switching power converter. Remaining high frequency noise is removed by the analog LC filter. niques using complex proportional-integral-derivative (PID) controller [11] can also be implemented if it is required. Figure 8 shows a mathematical model for the digitally controlled DC-DC converter. ADC in Fig. 1 is replaced by STF and NTF blocks, and the digital blocks are replaced by an integrator K(s). The L and C in Fig. 1 are combined with a load resistor R and shown as a second-order RLC block L(s). Since the feedback system requires a subtractor for V ref and V out, an additional block is designed as in Fig. 9. The system analysis shows that the transfer function for V ref is: H1 = V out STF K (s) L(s) = V ref 1 + STF K (s) L(s) Similarly, the transfer function for the quantization noise V e is: H2 = V out NTF K (s) L(s) = V e 1 + STF K (s) L(s) Since the dc-dc converter in Fig. 8 is a mixture of continuoustime functions and discrete-time functions, we applied bilinear transformation to convert the discrete-time functions into analog representations. The digital integrator can be modeled as [5] (8) (9) Y (z) = (1 + z 1 + z 2 + z 3 + )V (z) (6) K (s) = K s (10) ( ) = z i V (z) (7) i=0 The DSM is used as an ADC in Fig. 1. The control law of the digital controller in our implementation is an integral controller as in [5]. The general digital controller design tech- The gain K of the integrator is K = d T CNT (11) where d is the duty cycle resolution of the PWM generator and T CNT is the period of the counter clock. If d is small, we can have fine control of output voltage, but the loop

14 Analog Integr Circ Sig Process (2006) 49:11 17 gain will be reduced and feedback response will be slow. For example, 7 bit PWM control has a duty cycle resolution of 3 V/2 7 = 23 mv, while 10 bit PWM has a resolution of 3V/2 10 = 2.9 mv. The different output responses for two PWM controllers are shown in next section. If both high output resolution and fast feedback response are required, the clock frequency of the DSM and the digital integrator can be increased as well as increasing the bit size N. In our implementation, same clock is used for all blocks for simplicity. Once the discrete-time functions are converted to continuous-time functions, the complete feedback loop can be analyzed. The frequency response of Eqs. (8) and (9) are shown in Figs. 10 and 11, respectively. These figures show that the output voltage equals the DC reference voltage V ref and that the quantization noise is significantly attenuated especially at DC. Because of the quantization noise-shaping, the one bit interface of DSM can be used as an accurate analog-to-digital interface circuit. Fig. 12 Digital controller architecture Fig. 13 Non-overlapping control circuit Fig. 10 Magnitude function of H1 Figure 12 shows the architecture of a digital controller. The digital integrator is the implementation of the control law block, and others are the implementation of the PWM duty control block in Fig. 1. The delay line is composed of 2 N unit delay elements. The short clock pulse sets the latch periodically, and the multiplexer selects the delayed signal that resets the latch. The single delay element has two inverters in it, and its power line is controlled by a linear regulator. This PWM duty control scheme is widely used in digital controllers [4, 5, 7]. Figure 13 shows the control circuit to drive the large PMOS and NMOS transistors in Fig. 1. The SR latch is the set/reset block in Fig. 12, and repeated for convenience. We have added two extra control logics to the general digital controller architecture. First is the hold control signal for the integrator as shown in Fig. 14. In stable state, the output of the differential amplifier in Fig. 9 will be the commonmode voltage, and the DSM output will be a sequence of 10 1010...This sequence will keep change the value of the integrator. Since the digital integrator directly controls the multiplexer, any change in the integrator will affect the duty ratio. This can cause unstable output voltage oscillation. In order to prevent this unwanted instability, we have added Fig. 11 Noise-shaping property of H2 Fig. 14 Up, down, and hold control of digital integrator

Analog Integr Circ Sig Process (2006) 49:11 17 15 hold signal to the integrator. Two output bits from the DSM block will be combined to generate the control signals. If two output bits are 1 1,an up control signal will be generated, and the integrator will be increased by 1. On the contrary, if output bits are 00,adown signal will be generated to decrease the integrator. For 10or 01output, a hold signal will be generated instead of a consecutive increase and decrease of the integrator. Second is the protection of overflow and underflow of the integrator. For example, 7 bit integrator should be limited to 127 as a maximum value, so the up signal is disabled when maximum value is reached. The same limit is applied to 0. The down control is disabled in this case. The hold control and the overflow and underflow protection are typical nonlinear actions. These nonlinear effects are not modeled in the previous frequency analysis, therefore, the frequency analysis has some limitations. In addition, the analysis also has a limitation in the analyzing the effect of tonal content in the firstorder DSM. Dithering would help to alleviate the concern at the cost of additional hardware. The DC-DC converter output signal contains ripple at the sampling frequency and its harmonics are folding back to the DSM, so extra quantization noise may fold back to low frequency. These DSM-related problems are not easy to analyze since the whole DC-DC converter is a complex continuous and discrete-time mixed system. The analysis of these issues is left as a future research topic and they are not further discussed in this paper. Time domain behavioral simulations are performed and studied, and a prototype board was assembled as shown in Fig. 15. The prototype board has a FPGA, which operates as a digital controller, and an analog modulator that is assembled with discrete analog components. The FPGA digital controller in the board was programmed and tested for different voltage and load conditions. The up/down/hold control and the overflow/underflow detection are all implemented and evaluated using the prototype board before the fabrication of the silicon chip. The final silicon chip in next section shows that the operations are very stable. 3. Experimental results Measurement results are shown in this section. A 20 µh inductor and a 22 µf capacitor are used for a LC filter with 500 khz switching frequency. Both 7 bit and 10 bit PWM controller chips are implemented in standard 0.35 µm CMOS process. Figure 16 shows a die photo of the developed DC- DC converter. The lower half of the chip shows the 7 bit PWM controller. The analog-digital interface block is located on the bottom right corner, and the digital block is on the bottom left corner of the chip. The PMOS and NMOS power transistors are also shown. The upper half of the chip has duplicate blocks for 10 bit PWM control and debugging purpose. The quiescent current of the analog-to-digital interface circuit is 230 µa. In measurement plots except the last one, the upper trace shows the DC-DC converter output voltage, while the lower trace shows the voltage or current signal that is changing. The load regulation performance is shown in Fig. 17 for the 7 bit PWM control. The input and reference voltages are set to 3.0 V and 1.5 V, respectively, and load current is changed from 75 ma to 275 ma and back to 75 ma. For the step load current change, the output voltage experiences about 200 mv variation. Then, the output voltage recovers in 300 µs and follows the reference voltage. The load current is controlled by resistors and switches, and measured by a small sense resistor. The spike at the rising edge of the load current is caused by the switching control of the load. The 10 bit PWM control in Fig. 18 also shows a good load Fig. 15 Photograph of a prototype board

16 Analog Integr Circ Sig Process (2006) 49:11 17 Fig. 18 Load regulation with 10 bit PWM control Fig. 16 Die photograph regulation performance. However, as Eq. (11) showed that the integrator gain is reduced in 10 bit PWM, the overall loop gain is also affected by the integrator gain reduction. The gain reduction is about 1/8, and as a result, the response time of the 10 bit PWM is about 8 times longer than that of the 7 bit PWM. Figures 17 and 18 may seem similar, but close attention reveals that the time scale is different for both plots. One is with 200 µs/div scale while another is with 1 ms/div scale. Same scales apply to next two plots. The reference voltage V ref is changed in Figs. 19 and 20. As V ref changes from 1.5 V to 2.0 V, the output voltage exactly follows the reference voltage in about 300 µs as before. The 10 bit PWM result in Fig. 20 also shows a good performance but with a longer response time as before. Fig. 19 Reference voltage change with 7 bit PWM control Fig. 17 Load regulation with 7 bit PWM control Fig. 20 Reference voltage change with 10 bit PWM control

Analog Integr Circ Sig Process (2006) 49:11 17 17 Fig. 21 500 khz switching ripple in output voltage The 500 khz output voltage ripple in Fig. 21 proves a stable operation of our digitally controlled DC-DC converter. It shows unavoidable switching noise that is generated when power transistors turn on and off. Upper trace shows the output voltage with a 200 mv/div scale, and the lower trace shows it with zoomed scale. Since the output voltage is half of the input voltage, the duty cycle of the DC-DC converter needs to be 0.5. The voltage ripple in Fig. 21 shows the 50% duty cycle as expected. 4. Conclusions An efficient analog-to-digital interface circuit is implemented for digitally controlled DC-DC converters. Instead of conventional flash-type ADCs, the 1 bit delta-sigma modulator effectively converts the error voltage to digital signal for digital feedback controllers. Mathematical analysis of the system is provided and silicon chip is implemented. Measurement results of the chip show good output voltage regulations of the developed digitally controlled DC-DC converter. Acknowledgments The authors would like to thank valuable comments from anonymous reviewers. This work was supported by the second-phase Brain Korea 21 project in 2006. References 1. J. Kim and M.A. Horowitz, An efficient digital sliding controller for adaptive power-supply regulation. IEEE J. of Solid-State Circuits, vol. 37, pp. 639 647, May 2002. 2. S. Bibian and H. Jin, High performance predictive dead-beat digital controller for DC power supplies. IEEE Trans. on Power Electronics, vol. 17, pp. 420 427, May 2002. 3. B.J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, Highfrequency digital PWM controller IC for DC-DC converters. IEEE Trans. on Power Electronics, vol. 18, pp. 438 446, Jan. 2003. 4. A. Syed, E. Ahmed, and D. Maksimovic, Digital PWM controller with feed-forward compensation. Applied Power Electronics Conference, pp. 60 66, 2004. 5. A.P. Dancy, R. Amirtharajah, and A.P. Chandrakasan, Highefficiency multiple-output DC-DC conversion for low-voltage systems. IEEE Trans. on Very Large Scale Integration Systems, vol. 8, pp. 252 263, June 2000. 6. G.-Y. Wei and M. Horowitz, A fully digital, energy-efficient, adaptive power-supply regulator. IEEE J. Solid-State Circuits, vol. 34, pp. 520 528, 1999. 7. A.V. Peterchev, J. Xiao, and S.R. Sanders, Architecture and IC implementation of a digital VRM controller. IEEE Trans. on Power Electronics, vol. 18, pp. 356 364, Jan. 2003. 8. K. Kutluay, I. Cadirci, A. Yafavi, and Y. Cadirci, Digital control of universal telecommunication power supplies using dual 8-bit microcontrollers. Industry Application Conference, pp. 1197 1204, 2002. 9. A.V. Peterchev and S.R. Sanders, Quantization resolution and limit cycling in digitally controller PWM converters. Power Electronics Specialists Conference, pp. 465 471, 2001. 10. J. Roh, S.-D. Lee, and S. Park, Digital PWM controller for DC- DC converters with minimum analogue circuits. IEE Electronics Letters, vol. 39, pp. 1402 1403, 2003. 11. G.F. Franklin, J.D. Powell, and M. Workman, Digital Control of Dynamic Systems, 3rd edition. Addison-Wesley, 1998. 12. R.W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd edition. KAP, 2001. 13. A.I. Pressman, Switching Power Supply Design, 2nd edition. McGraw-Hill, 1998. 14. S.R. Norsworthy, R. Schreier, and G.C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. IEEE Press, 1996. Jeongjin Roh received the B.S degree in electrical engineering from the Hanyang University, Korea, in 1990, the M.S. degree in electrical engineering from the Pennsylvania State University in 1998, and the Ph.D. degree in computer engineering from the University of Texas at Austin in 2001. From 1990 to 1996, he worked at Samsung Electronics in Kiheung, Korea, as a senior circuit designer for several mixed-signal products. From 2000 to 2001, he worked at Intel Corporation in Austin, Texas, as a senior analog designer for wireless communication circuits. In 2001, he joined the faculty at the Hanyang University in Ansan, Korea. His research interests include low-power analog circuits, power management ICs, and oversampled delta-sigma converters.