HIGH PERFORMANCE ADDER USING VARIABLE THRESHOLD MOSFET IN 45NM TECHNOLOGY

Internatonal Journal of Electrcal, Electroncs and Computer Systems, (IJEECS) HIGH PERFORMANCE ADDER USING VARIABLE THRESHOLD MOSFET IN 45NM TECHNOLOGY 1 Supryo Srman, 2 Dptendu Ku. Kundu, 3 Saradndu Panda, 4 Bansbadan Maj, 5 Assh Ku. Mukhopadhyay 123 Electroncs and Communcaton Department, Narula Insttute of Technology, Kolkata, Inda 4 Professor & Head, Dept. of Electroncs and Communcaton Engneerng, NIT, Durgapur, Inda 5 Drector, BITM Santnketan, Brbhum, West Bengal, Inda Emal : 1 srman.supryo@gmal.com, 2 dptendukumarkundu@gmal.com, 3 saradndupanda@gmal.com, 4 bmajecent@yahoo.com, 5 askm55@gmal.com Abstract In the modern tme desgnng a crcut that consumes less power wth mnmum delay and nose s one of the major challenges. Normally the crcuts are desgn n CMOS technology. But we know Dynamc Threshold MOSFET (DTMOS) consumes less power than CMOS as t s operated n sub-threshold regon and the leakage current s used for ts computatonal operaton. Now to reduce the power consumpton further and acheve an ultra-low power regon of operaton Varable Threshold MOSFET () s ntroduced. In ths paper we desgn a Conventonal Full adder and Eght transstor Full adder(8t) crcut usng and desgn a parallel Adder and Subtractor usng ths Full adder and calculated ts nose, power and delay n T-spce. Keywords CMOS, DTMOS,, T-SPICE. I. INTRODUCTION In the modern era, operatng a MOSFET n low power regon s the prme objectve of the research feld. Ths advantage of low power MOSFET s especally attractve for developng medcal devces lke (Hearng ads, pacemakers etc.), sensors and devces [1]. In the normal MOSFET t s not possble to attan a low power operaton because there we have to operate the MOSFET after ts threshold voltage lmt and s some leakage current also flow to the devce, both of them leads to more power. So, f we can operate the transstor below ts threshold voltage the power consumpton wll automatcally reduce. To mplement ths concept DTMOS s ntroduced, where the MOSFET s to operate n the sub- threshold regon and the leakage current s used as computatonal current n crcuts. Now f we gve a proper bas voltage appled between gate and substrate, t leads to lowerng operatng currents and power dsspaton. Ths arrangement s called as. In normal NMOS, Fg. 1, the substrate s usually connected to ground or n the lowest potental of the crcut and n PMOS; the substrate s generally connected to supply voltage or the hghest potental n the crcut. The symbol of DTMOS s gven n Fg.2 the substrate s always n gate potental. When DTMOS s on, the threshold s reduced and the current s ncreased and propagaton delay decreased. When the transstor s OFF, the threshold s rased, reducng leakage current and mnmzng power and energy dsspaton. s nothng but an extenson of DTMOS n the sense that the substrate voltage always dffers by a fx voltage from the gate voltage. As shown n Fg 3, by connectng postve bas between gate and substrate for NMOS and negatve bas between gate and substrate for PMOS, there s rapd reducton of power dsspaton n when compared to DTMOS and tradtonal CMOS. The crcut s named as because, we have used the same DTMOS wth a based voltage between gate and substrate.the voltage of each transstor s dynamcally adjusted dependng on gate voltage, causng the threshold voltage of devce to adjust dynamcally. In ths paper, we have desgned and mplement the for desgnng the full adder (conventonal and 8T) and a Parallel adder Subtractor and smulate and power, delay measure of the crcut n T-spce and compare and analyze the result wth conventonal approach and show the usefulness of n term of power consumpton and delay and nose. ISSN (Onlne): 2347-2820, Volume -1, Issue-2, 2013 34

Internatonal Journal of Electrcal, Electroncs and Computer Systems, (IJEECS) conductng channel. The output characterstc of PMOS transstor s shown n Fg.6. Fg.1. Structure of Conventonal PMOS and NMOS Fg.4.Output characterstc of VTNMOS Fg.2. Structure of DTPMOS and DTNMOS Fg.5. Input characterstc of VTNMOS Fg.3. Structure of VTPMOS and VTNMOS II. CURRENT VOLTAGE (I-V) CHARACTERISTIC For evaluatng the I-V characterstcs of NMOS devces under operatng condton, the I-V characterstcs are measured and are gven n Fg.4, To examne the effects of substrate bas on I-V output characterstcs of NMOS under operatng condton, dran current I ds for dfferent V ds voltages varyng from 0 to 150mV and the output s shown n Fg 4.It may be seen that the varaton n I ds wth dran voltage,vds becomes less as V IN s made postve (deep sub- threshold regon).the nput characterstc s also shown n Fg.5. Here, the conductng channel acts as a resstance and because of that the dran current I D s proportonal to the dran-source voltage V DS.The characterstcs may be flat, to ndcate that the output resstance become very hgh. So, t gves the lnear regon or the Ohomc regon of the characterstc. Thus the dran current s less senstve to varatons n dran voltages, whch s a very useful feature for applcaton of electroncs devce n crcuts ndustry. In the case of PMOS for a gven negatve V GS, the dran voltage s made slghtly negatve wth respect to the source. A current flows from the source to the dran through the Fg.6. Output characterstc of VTPMOS III. CIRCUIT TECHNIQUES The transstors for logc are mplemented n 45 nm technology. The threshold voltage for these devces s 150mV for VTNMOS and-150mv for VTPMOS. The Wdth of VTNMOS (W N ) s chosen as 0.135µm and VT- PMOS (W P ) s chosen as 0.27µm. The supply voltage s taken as 0.1V whch s below the threshold of both the devces. For dfferent values the performance of the XOR gate s desgned usng technque and power dsspaton, propagaton delay have been obtaned through smulaton t n T-Spce. When the bas voltage s ncreased beyond supply voltage, the logc levels are affected. Hence there s a lmtaton for bas voltage and t should be always below supply. A. XOR Operaton The XOR gate s mplemented by 3 transstors where the transstors are connected as n the fg.7.when the nput B s at logc hgh, the nverter functons lke a normal CMOS nverter. When the nput B s at logc low, the CMOS nverter output s at hgh mpedance. However, the pass transstor M 3 s enabled and the output Y gets ISSN (Onlne): 2347-2820, Volume -1, Issue-2, 2013 35

Internatonal Journal of Electrcal, Electroncs and Computer Systems, (IJEECS) the same logc value as nput A. However, when A=1 and B=0, voltage degradaton due to threshold drop occurs across pass transstor and consequently the output Y s degraded wth respect to the nput. Here the crcut dagram of XOR s gven whch s constructed by and the output waveform s also gven n Fg. 7. Fg.8. Crcut dagram of Conventonal Full Adder usng Fg.7.Crcut dagram and Output of XOR (3T) B. Conventonal Full Adder The followng table shows the truth table of a bnary full adder: TABLE-1 TRUTH TABLE OF FULLADDER CIRCUIT A B C S C o 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Boolean expresson for S and C o s gven by the followng equatons: s A B C ABC ABC ABC ABC C 0 AB BC AC One way to mplement the full-adder crcut s to take the logc equatons above and to translate them drectly nto complementary CMOS crcutry. Some logc manpulatons can help to reduce the transstor count. For nstance, t s advantageous to share some logc between the sum- and carry-generaton sub crcuts. The followng s an example of such a reorganzed equaton set: C 0 AB ( B A) C S ABC C ( A B C ) 0 The equvalence wth the orgnal equatons s easly verfed. The correspondng statc CMOS s shown n the Fg 8 and requres 28 transstors. The output of Conventonal Full Adder s gven n Fg.9 Fg.9. Output of Conventonal Full Adder usng C. 8T Full Adder Structured approach for mplementaton of sngle bt full adder usng XOR/XNOR has been shown n Fgure 10. Wth decomposton of full adder cell nto smaller cells, the equaton becomes: Sum = H Cn = H. Cn+ H_bar. Cn Cout = A. H_bar+ Cn. H Where H s (A B) and H_bar s complement of H. Fg.10. Block Dagram of Full Adder n XOR Blocks The exclusve OR (XOR) and exclusve NOR (XNOR) gates are the basc buldng blocks of a full adder crcut. The XOR/XNOR gates can be mplemented usng AND, OR, and NOT gates wth hgh redundancy. Optmzed desgn of these gates enhances the performance of VLSI systems as these gates are utlzed as sub blocks n larger crcuts. Here the XOR gates are mplemented by prevous mentoned 3T XOR Gate. To generate the carry output one 2:1 MUX s necessary where H s taken as control.e. select lne and two nputs are A and Cn. A desgn of an eght transstor (8T) full adder s shown n Fgure. 11. ISSN (Onlne): 2347-2820, Volume -1, Issue-2, 2013 36

Internatonal Journal of Electrcal, Electroncs and Computer Systems, (IJEECS) Fg.11. Crcut dagram of 8T Full Adder usng D. Parallel Adder and Subtractor The 4bt parallel bnary adder crcut performs both addton of two nputs A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0. The augends (A 3 A 2 A 1 A 0 ) and addend (B 3 B 2 B 1 B 0 ) are added wth C IN =0.Hence the crcut works as a 4-bt adder resultng n sum P 3 P 2 P 1 P 0 and carry C OUT. The 4bt subtractor performs subtracton of two nputs A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0.Frst the nverter produces the 1s complement of the addend (B 3 B 2 B 1 B 0 ).Snce 1 s gven to Cn of the least sgnfcant bt of the adder, t s added to the complemented addend producng ts 2 s complement of before addton. Then A 3 A 2 A 1 A 0 wll be added to the 2 s complement of B 3 B 2 B 1 B 0 to produce the Dfference. The crcut dagram of Parallel Adder and Parallel Subtractor s gven n Fg.12 and Fg.13 respectvely. has been calculated wth the gven specfcaton and gven n Table II. From the table t s clear that 8T full adder wth consumes less power so, we have desgned further a parallel adder subtractor crcut wth the help of 8T full adder and compare ts nose power delay wth the parallel adder subtractor crcut made wth conventonal CMOS. The output waveform of 8T full adder wth s gven n Fg.14 and the output of parallel adder of bts(1111+1111) and (0001+0110) and the output of parallel subtractor(1111-0001) and (1010-0101) s also gven n Fg.15. and Fg.16. Fg.14. Output of Full Adder usng Fg.12. Crcut dagram of 4 Bt Parallel Adder usng Fg.15. Output of 4 Bt Parallel Adder usng Fg.13. Crcut dagram of 4 Bt Parallel Subtractor usng IV. RESULTS The conventonal full adder and the conventonal full adder wth s smulated n 45nm Technology moreover 8T Full Adder and 8T Full Adder wth s also smulated. The threshold voltage of NMOS n 45nm Technology 0.15V and for PMOS t s - 0.15V.The V dd s taken as 0.1V.The nput voltage s taken as below the threshold voltage so the MOS are operated n sub-threshold regon. The frequency of operaton s taken as 1000 MHz. The nose power delay Fg.16. Output of 4 Bt Parallel Subtractor usng Table-II NOISE POWER AND DELAY COMPARISION CONFIGERATION POWER (nw) NOISE (µv) DELAY (nsec) Conventonal Full 31 200 17 Adder Conventonal Full 17 50 50 Adder () 8T Full Adder 1.38 65 15 8T Full Adder() 0.765 60 47 ISSN (Onlne): 2347-2820, Volume -1, Issue-2, 2013 37

Internatonal Journal of Electrcal, Electroncs and Computer Systems, (IJEECS) CONFIGERATION POWER NOISE Parallel Adder wth Conventonal Full Adder 1.16µW 1.3MV Parallel Adder wth 8T Full Adder () 3.2nW 45µV Fg.17. Power Consumpton Comparson of Adders Fg.18. Delay Comparson of Adders Fg.19. Nose Comparson of Adders TABLE-III NOISE AND DELAY COMPARISION OF APRALLEL ADDERS V. CONCLUSION logc crcut technques compared to CMOS crcuts s extensvely appled due to the low power consumpton characterstc. From the result analyss we see, though t has lttle bt extra delay rather than normal CMOS or DTMOS, but t s ths dsadvantage overcome by ts extreme ultra low power regon operatng zone, whch leads to cost effectve crcut. If we buld any complex crcut usng ths approach, t wll be more effcent and low cost. ACKNOWLEDGMENT The authors would lke to thank Prof. (Dr.) M.R.Kanjlal and Faculty Members, Department of Electroncs and Communcaton Engneerng, Narula Insttute of Technology, WBUT, for many nsghtful dscussons. REFERENCES [1] K. Ragn, Dr. M. Satyam, And Dr. B.C. Jnaga Varable Threshold Mosfet Approach (Through Dynamc Threshold Mosfet)For Unversal Logc Gates, Internatonal Journal Of Vls Desgn & Communcato System (Vlscs),Vol.1,No.1, March 2010 [2] Farborz Assaderagh, Stephen Parke, Denns Smtsky, Jeffrey Bokor, Png K. Ko. Chenmng Hu (1994): A Dynamc Threshold Voltage Mosfet (Dtmos) For Very Low Voltage Opertaon,Ieee [3] Xangl L, Stephen A. Parke, And Bogdan M. Wlamowsk, Threshold Voltage Control For Deep Sub-Mcrometer Fully Depleted So Mosfet. [4] Farborz Assaderagh, Denns Sntsky, Stephen A. Parke,Jeffrey Bokor, Png K. Ko, And Chenmng Hu Dynamc Threshold-Voltage Mosfet (Dtmos) For Ultra-Low Voltage Vls, Ieee Transactons On Electron Devces, Vol. 44, No. 3, March 1997 ISSN (Onlne): 2347-2820, Volume -1, Issue-2, 2013 38