Low Current Switching Behavior of IGBT and Associated Spurious Tripping in Inverters Employing V CE De-saturation Protection

Low Current Switching Behavior of IGBT and Associated Spurious Tripping in Inverters Employing V CE De-saturation Protection Venkatramanan D, Anil Kumar Adapa, Kapil Upamanyu, Vinod John Department of Electrical Engineering Indian Institute of Science Bangalore, Karnataka, India Email: venkat86ram@ee.iisc.ernet.in, aniladapa@ee.iisc.ernet.in Abstract Insulated gate bipolar transistors (IGBT) have evolved significantly and become exceedingly fast. Today, their typical switching speeds are of the order of 100ns. The resulting dv dt is considerably large and when employed in a variable speed motor drive inverter, ringing over-voltages occur at the motor terminals even with cable as short as 1 meter in length. In any such power converter system, protection of IGBT in the event of a fault is an essential requirement. An effective way of protection is by detecting IGBT de-saturation, which occurs during device over-current or short-circuit, using sensed collectoremitter voltage (V CE). Several commercial isolated gate-driver ICs are available today in the market with integrated V CE desaturation protection feature. Such a protection scheme when employed in a modern IGBT based power converter and used for motor drive applications can lead to spurious trips. This paper investigates and reports the reasons for such spurious fault sensing by IGBT gate-drivers employed in two-level inverters. The circuit conditions are analyzed and it is shown that the IGBTs essentially act as capacitors while switching low currents. This behavior in combination with other factors such as fast device switching times, load power factor, and dead-time, is shown to cause spurious V CE fault trips. Two simple and costeffective circuit modifications are suggested which ensure that such spurious fault sensing is avoided in power converters. Keywords IGBT de-saturation protection, V CE sensing, gatedriver, motor cable, voltage doubling, low-current switching, spurious trips. I. INTRODUCTION IGBT based PWM power converters are widely employed today in a variety of medium and high power conversion applications, which typically include adjustable speed motor drives, off-grid or grid-tied renewable energy based DG systems, power quality conditioners, and static UPS systems [1], [2]. IGBTs have themselves evolved considerably over the past decade and have become exceedingly fast [3]. Protection of such an IGBT in case of a fault such as load short-circuit, is paramount. A variety of fault diagnostic and protection schemes for IGBT exist in literature [4]. Protection by detecting device de-saturation (DESAT) with the help of sensed V CE voltage is a popular scheme for identifying faults due to overcurrent, load short-circuit and dc-bus shoot-through [5], [6]. This work was supported by CPRI, Ministry of Power, Government of India, under the project Power conversion, control, and protection technologies for microgrid. 978-1-4673-8888-7/16/$31.00 c 2016 IEEE Fig. 1: Power circuit schematic of drive system showing threephase inverter, motor and interconnecting cable. TABLE I: Drive system ratings Item Power converter rating Motor rating Rated dc-bus voltage V DC Rated output voltage (l-l RMS) Output current (RMS) Value 15 kva 30 hp 680 V 415 V 23 A Nominal modulation index m a 1 Switching frequency f sw 10 khz Several commercial isolated gate-driver ICs as well as gatedrive boards are available today with integrated V CE DESAT protection feature [7] [9]. Spurious converter fault trips have been observed to occur consistently in three-level neutral point clamped (NPC) inverters that employ V CE DESAT protection, as reported in literature [5]. However, studies on spurious trip occurrences in two-level inverters are rather limited. In this work, it is shown that spurious V CE DESAT fault trips can occur consistently in two-level inverters as well, due to reasons distinct from that pointed out in [5], when a motor load is employed. Fig. 1 shows power circuit schematic of experimental setup, where a three-phase PWM inverter powers a 30 hp three-phase squirrelcage motor. Table. I lists the drive system ratings. Fig. 2 shows three-phase line currents of motor operating at no load, with 70% inverter dc-bus voltage and modulation index (m a ) of 1. It can be seen that DESAT-fault signal V CE F LT is asserted by the processor in the course of operation during R-phase current zero crossing, even before 100% system voltage is reached. It is pointed out that such

Fig. 3: DESAT protection circuit using HPCL-316J. Fig. 2: Motor line currents showing occurrence of spurious DESAT fault at R-phase current zero-crossing and Highfrequency ringing in line current and motor terminal voltage due to cable voltage-doubling effect. a fault is spurious in nature and occurs frequently at zerocrossings of the motor phase currents. The investigations carried out in this work show that diverse factors such as fast turn-off times of modern IGBTs, modulation index, load power factor, dc-bus voltage and lowcurrent IGBT switching characteristics play a key role in the spurious fault tripping. To begin with, effects of fast device transition times on motor and PWM inverter are explained. Then, the concept of V CE DESAT sensing based protection is introduced briefly, which is essential for understanding spurious fault sensing. Subsequently, low-current switching characteristics of IGBTs, which is distinct from that during nominal current switching due to influence of device collectoremitter capacitance, is explained. Experimental results are presented that illustrate the phenomena, which are used to explain the root-cause of spurious V CE DESAT fault. Two cost-effective circuit modifications are suggested that can be employed to avoid such spurious fault tripping. Experimental results validating the same are presented followed by conclusion. II. EFFECT OF IGBT TRANSITION TIME A state-of-the-art IGBT has a switching time that could be as low as 100ns [3]. Owing to fast transition time and resultant large dv dt, even a short cable of 1m length could cause voltage overshoot at the motor terminals due to wave reflection phenomena [10]. Fig. 2 illustrates the voltage excursions and oscillations occurring at 2.9 MHz on a 30 hp induction Fig. 4: Standard double-pulse test circuit and Turn-off transient of IGBT S B during double pulse test at 750V and 25A, without complementary pulse command to S T. motor terminals, for 3m cable length and 100 ns voltage rise time at the inverter end. It can be seen that the motor current also carries a high-frequency oscillatory component aside from switching ripple and fundamental components. This high-frequency current must be catered to by the power converter, and has a bearing on spurious V CE fault at current zero-crossing. III. V CE DESATURATION BASED PROTECTION The concept of V CE DESAT protection is discussed thoroughly in [6] [9] and is briefly explained in this section. Fig. 3 shows the DESAT fault detection circuit employed in commercial IC HPCL-316J [11]. DESAT-fault is detected by sensing the voltage across 100 pf blanking capacitor C blank, which is connected to DESAT pin of IC as well as the IGBT collector. A fault is declared by the IC when this voltage exceeds an internal reference of 7 V. An internal current source of 250 µa is present that continuously tends to charge C blank. However when IGBT turns on, this voltage is clamped to onstate voltage drop of device, which is 2 V typically. C blank s voltage is expected to exceed 7 V only in case of over-current or IGBT short-circuit condition. It is shown in this work that if certain extraneous circuit condition disturbs C blank s voltage beyond 7 V, a spurious fault declaration can occur. IV. LOW-CURRENT IGBT SWITCHING CHARACTERISTICS Switching characteristics of IGBT at nominal or rated operating conditions is well discussed in literature [12]. Whereas, reports are rather limited for low or near-zero-current switching characteristics of IGBT [13]. It is however important to understand the same in the present case, as spurious faults are observed to occur at current zero-crossings. Fig. 4

Fig. 6: Equivalent circuit model of an inverter leg during low current switching when both devices are turned off. (c) Fig. 5: Double-pulse test result at large DUT voltage and nearzero current showing transitions without complementary pulse to S T, transitions with complementary pulse applied to S T, and (c) transitions at large DUT voltage and zero current with complementary pulse applied to S T. shows standard double-pulse test circuit employed, where device under test (DUT) is bottom IGBT S B. In this work, tests are conducted with complementary gate-pulses applied to top device S T as well, in contrast to the conventional test procedure wherein the top device is kept turned off [14]. A 1200V, 40A, TO-247 package IGBT is used in this work [15] and Rogowski coil based current probe CWT ultra mini is employed for measuring device source current, as indicated by Fig. 4. The typical turn-off switching characteristics of DUT is shown in Fig. 4, indicating device voltage V DS,B and current I DS,B profiles at large voltage and current, during the second turn-off pulse of the double-pulse test without complementary pulse applied to S T. It can be seen that the voltage rise time of the device is about 100ns. Fig. 5 shows switching characteristics of DUT at large voltage but near-zero current, without complementary pulse to S T. It can be seen that the DUT voltage V DS,B during the first turn-off pulse, takes about 1.5µs to reach V DC. During the second turn-off pulse, when the switching current is relatively larger, the DUT takes lesser time of about 600ns to reach V DC, which suggests the actual value of (low) current has a bearing on voltage rise time. It may be noted that V DS,B continues rise slowly even after gate voltage V GS,B has fallen below 0V, when the electron channel below the gate in the device is completely cut-off. This is possible when the device drain-source capacitance dominates the switching operation and governs the voltage profile during turn-off. Fig. 5 shows switching characteristics of DUT at large voltage and near-zero current, but with complementary gatepulse given to top device S T. The dead-time provided in the present case is 750ns. It can be noted that after first turn-off pulse, V DS,B begins to rise slowly, but quickly charges to V DC as soon as S T is turned-on after the preset dead-time. Also, the corresponding charging surge current is seen in the measured I DS,B waveform. Fig. 5(c) shows switching characteristics of DUT at large voltage and at zero current, with complementary gate-pulse given to top device S T. It can be seen that V DS,B rises quickly to V DC from 0 V only after S T is turned on. The corresponding charging surge current is seen in the device current trace. S T acts as a capacitor and gets charged to V DC during first turnon command of S B. S T s capacitor discharges only when it receives a turn-on pulse, post to turn-off of S B. From these experimental observations, it can be surmised that the switching behavior of device at low currents is unlike that during nominal operating conditions. The manifested (slow) device voltage rise profile is not due to extension of inherent device transition time, but rather due to charging and discharging of device parasitic capacitances C DS,B and C DS,T respectively. The device would actually turns off soon after the gate-source voltage V GS,B falls below gate threshold value, as the conducting channel between drain and source due to the field effect, no longer exists. Fig. 6 shows a capacitive equivalent circuit model of the inverter leg that can be used to analyze spurious tripping issue at motor current zero-crossings, where essentially low-current switching of the devices occur. V. SPURIOUS V CE DESAT FAULT Few experimental observations are presented in this section that illustrate the behavior of various circuit quantities on motor and converter side, that lead to a spurious V CE fault declaration. It is remarked that fault repeatedly occurs at current zero-crossings, which is captured and presented. The capacitor model of the device described in Section IV is used to explain the observed behavior. Unless indicated otherwise, in all the observations made, dc-bus voltage is 500 V. Sinetriangle PWM technique is employed on the inverter with 750

ns dead-time, m a equals unity and a 15 m cable is employed to connect to the induction motor. A. Experimental Observations Fig. 7 provides a close-up view of the line-line voltages at motor and converter sides, at the instant of spurious fault declaration. It can be noticed that fault is detected near current zero-crossing of I R. Also, voltage V RG INV appears disturbed, which coincides with high-frequency oscillations that rides over I R due to reasons pointed out in Section II. Fig. 7 provides a zoomed view of R-phase device voltages V DS,S1 and V DS,S2 along with zero-crossing of motor line current I R, just prior to fault detection. It can be noticed that the turning-on of top device S 1 during R-phase current zero-crossing initiates high-frequency oscillation in the same. The oscillations in current continue to exist even after S 1 is turned off. During the dead-time period when both devices are off, the device voltages jitter at high frequency along with line current oscillation following which a fault is declared. Note that such a jitter can occur only during the dead-time period when both devices are turned-off, since at all other times, gatevoltage drive is present which essentially determine the device states and hence their V CE voltages. The observed jitter during current zero-crossing can be explained using the capacitor model of inverter leg described in Section IV and Fig. 8. When S 1 turns on during current zero-crossing, the capacitor C S1 is completely discharged and capacitor C S2 is charged to V DC, as indicated in Fig. 7. Alongside this, high-frequency oscillations are initiated as well, which during the dead-time period and before the subsequent turn-on of S 2, discharge C S2 and charges C S1 and viceversa alternatively as illustrated by Fig. 8, till the oscillations die-out. The charging and discharging of device capacitors by the high-frequency current oscillation is manifested as the jitter in the device collector-emitter voltages in Fig. 7. The device capacitances being very small in value, typically ranging in few hundred picofarads, are charged and discharged by the oscillatory current at a rather fast rate, thus causing fast changes in voltage V CE. The desat-diode D D recommended in the IC data-sheet is MURS120T3G, which is a ultrafast diode carrying a junction capacitance C D of about 45pF [16]. The recommended value of C blank is 100pF, for 3µs blanking time [11]. Fast V CE changes thus results in a capacitive current being injected into C blank through C D, thereby disturbing the voltage at DESAT pin as shown in Fig. 8. This disturbance could exceed 7 V, which is sensed by the gate-driver IC and a fault is subsequently declared that is spurious in nature. Fig 9 shows the gate-emitter voltages of the devices just prior to spurious DESAT-fault declaration during R-phase current zero-crossing. The corresponding disturbances occurring in C blank voltage during the dead-time period prior to turn-on of S 2, which is due to high-frequency resonant line current ringing, is illustrated in Fig 9. B. Inference In essence, when power factor is close to zero, current zerocrossing coincides with phase voltage peak, wherein PWM turn-off pulse width durations are rather small, and particularly so when modulation index is close to unity. When motor Fig. 7: Spurious V CE fault declaration in R-phase device showing line current zero-crossing and line-line PWM voltages on converter and motor side and line-current zerocrossing and collector-emitter device voltages of R-phase leg just prior to fault declaration. Fig. 8: Charging and discharging of device capacitances by high-frequency ringing in R-phase line current during zerocrossing and capacitive charging current disturbing C blank voltage in DESAT circuit.

Fig. 10: Experimental setup showing three-phase inverter, controller and 30 hp induction motor. Fig. 9: Spurious VCE fault declaration in R-phase device showing gate-emitter device voltages of R-phase leg and dead-time during current zero-crossing, just prior to spurious fault declaration and disturbance caused in Cblank voltage during the dead-time period leading to spurious fault detection. loads are employed, an additional high-frequency resonance current component flows in the line currents due to cable and motor parasitics. Since IGBTs behave like capacitors at the time of current zero-crossing, the high-frequency current component causes jitters in device collector-emitter voltages during the dead-time periods, as in Fig. 7. This jitter corrupts the sensed blanking capacitor Cblank voltage due to capacitive coupling through junction capacitance of desatdiode. During turn-on command post to dead-time, if Cblank s voltage happens to exceed 7V due to corruption by rising edge of VCE jitter, as in Fig 9, then a spurious DESAT fault is declared. VI. M ITIGATION T ECHNIQUES There are different ways in which the spurious trip issue can be dealt with. Increasing the device transition times by increasing gate-resistance or with additional gate-source capacitance would mitigate the high-frequency oscillations induced in line current, however this also would increase device switching losses and affect the converter efficiency. Use of output filters or dv dt filters also mitigates the problem of highfrequency ringing in line currents [17]. However, this method is not only expensive but also an over-design if employed just for mitigation of spurious trip problem. Experimental results show that increasing the dead-time to 2µs or more appears to eliminate spurious trip occurrence. The reason for Fig. 11: Ferrite bead arrangement at the inverter three-phase output lines. this behavior is that increased dead-time provides additional room for oscillations to die down, and hence by the time the next turn-on pulse arrives, the Cblank voltage is settled. However, increasing dead-time could introduce other issues in motor loads such as lower order harmonics and sub-harmonic oscillations [18]. In this section, two simple and inexpensive solutions are presented for addressing the issue of spurious trip, which are validated through experiments. Fig 10 shows the experimental setup consisting of three-phase inverter and 30hp induction motor. A. Output ferrite beads Addition of ferrite cores or beads in the output lines effectively dampens out high-frequency ringing in load current, and thus avoids spurious trips. Note that ferrite cores would saturate at higher values of load current and cease to provide damping, but this is inconsequential to the problem in question, which occurs only at zero-crossings, where the ferrites remain functional. Fig. 11 shows the physical arrangement of ferrite beads at the inverter AC output lines. With ferrite-beads in place, motor operation at 15 kva power level has been experimentally verified through an 8-hour burn-in test without spurious trips.

DESAT diode s junction capacitance, and thus result in a spurious DESAT-fault. Two simple and inexpensive mitigation techniques are suggested that address the problem of inauthentic fault detection, which are verified experimentally and are seen to be effective methods to prevent spurious tripping of the power converter. REFERENCES Fig. 12: Modification in de-saturation detection circuit of HPCL-316J. Fig. 13: Three-phase motor line currents and line-line voltage V RG at rated inverter operating conditions of 15 kva during burn-in test. B. Filter in DESAT protection circuit The disturbance in C blank voltage is caused primarily due to capacitive coupling between C blank and device collector, and the capacitive current injected during fast collector-emitter voltage changes. The magnitude of injected current can be decreased by increasing the resistance in the charging path. An additional resistor R F of 1kΩ and capacitor C F of 100pF in the DESAT-circuit can be used, as indicated in Fig.12. This circuit in effect acts as a low pass filter and prevents excessive voltage excursions in C blank. Although the addition of 1kΩ filter resistance in DESAT-circuit is at variance with the data-sheet recommendation [11], it does not hamper the short-circuit detection capability of the circuit, which has been verified experimentally. With filter in place, spurious trips are completely eliminated and the same has been experimentally verified through an 8-hour burn-in test where motor is operated by the inverter at 15kVA power level, as indicated by Fig.13. VII. CONCLUSION Spurious trips have been observed to occur in two-level power converters powering motor loads, that employ IGBT de-saturation based fault detection scheme. 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