Performance Analysis Of Low Power Using Hybrid And Subthreshold Adiabatic Logic For Digital Circuit

Transcription

1 Performance Analysis Of Low Power Using Hybrid And Subthreshold Adiabatic Logic For Digital Circuit S.Yamuna 1, Dr.Deepa Jose 2 ABSTRACT By using CMOS logic and transmission gate logic, a hybrid 1-bit full adder is designed, which is reported in this paper. The design is first implemented for 1-bit full adder and then extended for application of 4-bit Ripple Carry Adder(RCA).The Modification in the 4-bit Ripple Carry Adder is done by using Subthreshold adiabatic logic(sal) circuits.it is analyzed to make great improvement in ultra low power circuit design. When comparing with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power.after the implementation, the comparison of power is made between Hybrid logic and the Subthreshold adiabatic logic for 4-bit Ripple Carry Adder.Hence, 18% of power is reduced using SAL logic. The circuit is simulated using Cadence Virtuoso tool in 180nm technology. Keywords: Hybrid Logic, Low Power, Subthreshold Adiabatic Logic. 1. INTRODUCTION Full adders, is one of the most important block of all the VLSI circuitapplications, it is the main domain for the researchers. For implementing1-bit full adder, different logic styles are used each having itsown merits and demerits.all these designs are classified into two categories: 1. static design and 2. dynamic design. Static full adders are generally simple with less power consumption but the requirement of chip area is larger compared with its dynamicdesign.by using more than one logic style for the implementation is known as hybrid-logic design style[1-5]. The features of different logic styles of these designs is used to improve the performance of the full adder.the merits of standard complementary CMOS style-based adders with 28 transistors are its robustness against transistor sizing and voltage scaling; the requirement of buffers and high input capacitance are the demerits of this design.the other logic style is CPL, it shows good voltage swing restoration employing32 transistors. The disadvantages of the CPL are its highswitching activity and high transistor count [5-11]. So, it is not an appropriate choice for low-power applications. The main disadvantage of CPL is voltage degradation. It uses only20 transistors for full adder implementation. Later, the hybrid logicstyle is used to improve the performance of power. The knowledge about power dissipation, leakage current, and noise immunity is required to analyze and design of SAL. The behaviors of adiabatic logic in subthreshold region is discussed in this paper. To analyze the workability of adiabatic logic circuits in subthreshold region, here 4-bit Ripple Carry Adder is used as a reference circuit. 2. METHODOLOGY 2.1 HYBRID FULL ADDER 1 PG student,centre for Excellence in VLSI Design, Department of Electronics and Communication engineering, KCG College of Technology, Chennai Associate Professor, Centre for Excellence in VLSI Design, Department of Electronics and Communication engineering, KCG College of Technology, Chennai-97. The full adder circuit is designed by three Modules as shown in Fig. 1(a). Module 1 and module 2 represents the XNOR modules to generate the sum signal (SUM) andmodule 3 to generate the output carry signal (C out ). Here, each Volume 5, Issue 12, December 2016 Page 24

2 module is designed individually. So that the entire adder circuit is optimized in terms of power. These modules are explained below in detail. In the proposed full adder circuit, the power consumption of the entire adder circuit depends on XNOR module. The modified XNOR circuit is shown in Fig. 1(b) where the power consumption is reduced mainly by the use of weak inverter. It is formed by transistors Mp1 and Mn1 [Fig. 1(b)]. Output signals is generated by level restoring transistors Mp3 andmn3 [Fig. 1(b)]. The modified XNOR presented in this paper gives low-power and high-speed compared with conventional full adder. Fig.1 (a) Schematic structure of full adder. (b) XNOR module. (c) Carry generation module. In the proposed circuit, the output carry signal is generated by the transistors Mp7, Mp8, Mn7, and Mn8 as shownin Fig. 1(c). Mn7 and Mp7 represents singletransmission gate, theinput carry signal (Cin) propagates only through it. Which reduce the overall carry propagation path significantly. In strong transmission gates,channel width of transistorsis made large.the main use of strong transmission gates is to furtherreduction in propagation delay of the carry signal Fig. 2. Detail circuit diagram of proposed full adder. The detail circuit diagram of the proposed full adder is shown in Fig.2.The output of sum in the full adder is implemented by XNOR modules. The transistors Mp1 and Mn1 shows an inverter which generate B, it is effectively used to design the controlled inverter using the transistors Mp2 and Mn2. Controlled inverter has some voltage degradation problem, to overcome that two pass transistors Mp3 and Mn3 is used. The second stage of XNOR module to implement the complete SUM function is realized by pmos transistors and nmos transistors. If, A = B, thenc out = B; else,c out = C in. If the inputs are same, then C out = B, it is implemented by the transmission gate transistors of Mp8 and Mn8. Else, the input carry signal(c in ) is C out then it is implemented by another transmission gate transistors of Mp7 and Mn7. Volume 5, Issue 12, December 2016 Page 25

3 Fig. 3 4-bit Ripple Carry Adder The implementation of hybrid logic style in 1-bit full adder consumes less power when compared with the conventional full adder. So, it is applied to the application of 4-bit Ripple Carry Adder. Fig.3 shows the 4-bit Ripple Carry Adder 2.2 SUBTHRESHOLD ADIABATIC LOGIC Basic Model of MOSFET in Subthreshold Region Using EKV model, the I V characteristics of the subthresholdpmos device can be expressed by I Sub = I 0 e (VSG VTH )/n pvt (1 e VSD/VT ) wherei 0 = 2ηpμpCox(W/L)V 2 T VSG, VSD, and VTH aresource to gate, source to drain, and threshold voltage ofpmos, respectively. V T = (k T /q) is thermal voltage, ηpissubthreshold slope factor, and μpis the mobility of pmosdevice. In subthreshold regime, the threshold voltage (VTH) depends on source-to-drain voltage (VSD) through body effectand drain-induced barrier lowering. Considering these effects,threshold voltage can be expressed as follows: V TH = V TO γv SB ηv SD. Here, V TO is the threshold voltage at zero bias and γ and η are the body effect and drain-induced barrier lowering coefficient, respectively. The Drain Induced Barrier Lowering coefficient (η) which is a unitless quantity, can be expressed as η = 1/2 cosh(l eff /2lt ) wherelt= (ε Si ToxX Dep /βεox) 1/2 and γ = I SUB = K P exp(v SG /npvt)(1 exp( VSD/VT)) wherek P = I0 exp( V TO ηv SD /npvt ). For the sake of simplicity, let us further simplify the magnitude of Kpby assuming, ηv SD /n pv T -1 Fig. 4.Logical structure of basic SAL logic gates. 2.3 SUBTHRESHOLD ADIABATIC LOGIC-BASED 4-BIT RCA To analyse the workability of proposed logic, here SAL-based 4-bit RCA is designed. By using the SAL based standard library gates like buffer/inverter, AND, OR, NAND, NOR, which are necessary to implement the 4- bit RCA. Fig 4 shows the structure of SAL based logic gates. This logic structure requires either the pull-up or pull-down network of static conventional logic. For example, implement a NAND or a NOR gate, the pull-up network is placed between the supply clock and the output load capacitors. Volume 5, Issue 12, December 2016 Page 26

4 Fig. 5.Logic structure of 4-bit CLA. In NAND structure, the output node voltage will follow the supply clock closely, and we get a triangular output waveform, for every input combination except A = B = 1. When A = B = 1 leakage currents will flow through parallel pmos transistor. In the load capacitor, a very small amount of charge will be stored. The structure of 4-bit RCA is shown in Fig.5 3. RESULT AND OUTPUT 1-bit Full adder is implemented by using Hybrid logic and the Subthreshold Adiabatic Logic(SAL). In this the power consumption is reduced in SAL logic and it is extended to the application of 4-bit Ripple Carry Adder(RCA). The power consumption of Hybrid and SAL logic are shown in tabular format. The simulation and the Output Waveform is shown below. Fig. Schematic of 1-bit Hybrid Full adder Fig. Schematic of 1-bit SAL Full adder Fig. Schematic of 4-bit RCA of Hybrid logic Volume 5, Issue 12, December 2016 Page 27

5 Fig. Schematic of 4-bit RCA of SAL logic Fig. Output Waveform of 4-bit RCA of Hybrid logic Fig. Output Waveform of 4-bit RCA of SAL logic Table 1: Power consumption of full adder using Hybrid and SAL logic Table 2: power consumption of 4-bit RCA using Hybrid and SAL logic 5. CONCLUSION In this paper, a low-power hybrid 1-bit full adder has been designed and it is extended for 4-bit RCA. The simulation was carried out using standard Cadence Virtuoso tools with 180-nm technology and compared with 4 bit RCA of subthreshold adiabatic logic design. SAL has been presented in this paper to advance the ultralow power research. The simulation results established that the proposed adder offered improved Power compared with the earlier reports. Volume 5, Issue 12, December 2016 Page 28

6 This proposed logic scheme can be used in future power-saving embedded circuits and mainly for power efficient devices where ultralow power and longevity are thepivotal issues. REFERENCES [1]. P. Bhattacharyya; B. Kundu; S. Ghosh; V. Kumar; A. Dandapat, Performance Analysis of a Low-Power High- Speed Hybrid 1-bit Full Adder Circuit in Proc. IEEE VLSI system, October.2015, pp [2]. M. Chanda; S. Jain; S. De; C. K. Sarkar, Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application in Proc. VLSI system, December 2015,pp [3]. P. Prashanth and P. Swamy, Architecture of adders based on speed, area and power dissipation, in Proc. World Congr. Inf. Commun.Technol. (WICT), Dec. 2011, pp [4]. S. Wairya, G. Singh, R. K. Nagaria, and S. Tiwari, Design analysis of XOR (4T) based low voltage CMOS full adder circuit, in Proc. IEEENirma Univ. Int. Conf. Eng. (NUiCONE), Dec. 2011, pp [5]. C.-K. Tung, Y.-C.Hung, S.-H.Shieh, and G.-S.Huang, A low-powerhigh-speed hybrid CMOS full adder for embedded system, in Proc.IEEE Conf. Design Diagnostics Electron.Circuits Syst., vol. 13.Apr. 2007, pp [6]. M. L. Aranda, R. Báez, and O. G. Diaz, Hybrid adders for high-speedarithmetic circuits: A comparison, in Proc. 7th IEEE Int. Conf. Elect.Eng. Comput. Sci. Autom. Control (CCE), Tuxtla Gutierrez, NM, USA,Sep. 2010, pp [7]. M. Aguirre-Hernandez and M. Linares-Aranda, CMOS full-adders forenergy-efficient arithmetic applications, IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 19, no. 4, pp , Apr [8]. T.-T. Liu and J. M. Rabaey, A 0.25 V 460 nw asynchronous neural signal processor with inherent leakage suppression, IEEE J. Solid-StateCircuits, vol. 48, no. 4, pp , Apr [9]. A. Calimera, A. Macii, E. Macii, and M. Poncino, Design techniques and architectures for low-leakage SRAMs, IEEE Trans. Circuits Syst.I,Reg. Papers, vol. 59, no. 9, pp , Sep [10]. Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design. New York, NY, USA: Springer-Verlag, [11]. T. Pranisha, Deepa Jose, "Area Efficient Cordic FFT Using Error Correction Codes And Parseval Checks For OFDM Systems" ARPN Journal of Engineering and Applied Sciences,Vol. 11, Issue.5, pp Volume 5, Issue 12, December 2016 Page 29