RT- HIL Implementation of Hybrid Synchrophasor and GOOSE- based Passive Islanding Schemes

Transcription

1 RT- HIL Implementation of Hybrid Synchrophasor and - based Passive Islanding Schemes M. Shoaib Almas E- mail: msalmas@kth.se PhD Candidate Electric Power Systems Department KTH Royal Institute of Technology Stockholm, Sweden Dr. Luigi Vanfretti E- mail: luigiv@kth.se Luigi.vanfretti@statnett.no Associate Professor, Docent Special Advisor in Electric Power Systems Strategy and Public Department Affairs KTH Royal Institute of R&D Department (FoU) Technology Statnett SF Stockholm, Sweden Oslo, Norway Working Group: Power System Dynamics Measurements July 28, 215

2 2 The work presented here is a result of the collaboration between KTH SmarTS Lab (Sweden), Statnett SF (Norway) This work has been financed by: Statnett SF, the Norwegian transmission system operator, through its Smart Operation R&D program. The Nordic Energy Research through the STRONgrid project. The following people have contributed to this work: KTH SmarTS Lab: Dr. Luigi Vanfretti, M. Shoaib Almas, Maxime Baudette, Viktor K. Appelgren, Eldrich Rebello Statnett SF: Stig Løvlund, Jan O. Gjerde, Dr. Luigi Vanfretti.

3 3 Outline view of SmarTS Lab Synchrophasors for time- critical protection applications? Why a hybrid synchrophasor and IEC based scheme? Passive islanding detection schemes using local synchrophasors /under /under ROCOF Passive islanding detection schemes using wide- area synchrophasors Conclusions

4 4 Our Architecture ECS

5 5 Synchrophasors for Protection Applications System Integrity Protection Schemes (SIPS), Remedial Action Schemes (RASs), Intelligent Load- Shedding schemes utilizing synchrophasor measurementsare beingresearched. Back- up protection relays have an operating time between 1-5 msec, which can easily be taken care by synchrophasor- basedschemes. Local synchrophasor- based islanding detection schemes are the first logical step towards the implementation of more complex and wide- area synchrophasor- based islanding schemes.

6 6 Hybrid Synchrophasor and IEC based Passive Islanding Detection Methods The proposed hybrid schemes ensure minimum communication delays. (Synchrophasors utilized internally + Latency related to I/O status change of PMU) Deployment ofprotection actions usinglogic equations avoids the delays incurred due to intermediate PDC or IEEE C protocolparser. Latencies such as PMU filtering delay, PMU synchrophasor computation delay, latencies associated with remote measurements time- alignment, PMU algorithm execution delay, synchrophasor frame formation delay and message delays cannot be evaluated by simulation- alone. (RT- HIL is necessary).

7 7 Hybrid Synchrophasorand IEC based Passive Islanding Detection Methods (Local Synchrophasors) IEEE 3- machine, 9- bus power system modelled in MATLAB/Simulink. The islanded region is outlined G2 Bus 2 Bus 7 T2 Bus 4 G1 T1 Load C 1 MW 35 Mvar Bus 9 T3 Bus 3 CB- 1a Bus 8 3 MW 18/23 kv 23/18 kv 27 MW CB- 1b Bus 6 Bus 5 Load B CB- 2a 9 MW CB- 2b 3 Mvar Legend Load A 125 MW 5 Mvar Islanded System Hardwire interface Synchrophasors over TCP/IP IEC /23 kv Bus 1 CB- 3 3 MW G3 and current phasors computed at 5 msgs/sec SEL- 421 PMU Trip Signal () To Monitoring Application

8 Hybrid Synchrophasorand IEC based Passive Islanding Detection Methods (Local Synchrophasors) Local Synchrophasors The synchrophasors are internally utilized by the PMU to execute the islanding detection algorithms deployed using logic equations. Once the islanding condition is detected, a trip command is generated by the PMU and a message with changed status is sent to the RTS Real- Time Simulator IEEE 3- machine, 9- bus system being executed in real- time using Opal- RT Real- Time Simulator GPS Antenna Substation Clock Arbiter Model 194 B Amplified three phase voltage and current of Bus 2 and Current Amplifiers Trip Signal () Once islanding condition is detected, PMU sends a trip signal using message to RTS. This message is subscribed inside RTS to open circuit breaker CB- 3 upon status change. Legend GPS Signal Hardwired SEL- 421 PMU S3DK S3DK unwraps the PMU stream and provide raw phasors, analog and digital wrapped in IEEE C format in Labview enviroment. PMU stream Trip Signal () Phasors for Va, Vb, Vc, V+, Ia, Ib, Ic, I+ computed at 5 msgs /sec Synchrophasor based Passive Islanding Detection Algorithm based on local synchrophasors is executed inside the PMU Islanding Detection Monitoring Application S 3 DK Raw measurements in LabVIEW Islanding Detected Developed Monitoring Application Measured Synchrophasor Time Breaker Trip Trip Time 19:57:8.2

9 9 Hybrid Synchrophasorand IEC based Passive Islanding Detection Methods (Local Synchrophasors) V+ mag local (PMU) a.9 cyc cyc TRIP b PMV53 := V1YPMM % Storing positive sequence voltage phasor magnitude in user defined analog PMV54 := 1.1 % Storing upper threshold value of 1.1 in user defined analog PMV55 :=.9 % Storing lower threshold value of.9 in user defined analog PSV1 := PMV53 > PMV54 % SET if positive sequence voltage phasor magnitude is greater than upper threshold PSV2 := PMV53 < PMV55 % SET if positive sequence voltage phasor magnitude is lesser than lower threshold PSV3 := PSV1 OR PSV2 % Logical OR operation. SET if either upper or lower threshold is exceeded. PSV49 := PSV1 % Store the status of upper threshold surpass as Digital 1 in C frame. PSV5 := PSV2 % Store the status of lower threshold surpass as Digital 2 in C frame. PSV51 := PSV3 % Store the status of PSV3 as Digital 3 in C frame. PCT1IN := PSV3 % Input for conditioning timer. Timer tracks PSV3 PCT1PU := 1. % Pickup is set to 1 cycles i.e. When PSV3 changes state from to 1, the timer will pick it up only if the state of PSV1 stays at 1 for 1 cycles PCT1Q : Timer output goes to 1 when the total time exceeds 1 cycles after the PSV1 is set PSV52 := PCT1Q % Store the status of conditional timer output as Digital 4 in C frame. c PMU Name PMU ID Input Connection PMU State PMU Status Unlock Time Distance M 2 Distance M Found OK Locked Timestamp 6/27/215 2:46:23.74 Hz. df/dt. Hz./s Phasors Analogs Digitals = Nominal Name Magnitude Value V1YPM VAYPM VBYPM VCYPM I1WPM Name Value PMV64. PMV63. PMV62. PMV61. PSV49 Configured Phasors, Analogs and Digitals for the PMU. These values are packgaed in C frame and are streamed out as synchrophasors PSV53 PSV57 PSV61 PSV5 1 PSV54 PSV58 PSV62 PSV51 1 PSV55 PSV59 PSV63 PSV52 1 PSV56 PSV6 PSV64 (a) Logic diagram (b) Protection logic equations used to deploy the algorithm within the PMU. (c) Synchrophasor frame showing the configured phasors, analogs and digitals. PSV 49- PSV 52 stores the digital status as configured by the protection logic equations (b).

10 Hybrid Synchrophasorand IEC based Passive Islanding Detection Methods (Wide- Area Synchrophasors) PMU- B is configured as a client for PMU- A and direct relay- to- relay communication technique is used between them. This allows the two PMUs to exchange synchrophasors directly, without the requirement of an intermediate PDC 1 Real- Time Simulator IEEE 3- machine, 9- bus test system being executed in real- time using Opal- RT Real- Time Simulator GPS Antenna Substation Clock Arbiter Model 194 B Amplified three phase voltage and current of Bus 7 (Remote Bus) and Current Amplifiers Amplified three phase voltage and current of Bus 4 (Local Bus) and Current Amplifiers Trip Signal () PMU- A (Server) PMU- B (Client) Once islanding condition is detected, PMU sends a trip signal using message to RTS. This message is subscribed inside RTS to open circuit breaker CB- 3 upon status change. Legend Phasor Measurement Units (PMUs) Va, Vb, Vc, V+, Ia, Ib, Ic, I+ computed at 5 frames / sec are sent to PMU- B Direct relay- to- relay communication Synchrophasor based Passive Islanding Detection Algorithm based on wide- area synchrophasors is executed inside PMU- B GPS Signal Hardwired a PMU stream Trip Signal Va- mag local (PMU- B) Va- mag remote (PMU- A) abs b.1 1 cyc cyc TRIP PMV53 := V1VPMM % Storing positive sequence voltage phasor in user defined analog value PMV54 := RTCAP1 % Storing positive sequence remote phasor in user defined analog value) PMV55 :=.1 % Storing threshold value of.1 in user defined analog value PSV1 := Abs(PMV53- PMV54) > PMV55 % SET if Absolute value of difference in positive sequence synchrophasor magnitude is greater than.1. Logic equations for PCT1 (Timer) and Synchrophasors digitals are the same as in Fig. 3(b) Algorithms for wide- area synchrophasor- based islanding detection using synchrophaosr frequency and ROCOF thresholds were implemented in the same way

11 ROCOF >.2 ROCOF >.2 11 Reactive Power Mismatch (ΔQ) 3% 2% 1% - 35% - 25% - 15% - 1% NDZ Comparison Reactive Power Mismatch (ΔQ) NDZ Non- Detection Zone for Passive Islanding Detection Schemes using Local Synchrophasor Measurements 1% 2% 3% 1% 2% 3% - 2% - 2% a - 3% b - 3% c 3% 2% 1% - 35% - 25% - 15% - 1% NDZ 1% 2% 3% 3% 2% 1% 5% - 35% - 25% - 15% - 1% NDZ Active Power Mismatch (ΔP) 1% 2% 3% - 25% - 15% ROCOF >.2 Non- Detection Zone for Passive Islanding Detection Schemes using Wide- Area Synchrophasor Measurements - 2% - 2% a - 3% b - 3% c 3% 2% 1% 5% - 35% - 25% - 15% - 1% NDZ - 25% - 15% ROCOF >.2 3% 2% 1% 5% - 5% - 1% - 2% - 3% 3% 2% 1% 5% - 5% - 1% - 2% - 3% ROCOF >.2 NDZ 1% 2% 3% ROCOF >.2 ROCOF >.2 NDZ 1% 2% 3% ROCOF >.2 Active Power Mismatch (ΔP)

12 12 Trip Time for DG Disconnection (s) Wide- Area Synchrophasors Trip Time for DG Disconnection (s) Local Synchrophasors Trip Time (s) Trip Time (sec) Active Power Mismatch (%) / / ROCOF Based Islanding o/u o/u ROCOF Threshold N D Z N D Z INF INF INF - 1% 1-9% 2-8% 3-7% 4-6% 5-5% 6-4% 7-3% 8-2% 9-1% 11 % 1% 12 2% 13 3% 14 4% 15 5% 16 6% 17 7% 18 8% 19 9% 2 1% o/u Volt o/u Freq ROCOF Threshold Active Power Mismatch (%) N D Z N D Z Active Power Mismatch (ΔP) / / ROCOF Based Islanding N D Z INF - 1% - 9% - 8% - 7% - 6% - 5% - 4% - 3% - 2% - 1% % 1% 2% 3% 4% 5% 6% 7% 8% 9% 1% N D Z Active Power Mismatch (ΔP) Operating Time Comparison

13 13 Communication Latencies Analysis VRAW Communication Latency between PMU and a real- time synchronized RTS VRAW (Volts) a VRAW : input to the VT Module of PMU Delay (millisecond) b VAZM : Filtered Instantaneous Magnitude of Phase A Time stamp of Synchrophasor Measurements Transducer Delay + Filter Delay 3 ms 3 ms Total PMU Processing Delay (6 ms) PMV61 : Synchrophasor computed for Phase A by the PMU Phasor Computation Delay () () () () () () () () () () () () () () () () () c () () () () () () () () () () () () () () () () () message being published by SEL PMU at a heartbeat of 1 msec. This monitors the communication path between the PMU and controller Once the status changes, bursts of repeated messages within 4-8 msec are sent by PMU and it gradually slows back down to the heartbeat rate of 1 msec Calculation of different latencies PMU processing delay (6 msec) [Filtering + Synchrophasor computaion] Delay associated in assembling synchrophasors in IEEE C format (45 msec) Communication latency of messages (4 msec)

14 14 Conclusions ROCOF-based schemes are effective for both active and reactive power mismatch, and result in faster operation. Wide-area schemes not only perform faster, but also have smaller NDZs If latencies are kept to a minimum, wide-area passive islanding detection schemes reduce the NDZ to half or two-third of the one using local synchrophasors. Fraction of Second (s) Extra Delay Incurred Within PMU-B for Synchrophasor Acquisition from PMU A and Time-Allignment X: 1.4 Y:.98 Fraction of Second (FOS) of PMU A Delayed Fraction of Second of PMU B for Time- Allignment X: 1.4 Y: Time (s) X: 1.4 Y:.98 Total Delay for Time Allignemnt = = 4 ms X: 1.4 Y: Time (s) Additional delay of 4 ms incurred inside PMU- B for synchrophasor acquisition from PMU- A and its time alignment while executing wide- area synchropahsors- based passive islanding detection schemes.

15 15 Thank you! Questions? an/organisation/avdelningar/eps/r esearch/smarttslab