PRELIMINARY PIN ASSIGNMENT VDD. nq0. CLK nclk. nq1 CLK_SEL. PCLK npclk. nq2 GND. Q3 nq3 CLK_EN. Q4 nq4. Q5 nq5. nq6. nq7. nq8

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1 DIFFERENTIAL-TO-HSTL FANOUT BUFFER DATA SHEET GENERAL DESCRIPTION The is a low skew, 1-to-9 Differentialto-HSTL Fanout Buffer and a member of the ICS family of High Performance Clock Solutions from ICS. The has two selectable clock inputs. The, pair can accept most standard differential input levels. The P, np pair can accept LPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ideal for today s most advanced applications, such as IA64 and static RAMs. FEATURES Nine HSTL outputs Selectable differential, or LPECL clock inputs, pair can accept the following differential input levels: LPECL, LDS, HSTL, SSTL, HCSL P, np supports the following input types: LPECL, CML, SSTL Maximum output frequency: 0MHz Output skew: 25ps (typical) Part-to-part skew: 200ps (typical) Propagation delay: 1.3ns (typical) OH = 1.4 (maximum) core, 1.8 output operating supply voltages -40 C to 85 C ambient operating temperature Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT _EN P np _SEL 0 1 D LE Q Q0 nq0 Q1 nq1 Q2 nq2 Q3 nq3 Q4 nq4 Q5 nq5 _SEL P np GND _EN O O Q0 nq8 nq0 Q8 Q1 nq7 nq1 Q7 Q2 nq6 nq2 Q6 O O O Q3 nq3 Q4 nq4 Q5 nq5 O Q6 nq6 Q7 nq7 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top iew Q8 nq8 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. IDT / ICS 1 1

2 TABLE 1. PIN DESCRIPTIONS Number Name _SEL 5 P 6 np 7 GND 8 _EN 9, 16, 17, 24, 25, 32 O 10, 11 nq8, Q8 12, 13 nq7, Q7 14, 15 nq6, Q6 18, 19 nq5, Q5 20, 21 nq4, Q4 22, 23 nq3 Q3 26, 27 nq2, Q2 28, 29 nq1, Q1 30, 31 nq0, Q0 NOTE: P ullup and Pulldown Type Description P ower Power supply pin. P ulldown Non-inverting differential clock input. P ullup Inverting differential clock input. Pulldown Clock select input. When HIGH, selects P, np inputs. W hen LOW, selects C LK,. LTTL / LCMOS interface levels. P ulldown Non-inverting differential LPECL clock input. P ullup Inverting differential LPECL clock input. P ower Power supply ground. Pullup P ower Output supply pins. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nq outputs are forced high. LCMOS / L TTL interface levels. refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol C IN R R PULLUP PULLDOWN Parameter Test Conditions Minimum Typical Maximum Capacitance 4 pf Pullup Resistor 51 kω Pulldown Resistor 51 kω Units IDT / ICS 2 2

3 TABLE 3A. CONTROL INPUT FUNCTION TABLE _EN s _SEL 0 0, 0 1 P, np 1 0, Outputs Selected Sourced Q0:Q8 nq0:nq8 Disabled; LOW Disabled; LOW Enabled Disabled; HIGH Disabled; HIGH Enabled 1 1 P, np Enabled Enabled After _EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in F igure 1. In the active mode, the state of the outputs are a function of the, and P, np inputs as described in Table 3B., np, P Disabled Enabled _EN nq0:nq8 Q0:Q8 FIGURE 1. _EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE or P s Outputs or np Q0:Q8 nq0:nq8 0 1 LOW 1 0 HIGH 0 Biased; NOTE 1 1 Biased; NOTE 1 LOW HIGH Biased; NOTE 1 0 HIGH Biased; NOTE 1 1 LOW NOTE 1: Please HIGH LOW HIGH LOW LOW HIGH to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential refer to the Application Information "Wiring the Differential to Accept Single Ended Levels". Polarity Non Inverting Non Inverting Non Inverting Non Inverting Inverting Inverting IDT / ICS 3 3

4 ABSOLUTE MAXIMUM RATINGS Supply oltage, 4.6 s, I -0.5 to Outputs, O -0.5 to O Package Thermal Impedance, θ JA 47.9 C/W (0 lfpm) Storage Temperature, T STG -65 C to 1 C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = -40 C TO 85 C Symbol O I Parameter ower Supply oltage utput Supply oltage ower Supply Current Test Conditions Minimum.13. Typical.. Maximum.46. P O P 60 ma Units TABLE 4B. LCMOS/LTTL DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = -40 C TO 85 C Symbol IH IL I IH I IL Parameter High oltage Low oltage High Current Low Current Test Conditions Minimum Typical Maximum _EN, _SEL _EN, _SEL _EN _SEL _EN _SEL IN IN IN IN = = Units = µ A = µ A = 0, = µ A 0, = µ A = TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = -40 C TO 85 C Symbol I IH I IL Parameter High Current Low Current Test Conditions IN IN IN IN = = Minimum Typical Maximum = Units 1 µ A = µ A = 0, = µ A 0, = µ A = PP Peak-to-Peak oltage Common Mode oltage; C MR 0.5 NOTE 1, NOTE 1: For single ended applications, the maximum input voltage for and is D D NOTE 2: Common mode voltage is defined as. I H IDT / ICS 4 4

5 TABLE 4D. LPECL DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = -40 C TO 85 C Symbol I IH I IL PP Parameter High Current Low Current P np P np Test Conditions = IN = IN Minimum Typical Maximum = Units 1 µ A = µ A = 3.465, = 0-5 µ A IN 3.465, = 0-1 µ A = IN Peak-to-Peak oltage Common Mode oltage; C MR 1.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as. I H NOTE 2: For single ended applications, the maximum input voltage for P and np is D D TABLE 4E. HSTL DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = -40 C TO 85 C Symbol Parameter Output High oltage NOTE 1 Output Low oltage NOTE 1 ; O H ; O L OX Test Conditions Minimum Typical Maximum Units Crossover oltage 40% x ( OH - O L ) + OL 60% x ( - ) + OH OL OL Peak-to-Peak SWING Output oltage Swing NOTE 1: Outputs terminated with Ω to ground. TABLE 5. AC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = -40 C TO 85 C Symbol f Parameter Test Conditions Minimum Typical Maximum Units Output Frequency 0 MHz MAX t PD ropagation Delay; NOTE 1 P ƒ 2MHz 1. 3 ns t sk(o) Output Skew; NOTE 2, 4 25 ps t sk(pp) Part-to-Part Skew; NOTE 3, ps t R / t Output Rise/Fall Time F 20% to MHz ps odc Output Duty Cycle % All parameters measured at 2MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. Measured from /2 to the output differential crossing point for single ended input levels. D D NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT / ICS 5 5

6 PARAMETER MEASUREMENT INFORMATION ± 5% 1.8 ± 0.2 O HSTL Qx nqx SCOPE, np, P PP Cross Points CMR GND = 0 CORE/1.8 OUTPUT LOAD AC TEST CIRCUIT GND DIFFERENTIAL INPUT LEEL nqx Qx nqy PART 1 nqx Qx PART 2 nqy Qy tsk(o) Qy tsk(pp) OUTPUT SKEW PART-TO-PART SKEW, np, P nq0:nq8 Q0:Q8 Clock Outputs 20% 80% 80% t R t F 20% OD t PD PROPAGATION DELAY OUTPUT RISE/FALL TIME nq0:nq8 Q0:Q8 t PW t PERIOD odc = t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT / ICS 6 6

7 APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage _REF = /2 is generated by the bias resistors, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of and might need to be adjusted to position the _REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5 and =, _REF should be 1.25 and / = _IN 1K _REF + - C1 0.1uF 1K FIGURE 2. SINGLE ENDED SIGNAL DRIING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: / INPUT: For applications not requiring the use of the differential input, both and can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from to ground. HSTL OUTPUT All unused LHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. P/nP INPUT: For applications not requiring the use of a differential input, both the P and np pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from P to ground. LCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT / ICS 7 7

8 DIFFERENTIAL CLOCK INPUT INTERFACE The / accepts LDS, LPECL, HSTL, SSTL, HCSL and other differential signals. Both SWING and OH must meet the PP and CMR input requirements. Figures 3A to 3E show interface examples for the / input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 1.8 LHSTL ICS LHSTL Driver LPECL R3 FIGURE 3A. HIPERCLOCKS /N INPUT DRIEN BY ICS HIPERCLOCKS HSTL DRIER FIGURE 3B. HIPERCLOCKS /N INPUT DRIEN BY LPECL DRIER LPECL R3 R4 LDS_Driv er 100 Receiver FIGURE 3C. HIPERCLOCKS /N INPUT DRIEN BY LPECL DRIER FIGURE 3D. HIPERCLOCKS /N INPUT DRIEN BY LDS DRIER LPECL C1 R3 R4 C2 R R R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS /N INPUT DRIEN BY LPECL DRIER WITH AC COUPLE IDT / ICS 8 8

9 LPECL CLOCK INPUT INTERFACE The P /np accepts LPECL, CML, SSTL and other differential signals. Both SWING and OH must meet the PP and CMR input requirements. Figures 4A to 4D show interface examples for the P/nP input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5 CML P 2.5 SSTL Zo = 60 Ohm R3 120 R4 120 P np P/nP Zo = 60 Ohm np P/nP FIGURE 4A. HIPERCLOCKS P/NP INPUT DRIEN BY A CML DRIER FIGURE 4B. HIPERCLOCKS P/NP INPUT DRIEN BY AN SSTL DRIER LPECL R3 R4 LDS_Driv er 100 Receiver FIGURE 4C. HIPERCLOCKS P/NP INPUT DRIEN BY A LPECL DRIER FIGURE 4D. HIPERCLOCKS P/NP INPUT DRIEN BY A LDS DRIER LPECL C1 R3 R4 P C2 np P/nP R R FIGURE 4E. HIPERCLOCKS P/NP INPUT DRIEN BY A LPECL DRIER WITH AC COUPLE IDT / ICS 9 9

10 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for = + 5% = 3.465, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core) MAX = _MAX * I _MAX = * 60mA = 208mW Power (outputs) MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 32.8mW = 295.2mW Total Power _MAX (3.465, with all outputs switching) = 208mW mW = 3.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for TM devices is C. The equation for Tj is as follows: Tj = θ JA * Pd_total + T A Tj = Junction Temperature θ JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1 C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85 C with all outputs switching is: 85 C + 0.3W * 42.1 C/W = C. This is well below the limit of C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θ JA for 32-pin LQFP, Forced Convection θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards 67.8 C/W 55.9 C/W.1 C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9 C/W 42.1 C/W 39.4 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT / ICS 10 10

11 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LHSTL output driver circuit and termination are shown in Figure 5. O Q1 OUT RL Ω FIGURE 5. HSTL DRIER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = ( /R ) * ( - ) OH_MIN L O_MAX OH_MIN Pd_L = ( /R ) * ( - ) OL_MAX L O_MAX OL_MAX Pd_H = (1.0/Ω) * (2-1.0) = 20mW Pd_L = (0.4/Ω) * (2-0.4) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW IDT / ICS 11 11

12 RELIABILITY INFORMATION TABLE 7. θ JA S. AIR FLOW TABLE FOR 32 LEAD LQFP θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards 67.8 C/W 55.9 C/W.1 C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9 C/W 42.1 C/W 39.4 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for is: 944 IDT / ICS 12 12

13 PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS SYMBOL JEDEC ARIATION ALL DIMENSIONS IN MILLIMETERS MINIMUM BBA NOMINAL N 32 MAXIMUM A A A b c D D BASIC 7.00 BASIC D Ref. E E BASIC 7.00 BASIC E Ref. e 0.80 BASIC L θ ccc Reference Document: JEDEC Publication 95, MS-026 IDT / ICS 13 13

14 TABLE 9. ORDERING INFORMATION Part/Order Number ICS8521BYI ICS8521BYIT ICS8521BYILF ICS8521BYILFT NOTE: Parts Marking ICS8521BYI ICS8521BYI ICS8521BYILF ICS8521BYILF Package Shipping Packaging 32 Lead LQFP tray Temperature -40 C to 85 C 32 Lead LQFP 1000 tape & reel -40 C to 85 C 32 Lead "Lead-Free" LQFP tray -40 C to 85 C 32 Lead "Lead-Free" LQFP 1000 tape & reel -40 C to 85 C that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, is a trademark of or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT / ICS 14 14

15 ICS ICS ICS1522 ICS8705 ICS1893BF Frequency User-Programmable ZERO 3.3- LOW SKEW, 10Base-T/100Base-TX DELAY, Generator 1-TO-4 1-TO-9 DIFFERENTIAL-TO-LCMOS/LTTL LCMOS/LTTL-TO- DIFFERENTIAL-TO-HSTL ideo & Clock Generator/ Buffers PHYceiver for Line-Locked LPECL FANOUT PENTIUM/Pro CLOCK FANOUT BUFFER Clock GENERATOR BUFFER Regenerator Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Device Technology, Inc Silver Creek alley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Device Technology, Inc. Accelerated Thinking is a service mark of Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX