FSA2859 Dual-Voltage, 0.8Ω DPDT Analog Switch with Power-Off Isolation

Transcription

1 Click here for this datasheet translated into Chinese! ugust 2008 F2859 Dual-Voltage, 0.8Ω DPDT nalog witch with Power-Off Isolation Features Power-Off Isolation (=0V) 0.8Ω Maximum On Resistance (R ON) for 4.5V 0.25Ω Maximum R ON Flatness for 4.5V Broad Operating Range: 1.65V to 5.5V Fast Turn-On and Turn-Off Times Control Input Referenced to V IO Break-Before-Make Enable Circuitry 0.5mm WLCP packaging ED Performance - HBM: JED22-114, I/O to 8kV - CDM: JED22-C V - IEC Contact / ir 8kV / 15kV pplications Cellular Phone Portable Media Player PD Ordering Information Description The F2859 is a high-performance Double-Pole / Double-Throw (DPDT) analog switch for audio applications driven by low voltage (1.8V) baseband processors or ICs. The device features ultra-low R ON of 0.8Ω (maximum) at 4.5V and operates over the wide range of 1.65V to 5.5V. The device is fabricated with sub-micron CMO technology to achieve fast switching speeds and is designed for break-before-make operation. The F2859 interfaces between the low-voltage IC and regular audio amplifiers and CODECs operating up to the supply range of 5.5V through the dual-voltage supplies of V IO and. The V IO supply operates the control circuitry, allowing for 1.8V (typical) signals on the control pin (n). IMPORTNT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Part Number Operating Temperature Range Top Mark Eco tatus F2859UCX -40 C to +85 C M2 Green Package 12-Ball WLCP, 0.5mm pitch Packing Method Tape and Reel For Fairchild s definition of green Eco tatus, please visit: nalog ymbols V IO Control 0 1 1B0 1B1 1 2B0 2B1 2 Figure 1. nalog ymbol F2859 Rev

2 Marking Information Pin Configuration Pin Definitions KK = Die Run Code X = Year Y = Work Week Z = ssembly ite Figure 2. Top Mark with Pin 1 Orientation D3 3 0 C3 4 1B1 B B D2 2 V IO C2 5 B D1 1 1 C1 6 2B1 B B0 Figure 3. Pin ssignments (Top Through View) Pin Ball Name Description 1 D1 1 Control Input 1 2 D2 V IO Digital Control upply 3 D3 0 Control Input 0 4 C3 1B1 Data Port (Normally Open) 5 C2 Ground 6 C1 2B1 Data Port (Normally Open) 7 B1 2 Common Data Port 2 8 B2 Ground 9 B3 1 Common Data Port B0 Data Port (Normally Closed) 11 2 upply Voltage B0 Data Port (Normally Closed) Truth Table Control Input (0,1) 0 = Low 1 = Low 0 = High 1 = High Function 1B0 connected to 1 2B0 connected to 2 1B1 connected to 1 2B1 connected to 2 F2859 Rev

3 bsolute Maximum Ratings tresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. ymbol Parameter Min. Max. Unit upply Voltage V V IO Digital Control upply Voltage V V sw witch Voltage (1) nb0, nb1, n V Input Voltage (1) 0, V I IK Input Diode Current -50 m I W witch Current (Continuous) 200 m I WPEK Peak witch Current Pulsed at 1ms Duration, <10% Duty Cycle 400 m P D Power Dissipation at 85 C 180 mw T TG torage Temperature Range C T J Maximum Junction Temperature +150 C T L Lead Temperature (oldering, 10 econds) +260 C ED Human Body Model (JEDEC: JED22-114) I/O to : 1, 2 8 ll Pins 2 Charged Device Model (JEDEC: JED22-C101) 500 V Machine Model (JEDEC: JED22-115) 100 V IEC Discharge system test performed on Contact 8 Fairchild s F2859 applications testing board ir 15 Note: 1 The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. kv kv Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to bsolute Maximum Ratings. ymbol Parameter Min. Max. Unit upply Voltage V V IO Digital Control upply V Control Input Voltage (2) 0, 1 0 V IO V V W witch Input Voltage nb0, nb1, n 0 V T Operating Temperature C θ J Thermal Resistance, till ir 350 C/W Note: 2 Control Input must be held HIGH or LOW; it must not float. F2859 Rev

4 Electrical Characteristics ll typical values are at 25 C unless otherwise specified. V IO=1.65 to 1.95V. ymbol Parameter (V) Conditions V IHIO V ILIO I IN I NO(0FF), I NC(OFF), I NO(On), I NC(On) I (ON) I OFF Input Voltage High - V IO Input Voltage Low - V IO Control Input Leakage Off-Leakage Current of Port nb0 and nb1 (3) On-Leakage Current of Port nb0 and nb1 (3) On Leakage Current of Port n (3) T =+25 C T =-40 to +85 C Min. Typ. Max. Min. Max to V IO V IO V 1.95 to V IO V 1.95 to 5.50 V 0,1=0 or V IO n Power Off Leakage Current of Port & Port B (3) 0 n=1v,4.5v nb0 or nb1=4.5, 1V n=1v,3.0v nb0 or nb1=3.0, 1V n=0.5v,2.3v nb0 or nb1=2.3, 0.5V n=0.3v,1.65v nb0 or nb1=1.65,0.3 V n=float nb0 or nb1=4.5, 1V n=float nb0 or nb1=3.0, 1V n=float nb0 or nb1=2.3, 0.5V n=float nb0 or nb1=1.65, 0.3V n=1v,4.5v; nb0 or nb1=1v, 4.5V or floating n=1v, 3.0V; nb0 or nb1=1v, 3.0V or floating n=0.5v, 2.3V; nb0 or nb1=0.5v, 2.3V or floating n=0.3v, 1.65V; nb0 or nb1=0.3v, 1.65V or floating n=0 to 5.5V ; nb0 or nb1=0 to 5.5V Unit n n n µ 5.50 =0 or, I OUT= I CC Quiescent upply Current 3.60 =0 or, I OUT= =0 or, I OUT= n 1.95 =0 or, I OUT= Continued on the following page F2859 Rev

5 Electrical Characteristics (Continued) ll typical values are at 25 C unless otherwise specified. V IO=1.65 to 1.95V. ymbol Parameter (V) Conditions R ON R ON R FLT(ON) witch On (3, 4) Resistance On Resistance Matching Between (3, 5) Channels On Resistance (3, 6) Flatness nb0 or nb1=2.5v nb0 or nb1=2.0v nb0 or nb1=1.8v nb0 or nb1=1.2v nb0 or nb1=2.5v nb0 or nb1=2.0v nb0 or nb1=1.8v nb0 or nb1=1.2v nb0 or nb1=1.0v, 1.5V, 2.5V nb0 or nb1=0.8v, 2.0V nb0 or nb1=0.8v, 1.8V T =+25 C T =-40 to +85 C Min. Typ. Max. Min. Max nb0 or nb1=0.6v, 1.2V 3.5 Notes: 3 Guaranteed by characterization, not production tested for = V. 4 On resistance is determined by the voltage drop between and B pins at the indicated current through the switch. 5 R ON=R ON maximum R ON minimum measured at identical, temperature, and voltage. 6 Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. Unit Ω Ω Ω F2859 Rev

6 C Electrical Characteristics ll typical value are at V IO=1.8V and =1.8V, 2.5V, 3.0V, and 5.0V at 25 C unless otherwise specified. ymbol Parameter (V) Conditions t ON Turn-On Time (7) t OFF Turn-Off Time (7) t BBM Q Break-Before- Make Time (7) Charge Injection OIRR Off Isolation 1.8 to 5.0 Xtalk Crosstalk 1.8 to 5.0 BW THD -3db Bandwidth Total Harmonic Distortion T =+25ºC T =-40 to +85ºC Min. Typ. Max. Min. Max to to 3.60 nb0 or nb1=, to 2.70 R L=50Ω, C L=35pF to to to 3.60 nb0 or nb1=, 2.30 to 2.70 R L=50Ω, C L=35pF to to to 3.60 nb0 or nb1=, to 2.70 R L=50Ω, C L=35pF to C L=1.0nF, V GEN=0V, R GEN=0Ω f=1mhz, R L=50Ω f=1mhz, R L=50Ω R L=50Ω R L=600Ω, =0.5V PP, f=20hz to 20kHz.002 Note: 7 Guaranteed by characterization, not production tested for = V. Unit Figure ns Figure 4 ns Figure 4 ns Figure 5 pc Figure 7-60 db Figure 6-65 db Figure 6 MHz Figure 9 % Figure 10 Capacitance ymbol Parameter (V) Conditions T =+25ºC Min. Typ. Max. Unit C IN Control Pin Input Capacitance 0 f=1mhz 3.2 pf C OFF nb Port Off Capacitance 1.65 to 5.50 f=1mhz 50 pf C ON n Port On Capacitance 1.65 to 5.50 f=1mhz 150 pf F2859 Rev

7 Test Diagrams V Bn B0 or B 1 R L 50 C L includes fixture and stray capacitance. V Bn B 0 Control Input B 1 C L 35pF C L includes fixture and stray capacitance. Control Input witch Output 0V 0V Figure 4. Turn On / Off Timing R L 50 C L 35pF Control Input 50% t ON t R = t F = 2.5ns t OFF 0.9 x 0.9 x Logic input waveforms inverted for switches that have the opposite logic sense. 0V Figure 5. Break-Before-Make Timing 50% T D t R = t F = 2.5ns 0.9 x 10nF 0 or Network nalyzer OFF-IOLTION = 20log ON-LO = 20log 50 B O B 1 ME REF CROTLK = 20log Figure 6. Off Isolation and Crosstalk F2859 Rev

8 Test Diagrams (Continued) V GEN R GEN B0 or B1 C L In Off On Off Control Input Capacitance Meter f = 1MHz Figure 7. Charge Injection 10nF B 0 or B 1 In Off 0V or Figure 8. On / Off Capacitance Measurement etup On Q = Δ C L Off Δ 10nF 10nF ignal Generator 0dBm B N R L nalyzer ignal Generator 0dBm B N R L nalyzer Logic Input 0V or Logic Input 0V or Figure 9. Bandwidth Figure 10. Harmonic Distortion F2859 Rev

9 Physical Dimensions 0.03 C 2X PIN 1 RE F G (Y)+/ D TOP VIEW C 1 2 E 0.05 C 3 D C B BOTTOM VIEW B D (X)+/ X F 0.03 C ETING PLNE C B 12x Ø0.260± C E IDE VIEW NOTE: (Ø0.200) CU PD RECOMMENDED LND PTTERN (NMD) 0.378± ±0.021 (Ø0.300) OLDER MK OPENING. NO JEDEC REGITRTION PPLIE. B. DIMENION RE IN MILLIMETER. C. DIMENION ND TOLERNCE PER MEY14.5M, D. DTUM C I DEFINED BY THE PHERICL CROWN OF THE BLL. E. PCKGE NOMINL HEIGHT I 586 MICRON ±39 MICRON ( MICRON). F. FOR DIMENION D, E, X, ND Y EE PRODUCT DTHEET. G. BLL D1 I DEIGNTED PIN 1. H. BLL COMPOITION: n95.5g3.9cu0.6 I. DRWING FILNME: MKT-UC012Brev2 Figure Ball, WLCP 0.5mm Pitch Table 1. Product pecific Dimensions Product D E X Y F2859UCX Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild emiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. lways visit Fairchild emiconductor s online packaging area for the most recent package drawings: F2859 Rev

10 F2859 Rev