FSA2859 Dual-Voltage, 0.8Ω DPDT Analog Switch with Power-Off Isolation
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- Barnaby Farmer
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1 Click here for this datasheet translated into Chinese! ugust 2008 F2859 Dual-Voltage, 0.8Ω DPDT nalog witch with Power-Off Isolation Features Power-Off Isolation (=0V) 0.8Ω Maximum On Resistance (R ON) for 4.5V 0.25Ω Maximum R ON Flatness for 4.5V Broad Operating Range: 1.65V to 5.5V Fast Turn-On and Turn-Off Times Control Input Referenced to V IO Break-Before-Make Enable Circuitry 0.5mm WLCP packaging ED Performance - HBM: JED22-114, I/O to 8kV - CDM: JED22-C V - IEC Contact / ir 8kV / 15kV pplications Cellular Phone Portable Media Player PD Ordering Information Description The F2859 is a high-performance Double-Pole / Double-Throw (DPDT) analog switch for audio applications driven by low voltage (1.8V) baseband processors or ICs. The device features ultra-low R ON of 0.8Ω (maximum) at 4.5V and operates over the wide range of 1.65V to 5.5V. The device is fabricated with sub-micron CMO technology to achieve fast switching speeds and is designed for break-before-make operation. The F2859 interfaces between the low-voltage IC and regular audio amplifiers and CODECs operating up to the supply range of 5.5V through the dual-voltage supplies of V IO and. The V IO supply operates the control circuitry, allowing for 1.8V (typical) signals on the control pin (n). IMPORTNT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Part Number Operating Temperature Range Top Mark Eco tatus F2859UCX -40 C to +85 C M2 Green Package 12-Ball WLCP, 0.5mm pitch Packing Method Tape and Reel For Fairchild s definition of green Eco tatus, please visit: nalog ymbols V IO Control 0 1 1B0 1B1 1 2B0 2B1 2 Figure 1. nalog ymbol F2859 Rev
2 Marking Information Pin Configuration Pin Definitions KK = Die Run Code X = Year Y = Work Week Z = ssembly ite Figure 2. Top Mark with Pin 1 Orientation D3 3 0 C3 4 1B1 B B D2 2 V IO C2 5 B D1 1 1 C1 6 2B1 B B0 Figure 3. Pin ssignments (Top Through View) Pin Ball Name Description 1 D1 1 Control Input 1 2 D2 V IO Digital Control upply 3 D3 0 Control Input 0 4 C3 1B1 Data Port (Normally Open) 5 C2 Ground 6 C1 2B1 Data Port (Normally Open) 7 B1 2 Common Data Port 2 8 B2 Ground 9 B3 1 Common Data Port B0 Data Port (Normally Closed) 11 2 upply Voltage B0 Data Port (Normally Closed) Truth Table Control Input (0,1) 0 = Low 1 = Low 0 = High 1 = High Function 1B0 connected to 1 2B0 connected to 2 1B1 connected to 1 2B1 connected to 2 F2859 Rev
3 bsolute Maximum Ratings tresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. ymbol Parameter Min. Max. Unit upply Voltage V V IO Digital Control upply Voltage V V sw witch Voltage (1) nb0, nb1, n V Input Voltage (1) 0, V I IK Input Diode Current -50 m I W witch Current (Continuous) 200 m I WPEK Peak witch Current Pulsed at 1ms Duration, <10% Duty Cycle 400 m P D Power Dissipation at 85 C 180 mw T TG torage Temperature Range C T J Maximum Junction Temperature +150 C T L Lead Temperature (oldering, 10 econds) +260 C ED Human Body Model (JEDEC: JED22-114) I/O to : 1, 2 8 ll Pins 2 Charged Device Model (JEDEC: JED22-C101) 500 V Machine Model (JEDEC: JED22-115) 100 V IEC Discharge system test performed on Contact 8 Fairchild s F2859 applications testing board ir 15 Note: 1 The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. kv kv Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to bsolute Maximum Ratings. ymbol Parameter Min. Max. Unit upply Voltage V V IO Digital Control upply V Control Input Voltage (2) 0, 1 0 V IO V V W witch Input Voltage nb0, nb1, n 0 V T Operating Temperature C θ J Thermal Resistance, till ir 350 C/W Note: 2 Control Input must be held HIGH or LOW; it must not float. F2859 Rev
4 Electrical Characteristics ll typical values are at 25 C unless otherwise specified. V IO=1.65 to 1.95V. ymbol Parameter (V) Conditions V IHIO V ILIO I IN I NO(0FF), I NC(OFF), I NO(On), I NC(On) I (ON) I OFF Input Voltage High - V IO Input Voltage Low - V IO Control Input Leakage Off-Leakage Current of Port nb0 and nb1 (3) On-Leakage Current of Port nb0 and nb1 (3) On Leakage Current of Port n (3) T =+25 C T =-40 to +85 C Min. Typ. Max. Min. Max to V IO V IO V 1.95 to V IO V 1.95 to 5.50 V 0,1=0 or V IO n Power Off Leakage Current of Port & Port B (3) 0 n=1v,4.5v nb0 or nb1=4.5, 1V n=1v,3.0v nb0 or nb1=3.0, 1V n=0.5v,2.3v nb0 or nb1=2.3, 0.5V n=0.3v,1.65v nb0 or nb1=1.65,0.3 V n=float nb0 or nb1=4.5, 1V n=float nb0 or nb1=3.0, 1V n=float nb0 or nb1=2.3, 0.5V n=float nb0 or nb1=1.65, 0.3V n=1v,4.5v; nb0 or nb1=1v, 4.5V or floating n=1v, 3.0V; nb0 or nb1=1v, 3.0V or floating n=0.5v, 2.3V; nb0 or nb1=0.5v, 2.3V or floating n=0.3v, 1.65V; nb0 or nb1=0.3v, 1.65V or floating n=0 to 5.5V ; nb0 or nb1=0 to 5.5V Unit n n n µ 5.50 =0 or, I OUT= I CC Quiescent upply Current 3.60 =0 or, I OUT= =0 or, I OUT= n 1.95 =0 or, I OUT= Continued on the following page F2859 Rev
5 Electrical Characteristics (Continued) ll typical values are at 25 C unless otherwise specified. V IO=1.65 to 1.95V. ymbol Parameter (V) Conditions R ON R ON R FLT(ON) witch On (3, 4) Resistance On Resistance Matching Between (3, 5) Channels On Resistance (3, 6) Flatness nb0 or nb1=2.5v nb0 or nb1=2.0v nb0 or nb1=1.8v nb0 or nb1=1.2v nb0 or nb1=2.5v nb0 or nb1=2.0v nb0 or nb1=1.8v nb0 or nb1=1.2v nb0 or nb1=1.0v, 1.5V, 2.5V nb0 or nb1=0.8v, 2.0V nb0 or nb1=0.8v, 1.8V T =+25 C T =-40 to +85 C Min. Typ. Max. Min. Max nb0 or nb1=0.6v, 1.2V 3.5 Notes: 3 Guaranteed by characterization, not production tested for = V. 4 On resistance is determined by the voltage drop between and B pins at the indicated current through the switch. 5 R ON=R ON maximum R ON minimum measured at identical, temperature, and voltage. 6 Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. Unit Ω Ω Ω F2859 Rev
6 C Electrical Characteristics ll typical value are at V IO=1.8V and =1.8V, 2.5V, 3.0V, and 5.0V at 25 C unless otherwise specified. ymbol Parameter (V) Conditions t ON Turn-On Time (7) t OFF Turn-Off Time (7) t BBM Q Break-Before- Make Time (7) Charge Injection OIRR Off Isolation 1.8 to 5.0 Xtalk Crosstalk 1.8 to 5.0 BW THD -3db Bandwidth Total Harmonic Distortion T =+25ºC T =-40 to +85ºC Min. Typ. Max. Min. Max to to 3.60 nb0 or nb1=, to 2.70 R L=50Ω, C L=35pF to to to 3.60 nb0 or nb1=, 2.30 to 2.70 R L=50Ω, C L=35pF to to to 3.60 nb0 or nb1=, to 2.70 R L=50Ω, C L=35pF to C L=1.0nF, V GEN=0V, R GEN=0Ω f=1mhz, R L=50Ω f=1mhz, R L=50Ω R L=50Ω R L=600Ω, =0.5V PP, f=20hz to 20kHz.002 Note: 7 Guaranteed by characterization, not production tested for = V. Unit Figure ns Figure 4 ns Figure 4 ns Figure 5 pc Figure 7-60 db Figure 6-65 db Figure 6 MHz Figure 9 % Figure 10 Capacitance ymbol Parameter (V) Conditions T =+25ºC Min. Typ. Max. Unit C IN Control Pin Input Capacitance 0 f=1mhz 3.2 pf C OFF nb Port Off Capacitance 1.65 to 5.50 f=1mhz 50 pf C ON n Port On Capacitance 1.65 to 5.50 f=1mhz 150 pf F2859 Rev
7 Test Diagrams V Bn B0 or B 1 R L 50 C L includes fixture and stray capacitance. V Bn B 0 Control Input B 1 C L 35pF C L includes fixture and stray capacitance. Control Input witch Output 0V 0V Figure 4. Turn On / Off Timing R L 50 C L 35pF Control Input 50% t ON t R = t F = 2.5ns t OFF 0.9 x 0.9 x Logic input waveforms inverted for switches that have the opposite logic sense. 0V Figure 5. Break-Before-Make Timing 50% T D t R = t F = 2.5ns 0.9 x 10nF 0 or Network nalyzer OFF-IOLTION = 20log ON-LO = 20log 50 B O B 1 ME REF CROTLK = 20log Figure 6. Off Isolation and Crosstalk F2859 Rev
8 Test Diagrams (Continued) V GEN R GEN B0 or B1 C L In Off On Off Control Input Capacitance Meter f = 1MHz Figure 7. Charge Injection 10nF B 0 or B 1 In Off 0V or Figure 8. On / Off Capacitance Measurement etup On Q = Δ C L Off Δ 10nF 10nF ignal Generator 0dBm B N R L nalyzer ignal Generator 0dBm B N R L nalyzer Logic Input 0V or Logic Input 0V or Figure 9. Bandwidth Figure 10. Harmonic Distortion F2859 Rev
9 Physical Dimensions 0.03 C 2X PIN 1 RE F G (Y)+/ D TOP VIEW C 1 2 E 0.05 C 3 D C B BOTTOM VIEW B D (X)+/ X F 0.03 C ETING PLNE C B 12x Ø0.260± C E IDE VIEW NOTE: (Ø0.200) CU PD RECOMMENDED LND PTTERN (NMD) 0.378± ±0.021 (Ø0.300) OLDER MK OPENING. NO JEDEC REGITRTION PPLIE. B. DIMENION RE IN MILLIMETER. C. DIMENION ND TOLERNCE PER MEY14.5M, D. DTUM C I DEFINED BY THE PHERICL CROWN OF THE BLL. E. PCKGE NOMINL HEIGHT I 586 MICRON ±39 MICRON ( MICRON). F. FOR DIMENION D, E, X, ND Y EE PRODUCT DTHEET. G. BLL D1 I DEIGNTED PIN 1. H. BLL COMPOITION: n95.5g3.9cu0.6 I. DRWING FILNME: MKT-UC012Brev2 Figure Ball, WLCP 0.5mm Pitch Table 1. Product pecific Dimensions Product D E X Y F2859UCX Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild emiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. lways visit Fairchild emiconductor s online packaging area for the most recent package drawings: F2859 Rev
10 F2859 Rev
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GENERAL DESCRIPTION The SGM4461 is a high-speed, low-voltage, advanced dual-independent double-pole/double-throw (DPDT) CMOS analog switch that is designed to operate from a single +1.8V to +5.5V power
Low-Voltage, Low R ON, SPDT Audio Switch with Negative Swing Capability
Low-Voltage, Low R ON, SPDT Audio Switch with Negative Swing Capability DG6, DG63 DESCRIPTION The DG6, DG63 is a low on-resistance, single-pole/ double-throw monolithic CMOS analog switch with negative
2 Port, USB 2.0 High Speed (480 Mbps) Switch, DPDT Analog Switch
2 Port, UB 2. High peed (48 Mbps) witch, DPDT Analog witch DG272 DECRIPTION The DG272 is 2 Port high speed analog switch optimized for UB 2. signal switching. The DG272 switch is configured in DPDT. It
FSAL200 Wide Bandwidth Quad 2:1 Analog Multiplexer / De-multiplexer Switch
FSAL200 Wide Bandwidth Quad 2:1 Analog Multiplexer / De-multiplexer Switch Features Typical 6Ω Switch Connection Between Two Ports Minimal Propagation Delay Through the Switch Low I CC Zero Bounce in Flow-Through
SGM7222 High Speed USB 2.0 (480Mbps) DPDT Analog Switch
GENERAL DECRIPTION The GM7222 is a high-speed, low-power double-pole/ double-throw (DPDT) analog switch that operates from a single 1.8V to 4.3V power supply. GM7222 is designed for the switching of high-speed
FSA2457 Dual DPDT, 5Ω Analog Data Switch
FSA2457 Dual DPDT, 5Ω Analog Data Switch Features Low On Capacitance for Data Path: 12pF Typical Low On Resistance for Data Path: 5Ω Typical Low Pow er Quiescent Consumption: 1μA Maximum Wide -3db Bandw
SGM4684 Chip Scale Packaging, Low-Voltage 0.4Ω, Dual, SPDT Analog Switch
GENERAL DESCRIPTION The SGM4684 is a dual, low on-resistance, low voltage, bidirectional, single-pole/double-throw (SPDT) CMOS analog switch designed to operate from a single 1.8V to 5.5V power supply.
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) STG3684
LOW VOLTAGE 0.5Ω MAX DUAL SPDT SWITCH WITH BREAK BEFORE MAKE FEATURE HIGH SPEED: t PD = 0.3ns (TYP.) at V CC = 3.0V t PD = 0.4ns (TYP.) at V CC = 2.3V ULTRA LOW POWER DISSIPATION: I CC = 0.2µA (MAX.) at
AS11P2TLR. Low voltage 1 Ω single-pole double-throw analog switch with breakbefore-make. Description. Features
Low voltage 1 Ω single-pole double-throw analog switch with breakbefore-make feature Description Datasheet - production data Features DFN6L High speed: t PD = 130 ps (typ.) at V CC = 3.0 V t PD = 140 ps
SGM Ω, High Speed, Low Voltage Dual, DPDT Analog Switch
GENERAL DESCRIPTION The SGM44601 is a high-speed, low-voltage, advanced dual-independent double-pole/double-throw (DPDT) CMOS analog switch that is designed to operate from a single +1.8V to +5.5V power
FST Bit Bus Switch
Features 4 Ω Switch Connection between Two Ports Minimal Propagation Delay through the Switch Low I CC Zero Bounce in Flow-through Mode Control Inputs Compatible with TTL Level Description December 2012
SGM3717 4Ω, 400MHz Bandwidth, Dual, SPDT Negative Signal Handling Analog Switch
Preliminary datasheet SGM3717 GENERAL DESCRIPTION The SGM3717 is a dual, bidirectional, single-pole/ double-throw (SPDT) CMOS analog switch designed to operate from a single +2.5V to +5.0V supply. It features
SGM Ω, High Speed, Low Voltage Dual, DPDT Analog Switch
GENERAL DESCRIPTION The SGM44599 is a high-speed, low-voltage, advanced dual-independent double-pole/double-throw (DPDT) CMOS analog switch that is designed to operate from a single +1.8V to +5.5V power
SGM Ω, High Speed, Low Voltage Dual, DPDT Analog Switch
GENERAL DESCRIPTION The SGM4462 is a dual, high-speed, low-voltage, double-pole/double-throw (DPDT) CMOS analog switch that is designed to operate from a single 1.8V to 5.5V power supply. It features high-bandwidth
DG2706. High Speed, Low Voltage, 3, Quad SPDT CMOS Analog Switch. Vishay Siliconix DESCRIPTION FEATURES APPLICATIONS
High Speed, Low Voltage, 3, Quad SPDT CMOS Analog Switch DESCRIPTION The DG2706 is a high speed, low voltage, low On-resistance, quad SPDT (single pole double throw) analog switch. It operates from a.6
2 Port, USB 2.0 High Speed (480 Mbps) Switch, DPDT Analog Switch
2 Port, UB 2. High peed (48 Mbps) witch, DPDT Analog witch DG273 DECRIPTION The DG273 is 2 port high speed analog switch optimized for UB 2. signal switching. The DG273 switch is configured in DPDT. It
NC7SZ157 TinyLogic UHS 2-Input Non-Inverting Multiplexer
NC7SZ157 TinyLogic UHS 2-Input Non-Inverting Multiplexer Features Broad CC Operating Range: 1.65 to 5.5 Ultra High-Speed Power Down High-Impedance Inputs/Outputs Over-oltage Tolerance Inputs Facilitate
Automotive 125 C Analog Switch Dual DPDT / Quad SPDT, 0.37, 338 MHz Bandwidth
Automotive 125 C Analog Switch Dual DPDT / Quad SPDT, 0.37, 338 MHz Bandwidth DESCRIPTION The, is a four-channel single-pole double-throw (SPDT) analog switch with two control inputs. It is also known
FSUSB22 Low-Power, 2-Port, High-Speed USB 2.0 (480Mbps) Switch
March 2008 FSUSB22 Low-Power, 2-Port, High-Speed USB 2.0 (480Mbps) Switch Features -40dB Off Isolation at 250MHz -40dB Non-adjacent Channel Crosstalk at 250MHz On Resistance: 4.5Ω Typical (RON) -3dB Bandwidth:
700 MHz, -3 db Bandwidth; Single SPDT Analog Switch
7 MHz, -3 db Bandwidth; Single SPDT Analog Switch DESCRIPTION is a low R ON, high bandwidth analog switch configured in single SPDT. It achieves 5 switch on resistance, greater than 7 MHz -3 db bandwidth
Description. Features. Application. Pin Assignment. Pin Description. Logic Function Table PI5A3158B
Low oltage Dual SPDT Analog Switch 2:1 Mux/Demux Bus Switch Features CMOS Technology for Bus and Analog Applications Low On-Resistance: 8Ω at 3.0 Wide Range: 1.65 to 5.5 Rail-to-Rail Signal Range Control
PI5A3158B Low Voltage Dual SPDT Analog Switch 2:1 Mux/Demux Bus Switch
2:1 Mux/Demux Bus Switch Features CMOS Technology for Bus and Analog Applications Low On-Resistance: 8Ω at 3.0 Wide Range: 1.65 to 5.5 Rail-to-Rail Signal Range Control Input Overvoltage Tolerance: 5.5(Min)
Power-off Isolation, 6, 1.8 V to 5.5 V, SPDT Analog Switch (2:1 Multiplexer)
Power-off Isolation,,. V to 5.5 V, SPDT Analog Switch (: Multiplexer) DESCRIPTION The is a high performance single-pole, double-throw (SPDT) analog switch designed for. V to 5.5 V operation with a single
SGM3003 Ultra Low ON-Resistance, Low Voltage, SPDT Analog Switch
GENERAL DESCRIPTION The SGM3003 is a single, low on-resistance, low voltage, bidirectional, single-pole/double-throw (SPDT) CMOS analog switch designed to operate from a single +1.8V to +5.5V supply. Targeted
Low-Voltage Single SPDT Analog Switch
Low-Voltage Single SPDT Analog Switch DG22 DESCRIPTION The DG22 is a single-pole/double-throw monolithic CMOS analog switch designed for high performance switching of analog signals. Combining low power,
Power-off Protection, 6, 1.8 V to 5.5 V, SPDT Analog Switch (2:1 Multiplexer)
Power-off Protection,,. V to 5.5 V, SPDT Analog Switch (: Multiplexer) DESCRIPTION The is a high performance single-pole, double-throw (SPDT) analog switch designed for. V to 5.5 V operation with a single
SGM Ω, 300MHz, Low-Power Full-Speed USB (12Mbps) Switch
GENERAL ESCRIPTION The SGM2258 is a high-performance, dual, single-pole/ double-throw (SPT) CMOS analog switch designed for switching USB 1.1 signals. High bandwidth and low on-resistance make this switch
STG3699B. Low voltage 0.5 Ω max, quad SPDT switch with break-before-make feature. Features. Description
Low voltage 0.5 Ω max, quad SPDT switch with break-before-make feature Features High speed: t PD = 1.5 ns (typ.) at V CC = 3.0 V t PD = 1.5 ns (typ.) at V CC = 2.3 V Ultra low power dissipation: I CC =0.2μA
SGM Ω, 300MHz, Low-Power Full-Speed USB (12Mbps) Switch
GENERAL ESCRIPTION The SGM2258 is a high-performance, dual, single-pole/ double-throw (SPT) CMOS analog switch designed for switching USB 1.1 signals. High bandwidth and low on-resistance make this switch
NC7SZ57 / NC7SZ58 TinyLogic UHS Universal Configurable Two-Input Logic Gates
NC7SZ57 / NC7SZ58 TinyLogic UHS Universal Configurable Two-Input Logic Gates Features Ultra High Speed Capable of Implementing any Two-Input Logic Functions Typical Usage Replaces Two (2) TinyLogic Gate
NC7SZ14 TinyLogic UHS Inverter with Schmitt Trigger Input
January 2010 NC7SZ14 TinyLogic UHS Inverter with Schmitt Trigger Input Features Ultra-High Speed: t PD 3.7ns (Typical) into 50pF at 5 CC High Output Drive: ±24mA at 3 CC Broad CC Operating Range: 1.65
SGM Ω, Low Voltage Quad, SPDT Analog Switch
GENERAL DESCRIPTION The SGM3699 is a quad, low on-resistance, low voltage, bidirectional, single-pole/double-throw (SPDT) CMOS analog switch that is designed to operate from a single 1.8V to 4.35V power
Dual SPDT Analog Switch
Dual SPDT Analog Switch DESCRIPTION The DG9236 is a CMOS, dual SPDT analog switch designed to operate from = 2.7 V to = 6 V max. operating, single supply. All control logic inputs have a guaranteed.8 V
TOP VIEW COM2. Maxim Integrated Products 1
19-3472; Rev ; 1/4 Quad SPST Switches General Description The quad single-pole/single-throw (SPST) switch operates from a single +2V to +5.5V supply and can handle signals greater than the supply rail.
WAS4799Q WAS4799Q. Order information. Low On Resistance, Quad SPDT Analog Switch. Http//:
WAS4799Q Low On Resistance, Quad SPDT Analog Switch Descriptions The WAS4799Q is a high performance, quad, Single Pole Double Throw (SPDT) analog switch that features ultra-low Ron of 0.5 Ω (typical) at
STG5682. Low voltage dual SPDTswitch with negative rail capability. Features. Description
Low voltage dual SPDTswitch with negative rail capability Features Distortion-free negative signal throughput down to V CC -5.5V Wide operating voltage range: V CC (Opr) = 1.65V to 4.5V single supply Ultra
Low Voltage, Dual SPDT Analog Switch with Charge Pump
Low Voltage, Dual SPDT Analog Switch with Charge Pump DG, DG, DG DESCRIPTION The DG, DG, DG are monolithic CMOS analog switching products designed for high performance switching of analog signals. Combining
2.5Ω, Low-Voltage, SPST/SPDT Analog Switches in UCSP Package
19-242; Rev 1; 2/3 2.5Ω, Low-Voltage, SPST/SPDT General Description The low on-resistance (R ON ), low-voltage analog switches operate from a single +1.8V to +5.5V supply. The / are single-pole/single-throw
NC7SZ86 TinyLogic UHS Two-Input Exclusive-OR Gate
NC7SZ86 TinyLogic UHS Two-Input Exclusive-OR Gate Features Ultra-High Speed: t PD 2.9ns (Typical) into 50pF at 5 CC High Output Drive: ±24mA at 3 CC Broad CC Operating Range: 1.65 to 5.5 Matches Performance
74AUP1G95 TinyLogic Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
74UPG9 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Features 0.8 V to.6 V V Supply Operation.6 V Over-Voltage Tolerant I/Os at V from 0.8V to.6 V Extremely High Speed
DG1411E, DG1412E, DG1413E. 1.5 On Resistance, ± 15 V / +12 V / ± 5 V, Quad SPST Switches. Vishay Siliconix.
1.5 On Resistance, ± 15 / +12 / ± 5, Quad SPST Switches DESCRIPTION The are ± 15 precision monolithic quad single-pole single-throw (SPST) CMOS analog switches. Built on a new CMOS process, the ishay Siliconix
NC7SZ08 TinyLogic UHS Two-Input AND Gate
NC7SZ08 TinyLogic UHS Two-Input AND Gate Features Ultra-High Speed: t PD 2.7ns (Typical) into 50pF at 5 CC High Output Drive: ±24mA at 3 CC Broad CC Operating Range: 1.65 to 5.5 Matches Performance of
Low-Voltage Single-Supply, SPDT Analog Switch in SC-70
Low-oltage Single-Supply, SPDT Analog Switch in SC-7 DESCRIPTION The DG499 is a cost effective upgrade to other types of 499 low-voltage, single-pole/double-throw analog switches available in the industry
STG3220. Low voltage high bandwidth dual SPDT switch. Features. Description. Applications
Low voltage high bandwidth dual SPDT switch Features Ultra low power dissipation: I CC = 1 μa (max.) at T A = 85 C Low "ON" resistance: R ON = 4.8 Ω (T A = 25 ºC) at V CC = 4.3 V R ON = 5.9 Ω (T A = 25
NC7WZ07 TinyLogic UHS Dual Buffer (Open-Drain Outputs)
April 2013 NC7WZ07 TinyLogic UHS Dual Buffer (Open-Drain Outputs) Features Ultra-High Speed: t PZL 2.3 ns (Typical) High I OL Output Drive: ±24 ma at 3 CC Broad CC Operating Range: 1.65 to 5.50 Power Down
NC7SZU04 TinyLogic UHS Unbuffered Inverter
NC7SZU04 TinyLogic UHS Unbuffered Inverter Features Unbuffered for Crystal Oscillator and Analog Applications Balanced Output Drive: ±16mA at 4.5 CC Broad CC Operating Range: 1.65 to 5.5 Matches Performance