NB100LVEP V / 3.3V ECL DUAL Differential 2:1 Multiplexer

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1 NB00VEP56 2.5V / 3.3V EC UA ifferentil 2: Multiplexer escription The NB00VEP56 is dul, fully differentil 2: multiplexer. The differentil dt pth mkes the device idel for multiplexing low skew clock or differentil dt signls. The device fetures both individul nd common select inputs to ddress both dt pth nd rndom logic pplictions. Common nd individul selects cn ccept both VEC nd VCMOS input voltge levels. Multiple V BB pins re provided. The V BB pin, n internlly generted voltge supply, is vilble to this device only. For single ended input opertion, the unused differentil input is connected to V BB s switching reference voltge. V BB my lso rebis AC coupled inputs. When used, decouple V BB nd vi 0.0 F cpcitor nd limit current sourcing or sinking to ma. When not used, V BB should be left open. Fetures Mximum Input Clock Frequency > 2.5 GHz Typicl Mximum Input t Rte > 2.5 Gb/s Typicl 525 ps Typicl Propgtion elys ow Profile QFN Pckge PEC Mode Operting Rnge: = V to 3.8 V with = 0 V NEC Mode Operting Rnge: = 0 V with = V to 3.8 V Seprte, Common Select, nd Individul Select (Comptible with EC nd CMOS Input Voltge evels) Q Output Will efult OW with Inputs Open or t Multiple V BB Outputs These evices re Pb Free nd re RoHS Complint T SUFFIX CASE 948E PIN QFN MN SUFFIX CASE 485 MARKING IAGRAMS* N00 VP56 AYW 24 N00 VP56 AYW A = Assembly oction = Wfer ot Y = Yer W = Work Week = Pb Free Pckge (Note: Microdot my be in either loction) *For dditionl mrking informtion, refer to Appliction Note AN8002/. ORERING INFORMATION See detiled ordering nd shipping informtion in the pckge dimensions section on pge 8 of this dt sheet. Semiconductor Components Industries, C, 204 Mrch, 204 Rev. 0 Publiction Order Number: NB00VEP56/

2 NB00VEP56 Tble. PIN FUNCTION ESCRIPTION Pin No. ÁÁÁÁÁÁÁÁ TSSOP QFN 4,20 3,9,8,9, 20 Nme I/O efult Stte escription Positive Supply Voltge. All VCC Pins must be Externlly Connected to Power Supply to Gurntee Proper Opertion. 5,24 Negtive Supply Voltge. All VEE Pins must be Externlly Connected to Power Supply to Gurntee Proper Opertion. 3,8 6,2 V BB0, V BB EC Reference Voltge Output 4 0 EC Input ow Noninverted ifferentil t Input to MUX 0. Internl 75 k to EC Input High Inverted ifferentil t Input to MUX 0. Internl 75 k to nd 37 k to b EC Input ow Noninverted ifferentil t b Input to MUX 0. Internl 75 k to b EC Input High Inverted ifferentil t b Input to MUX 0. Internl 75 k to nd 37 k to. 6 0 EC Input ow Noninverted ifferentil t Input to MUX. Internl 75 k to. 7 EC Input High Inverted ifferentil t Input to MUX. Internl 75 k to nd 37 k to. 9 3 b EC Input ow Noninverted ifferentil t b Input to MUX. Internl 75 k to. 0 4 b EC Input High Inverted ifferentil t b Input to MUX. Internl 75 k to nd 37 k to. 9 2 Q0 EC Output Noninverted ifferentil Output MUX 0. Typiclly Terminted with to V TT = 2.0 V. 8 Q0 EC Output Inverted ifferentil Output MUX 0. Typiclly Terminted with to V TT = 2.0 V. 3 7 Q EC Output Noninverted ifferentil Output MUX. Typiclly Terminted with to V TT = 2.0 V. 2 6 Q EC Output Inverted ifferentil Output MUX. Typiclly Terminted with to V TT = 2.0 V SE0 EC, CMOS Input 6 22 COM_SE EC, CMOS Input 5 2 SE EC, CMOS Input ow ow ow Noninverted ifferentil Select Input to MUX 0. Internl 75 k to. Noninverted ifferentil Common Select Input to Both MUX. Internl 75 k to. Noninverted ifferentil Select Input to MUX. Internl 75 k to. N/A EP Exposed Pd. (Note ). The thermlly conductive exposed pd on the pckge bottom (see cse drwing) must be ttched to het sinking conduit. 2

3 NB00VEP56 0 R 2 0 Q0 0b R 2 0b R 2 0 Q0 SE0 COM_SE SE Q Tble 2. TRUTH TABE SE0 X H H SE X H H COM_SE H Q0, Q0 b b Q, Q b b b R 2 0 Q b 20 0 Q Figure. ogic igrm V BBO Q0 SE0 0b COM_SE 0b SE Q V BB Q NB00VEP b 0 b Figure 2. ed Pinout (Top View) Q0 8 Q0 0 0 V BB COM SE0 SE SE NB00VEP b 0b V BB Exposed Pd (EP) Q Q b b Figure 3. ed Pinout (Top View) Tble 3. ATTRIBUTES Chrcteristics Vlue Internl Input Pulldown Resistor (R) 75 k Internl Input Pullup Resistor (R2) 37 k ES Protection Humn Body Model Mchine Model Chrged evice Model > 2 kv > V > 2 kv Moisture Sensitivity (Note ) Pb Pkg Pb Free Pkg evel evel evel evel Flmmbility Rting Oxygen Index: 28 to 34 U 94 V 0.25 in Trnsistor Count Meets or exceeds JEEC Spec EIA/JES78 IC tchup Test. For dditionl informtion, see Appliction Note AN8003/. 354 evices 3

4 NB00VEP56 Tble 4. MAXIMUM RATINGS Symbol Prmeter Condition Condition 2 Rting Unit Positive Mode Power Supply = 0 V 6 V Negtive Mode Power Supply = 0 V 6 V V I Positive Mode Input Voltge Negtive Mode Input Voltge = 0 V = 0 V V I 6 V I 6 V V I out Output Current Continuous Surge 00 ma ma I BB V BB Sink/Source ma T A Operting Temperture Rnge 40 to +85 C T stg Storge Temperture Rnge 65 to + C JA Therml Resistnce (Junction to Ambient) JEEC 5 3 (S Single yer Test Bord) 0 lfpm 0 lfpm 40 C/W C/W JA Therml Resistnce (Junction to Ambient) JEEC 5 6 (2S2P Multi yer Test Bord) with Filled Therml Vis 0 lfpm 0 lfpm JC Therml Resistnce (Junction to Cse) Stndrd Bord to 4 C/W C/W C/W T sol Wve Solder Pb Pb Free Stresses exceeding those listed in the Mximum Rtings tble my dmge the device. If ny of these limits re exceeded, device functionlity should not be ssumed, dmge my occur nd relibility my be ffected C Tble 5. C CHARACTERISTICS, PEC = 2.5 V, = 0 V (Note 2) Symbol Chrcteristic 40 C 25 C 85 C Min Typ Mx Min Typ Mx Min Typ Mx I EE Negtive Power Supply Current ma V OH Output HIGH Voltge (Note 3) V O Output OW Voltge (Note 3) V IH Input HIGH Voltge (SE0, SE, COM_SE) Input HIGH Voltge ( Inputs) (Note 4) Unit V I Input OW Voltge (SE0, SE, COM_SE) Input OW Voltge ( Inputs) (Note 4) V IHCMR Input HIGH Voltge Common Mode Rnge (ifferentil Configurtion) (Note 5) V I IH Input HIGH Current (@V IH ) A I I Input OW Current (@V I ) SE NOTE: evice will meet the specifictions fter therml equilibrium hs been estblished when mounted in test socket or printed circuit bord with mintined trnsverse irflow greter thn 0 lfpm. Electricl prmeters re gurnteed only over the declred operting temperture rnge. Functionl opertion of the device exceeding these conditions is not implied. evice specifiction limit vlues re pplied individully under norml operting conditions nd not vlid simultneously. 2. Input nd output prmeters vry : with. cn vry 0.25 V to +.3 V. 3. All loding with to 2.0 V. 4. o not use V BB t < 3.0 V. 5. V IHCMR min vries : with, V IHCMR mx vries : with. The V IHCMR rnge is referenced to the most positive side of the differentil input signl. A 4

5 NB00VEP56 Tble 6. C CHARACTERISTICS, PEC = 3.3 V, = 0 V (Note 6) Symbol Chrcteristic 40 C 25 C 85 C Min Typ Mx Min Typ Mx Min Typ Mx I EE Negtive Power Supply Current ma V OH Output HIGH Voltge (Note 7) V O Output OW Voltge (Note 7) V IH Input HIGH Voltge (SE0, SE, COM_SE) Input HIGH Voltge ( Inputs) Unit V I Input OW Voltge (SE0, SE, COM_SE) Input OW Voltge ( Inputs) V BB Output Reference Voltge (Note 8) V IHCMR Input HIGH Voltge Common Mode Rnge (ifferentil Configurtion) (Note 9) V I IH Input HIGH Current (@V IH ) A I I Input OW Current (@V I ) SE NOTE: evice will meet the specifictions fter therml equilibrium hs been estblished when mounted in test socket or printed circuit bord with mintined trnsverse irflow greter thn 0 lfpm. Electricl prmeters re gurnteed only over the declred operting temperture rnge. Functionl opertion of the device exceeding these conditions is not implied. evice specifiction limit vlues re pplied individully under norml operting conditions nd not vlid simultneously. 6. Input nd output prmeters vry : with. cn vry + V to 0.3 V. 7. All loding with to 2.0 V. 8. Single Ended input opertion is limited to 3.0 V in PEC mode. 9. V IHCMR min vries : with, V IHCMR mx vries : with. The V IHCMR rnge is referenced to the most positive side of the differentil input signl. A Tble 7. C CHARACTERISTICS, NEC = 0 V, = 3.8 V to V (Note 0) Symbol Chrcteristic 40 C 25 C 85 C Min Typ Mx Min Typ Mx Min Typ Mx I EE Negtive Power Supply Current ma V OH Output HIGH Voltge (Note ) V O Output OW Voltge (Note ) V IH V I Input HIGH Voltge (SE0, SE, COM_SE) Input HIGH Voltge ( Inputs) Input OW Voltge (SE0, SE, COM_SE) Input OW Voltge ( Inputs) V BB Output Reference Voltge (Note 2) V IHCMR Input HIGH Voltge Common Mode Rnge (ifferentil Configurtion) (Note 3) V I IH Input HIGH Current (@V IH ) A I I Input OW Current (@V I ) SE NOTE: evice will meet the specifictions fter therml equilibrium hs been estblished when mounted in test socket or printed circuit bord with mintined trnsverse irflow greter thn 0 lfpm. Electricl prmeters re gurnteed only over the declred operting temperture rnge. Functionl opertion of the device exceeding these conditions is not implied. evice specifiction limit vlues re pplied individully under norml operting conditions nd not vlid simultneously. 0.Input nd output prmeters vry : with.. All loding with to 2.0 V. 2.Single Ended input opertion is limited to from 3.0 V to 5.5 V in NEC mode. 3.V IHCMR min vries : with, V IHCMR mx vries : with. The V IHCMR rnge is referenced to the most positive side of the differentil input signl. Unit A 5

6 NB00VEP56 Tble 8. AC CHARACTERISTICS = 0 V; = V to 3.8 V or = V to 3.8 V; = 0 V (Note 4) 40 C 25 C 85 C Symbol Chrcteristic V OUTPP Output Voltge Amplitude f in GHz (See Figure 4) f in = 2 GHz f in = 2.5 GHz t PH, t PH Propgtion ely to Output ifferentil to Q, Q SE to Q, Q COM_SE to Q, Q t Skew Pulse Skew (Note 5) Within evice Input Skew (Note 6) Within evice Output Skew (Note 7) evice to evice Skew (Note 8) t JITTER RMS Rndom Clock Jitter (Note GHz Pek to Pek t ependent Jitter (Note GHz V INPP Input Voltge Swing (ifferentil Configurtion) (Note 2) Min Typ Mx Min Typ Mx Min Typ Mx Unit ps ps ps t r Output Rise/Fll MHz Q, Q t f (20% 80%) ps NOTE: evice will meet the specifictions fter therml equilibrium hs been estblished when mounted in test socket or printed circuit bord with mintined trnsverse irflow greter thn 0 lfpm. Electricl prmeters re gurnteed only over the declred operting temperture rnge. Functionl opertion of the device exceeding these conditions is not implied. evice specifiction limit vlues re pplied individully under norml operting conditions nd not vlid simultneously. 4.Mesured using 7 source, % duty cycle clock source. All loding with to 2.0 V. Input edge rtes ps (20% 80%). 5.Pulse Skew t PH t PH 6.Worst cse difference between 0 nd 0b (or between or b), when both output come from sme input. 7. Worst cse difference between Q0 nd Q outputs. 8. Skew is mesured between outputs under identicl trnsitions. 9. Additive RMS jitter with % uty Cycle Clock Signl. 20.Additive Pek to Pek jitter with input NRZ dt t PRBS Input voltge swing is single ended mesurement operting in differentil mode. 8 OUTPUT VOTAGE AMPITUE () Q AMP () INPUT FREQUENCY (GHz) Figure 4. Output Voltge Amplitude (V OUTPP ) vs. Input Frequency (f in ) t = 2.5 V, 25 C 6

7 NB00VEP56 Q Q V INPP = V IH () V I () V OUTPP = V OH (Q) V O (Q) t PH t PH Figure 5. AC Reference Mesurement river evice Q Q Z o = Z o = Receiver evice V TT V TT = 2.0 V Figure 6. Typicl Termintion for Output river nd evice Evlution (See Appliction Note AN8020/ Termintion of EC ogic evices.) 7

8 NB00VEP56 ORERING INFORMATION evice Pckge Shipping NB00VEP56TG NB00VEP56TR2G NB00VEP56MNG (Pb Free) (Pb Free) (Pb Free) 75 Units / Ril 20 Tpe & Reel 92 Units / Ril NB00VEP56MNR2G (Pb Free) 3000 Tpe & Reel For informtion on tpe nd reel specifictions, including prt orienttion nd tpe sizes, plese refer to our Tpe nd Reel Pckging Specifiction Brochure, BR80/. Resource Reference of Appliction Notes AN405/ EC Clock istribution Techniques AN406/ esigning with PEC (EC t +5.0 V) AN3/ ECinPS I/O SPiCE Modeling Kit AN4/ Metstbility nd the ECinPS Fmily AN568/ Interfcing Between VS nd EC AN672/ The EC Trnsltor Guide AN800/ Odd Number Counters esign AN8002/ Mrking nd te Codes AN8020/ Termintion of EC ogic evices AN8066/ Interfcing with ECinPS AN8090/ AC Chrcteristics of EC evices 8

9 NB00VEP56 PACKAGE IMENSIONS CASE 948E 02 ISSUE C 0.5 (0.006) T 0.5 (0.006) T U 2X /2 PIN IENT U S S C (0.004) T SEATING PANE 20X K REF 0.0 (0.004) M T U S V S 0 A V G H B U N J J N K K ÍÍÍÍ ÍÍÍÍ SECTION N N F ETAI E 0.25 (0.00) ETAI E SOERING FOOTPRINT* M W NOTES:. IMENSIONING AN TOERANCING PER ANSI Y4.5M, CONTROING IMENSION: MIIMETER. 3. IMENSION A OES NOT INCUE MO FASH, PROTRUSIONS OR GATE BURRS. MO FASH OR GATE BURRS SHA NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCUE INTEREA FASH OR PROTRUSION. INTEREA FASH OR PROTRUSION SHA NOT EXCEE 0.25 (0.00) PER SIE. 5. IMENSION K OES NOT INCUE AMBAR PROTRUSION. AOWABE AMBAR PROTRUSION SHA BE 0.08 (0.003) TOTA IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIA CONITION. 6. TERMINA NUMBERS ARE SHOWN FOR REFERENCE ONY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PANE W. MIIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC H J J K K BSC BSC M PITCH 6X X.26 IMENSIONS: MIIMETERS *For dditionl informtion on our Pb Free strtegy nd soldering detils, plese downlod the ON Semiconductor Soldering nd Mounting Techniques Reference Mnul, SOERRM/. 9

10 NB00VEP56 PACKAGE IMENSIONS QFN24, 4x4, P CASE 485 ISSUE B PIN REFEENCE 2X 0.5 C 2X 0.5 C NOTE C 0.08 C ETAI A ÉÉ ÉÉ TOP VIEW 7 ETAI B 2 A3 SIE VIEW 3 A B E A A 24X E2 C EXPOSE Cu SEATING PANE X b e 0.0 C A B e/ C NOTE 3 BOTTOM VIEW ETAI A ATERNATE CONSTRUCTIONS ÉÉÉ ÇÇÇ MO CMP A ETAI B ATERNATE TERMINA CONSTRUCTIONS A3 ÉÉÉ NOTES:. IMENSIONING AN TOERANCING PER ASME Y4.5M, CONTROING IMENSION: MIIMETERS. 3. IMENSION b APPIES TO PATE TERMINA AN IS MEASURE BETWEEN 0.25 AN 0.30 MM FROM THE TERMINA TIP. 4. COPANARITY APPIES TO THE EXPOSE PA AS WE AS THE TERMINAS. MIIMETERS IM MIN MAX A A A REF b BSC E 4.00 BSC E e 0 BSC RECOMMENE SOERING FOOTPRINT X PITCH 24X 0.32 IMENSIONS: MIIMETERS ECinPS is trdemrk of Semiconductor Components Industries, C (SCIC). ON Semiconductor nd re registered trdemrks of Semiconductor Components Industries, C (SCIC). SCIC owns the rights to number of ptents, trdemrks, copyrights, trde secrets, nd other intellectul property. A listing of SCIC s product/ptent coverge my be ccessed t Mrking.pdf. SCIC reserves the right to mke chnges without further notice to ny products herein. SCIC mkes no wrrnty, representtion or gurntee regrding the suitbility of its products for ny prticulr purpose, nor does SCIC ssume ny libility rising out of the ppliction or use of ny product or circuit, nd specificlly disclims ny nd ll libility, including without limittion specil, consequentil or incidentl dmges. Typicl prmeters which my be provided in SCIC dt sheets nd/or specifictions cn nd do vry in different pplictions nd ctul performnce my vry over time. All operting prmeters, including Typicls must be vlidted for ech customer ppliction by customer s technicl experts. SCIC does not convey ny license under its ptent rights nor the rights of others. SCIC products re not designed, intended, or uthorized for use s components in systems intended for surgicl implnt into the body, or other pplictions intended to support or sustin life, or for ny other ppliction in which the filure of the SCIC product could crete sitution where personl injury or deth my occur. Should Buyer purchse or use SCIC products for ny such unintended or unuthorized ppliction, Buyer shll indemnify nd hold SCIC nd its officers, employees, subsidiries, ffilites, nd distributors hrmless ginst ll clims, costs, dmges, nd expenses, nd resonble ttorney fees rising out of, directly or indirectly, ny clim of personl injury or deth ssocited with such unintended or unuthorized use, even if such clim lleges tht SCIC ws negligent regrding the design or mnufcture of the prt. SCIC is n Equl Opportunity/Affirmtive Action Employer. This literture is subject to ll pplicble copyright lws nd is not for resle in ny mnner. PUBICATION ORERING INFORMATION ITERATURE FUFIMENT: iterture istribution Center for ON Semiconductor P.O. Box 563, enver, Colordo 8027 USA Phone: or Toll Free USA/Cnd Fx: or Toll Free USA/Cnd Emil: orderlit@onsemi.com N. Americn Technicl Support: Toll Free USA/Cnd Europe, Middle Est nd Afric Technicl Support: Phone: Jpn Customer Focus Center Phone: ON Semiconductor Website: Order iterture: For dditionl informtion, plese contct your locl Sles Representtive NB00VEP56/

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