QUATERNARY LOGIC LOOK UP TABLE FOR CMOS CIRCUITS

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1 QUATERNARY LOGIC LOOK UP TABLE FOR CMOS CIRCUITS Anu Varghese 1,Binu K Mathew 2 1 Department of Electronics and Communication Engineering, Saintgits College Of Engineering, Kottayam 2 Department of Electronics and Communication Engineering, Saintgits College Of Engineering, Kottayam Abstract Interconnections are increasingly one of the dominant contributors to delay, area and energy consumption in CMOS digital circuits now a days. Multiple Valued Logic (MVL) can decrease the average power required for level transitions and also the number of required interconnections are reduced. So the impact of interconnections on overall energy consumption is reduced. In this paper, a quaternary Look Up Table (LUT) structure is designed to replace or complement binary LUTs in Field Programmable Gate Array (FPGA)s. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltage mode structures. A half adder prototype based on the designed LUT, fabricated in a standard 180-nm CMOS technology, able to work at 100 MHz is developed. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design. Index Terms - Field-programmable gate array (FPGA), Look Up Table (LUT), Multiple-Valued Logic (MVL), Quaternary Logic, Standard CMOS technology. I. INTRODUCTION The importance of interconnect in VLSI circuits increases with each new technology node. As transistors shrink with each new technology node, their weight in defining the main circuit characteristics, namely, area, delay or power, reduces in relative terms to interconnect. Moreover, higher integration allows for circuits with a larger number of active elements which affects in increasing the complexity of the required interconnect, both in number and length of wires. Multiplevalued logic (MVL) has been proposed in the past as a means to reduce the number of wires in a circuit. Increased data density, reduced dynamic power dissipation, and increased computational ability are some of the key benefits of MVL. In theory, a wire carrying a signal with N logic levels can replace log2 N wires carrying binary signals. Hence, the required number of wires may be significantly reduced. In turn, less wiring allows for a more packed layout, reducing the average interconnects length. Besides the immediate area gains, this compounded effect leads to less switched capacitance with benefits in delay and power consumption. Quaternary logic (radix-4-valued) is chosen as the base radix for the work reported here. Using a quaternary radix, it offers all the benefits of MVL such as reduced area due to signal routing reduction along with the important advantage of being able to easily interface with traditional binary logic. Quaternary logic offers a means to reduce interconnect since each circuit wire can, in principle, carry the same information as two binary wires. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltage mode structures. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features. The CMOS process has evolved by shrinking the transistors and employing lower supply voltages (lower VDD), therefore saving power and integrating more functionality into the same area. However, capacitance C also includes the routing capacitance associated with the wires connecting the logic gates. Routing is exceeding transistors contributions for latency and power dissipation of designs in modern CMOS processes. This is particularly challenging in modern FPGAs, where the power spent in routing may reach up to 70% of the overall consumption. Routing reduction leads to a direct reduction of the line capacitances and the overall circuit area which enables increase in the All Rights Reserved 131

2 operation frequency and reduction in the power consumption. Furthermore, supply voltage reduction is limited by practical boundaries; the transistors threshold voltage (Vth) cannot be reduced proportionally to the power supply voltage as it leads to an increasing leakage current, therefore increasing the static consumption of CMOS circuits. The exposed limitations encourage the exploration of circuit and system-level techniques to achieve higher energy efficiency. This may include dropping conventional noise margins of binary levels and, therefore, dealing with lesscomfortable noise margins of the MVL logic should be considered. However, previously reported implementations of MVL either present high power consumption, due to current-mode circuit elements or require nonstandard multi threshold CMOS technologies. These drawbacks have prevented MVL from being competitive when compared with binary logic. This paper proposes a novel view of MVL circuits through the design of a look up table (LUT) based on the quaternary representation that exploits simple voltage mode standard CMOS circuits. The proposed MVL LUT (Quaternary LUT) can replace or complement conventional binary logic, since the designed circuit is simple and efficient. II. LITERATURE SURVEY Multiple valued logic system is offering significant advantage like compact and easy development of circuits. A number of researchers have been working for evolution of multi valued logic system. A. CMOS TERNARY LOGIC CIRCUITS In this subsection, different types of multiple value logic are discussed along with its advantages and challenges. In addition to employing multiple power sources and multiple thresholds, a new theory of transmission functions for designing CMOS ternary logic circuits is described. [14].The main advantages of ternary circuits are listed below: (a) Since 3 is the smallest radix higher than binary, ternary functions and circuits have the simpler form and construction. They can be studied and discussed easily, yet they still display the characteristics of multi valued elements (b) As a measure of the cost or complexity of multi valued circuits, the product of the radix and the number of signals has been proposed. Since 3 is the digit nearest to e = 2.718, ternary circuits will be more economical according to this measure. (c) If balanced ternary logic (1, 0, - 1) is used, the same hardware may be used for addition and for subtraction (d) Since 3 is not an integral power of 2, research on ternary logic may disclose design techniques that are overlooked in the study of binary or quaternary logic. B. QUATERNARY LOGIC CIRCUITS Quaternary logic has shown to be a promising alternative for implementing FPGAs, since the quaternary circuits can reduce the circuits cost and at the same time reduces its power consumption. Field Programmable Gate Arrays are very convenient and flexible hardware platforms for the implementation of these systems, helping designers to cope with one of the more demanding requirements currently imposed on the industry: time to market. Their flexibility comes at a price in order to allow the many different interconnection schemes of the increasing number of devices in a single FPGA, an enormous area of the circuit must be used to implement all the required switches and wires. As technology evolves according to Moore s Law, providing ever smaller, faster, and lower voltage devices, the amount of interconnections inside a single chip is increasing significantly When considering FPGAs, this problem becomes even more critical, since the huge amount of interconnections impacts not only the circuit delay, but also the power consumption and area. MVL has received increased attention in the last decades because of the possibility to represent the information with more than two discrete All Rights Reserved 132

3 As a result, there is a possibility to increase the amount of information transferred using a single wire. In a VLSI circuit, interconnection plays the dominant role in every part of the circuit, nearly 70 percent of the area depends on interconnection, 20 percent of the area depends on insulation, and remaining 10 percent to devices. Binary logic is limited due to interconnect which occupies a large area on a VLSI chip. An approach to mitigate the impact of interconnections is to use MVL. Hence, more information can be carried in each wire, thus reducing the routing network. Reducing interconnect be the way to a direct reduction of line capacitances and the area. Therefore, this results in increasing the maximum operation frequency and also reducing the power consumption. Several implementation methods have been proposed to realize the MVL circuits. They can fundamentally be categorized as currentmode, voltage-mode and mixed-mode circuits. Several prototype chips of current-mode CMOS circuits have been fabricated, showing somewhat better performances compared to the corresponding binary circuits. Even though current-mode circuits have been popular and offer several benefits, the power consumption is high due to their inherent nature of constant current flow during the operation. Alternatively, voltage-mode circuits consume a large majority of power only during the logic level switching. III. QUATERNARY LOOK UP TABLE A. QUATERNARY LOGIC AND LUT A quaternary variable can assume four different logic levels. Assuming a rail-to-rail voltage range and equal noise margins for the four logic levels, three different reference voltage values are required, 1/6VDD, 3/6VDD, and 5/6VDD, to determine a quaternary value. This is shown in Fig.1. Since a quaternary variable (Q) is able to carry twice information as a binary variable (B), we have the following relation: Q = 2 B. Fig 1: Quaternary logic and reference voltage levels [1] Therefore, two binary variables may be grouped into one quaternary variable without information loss, merging two nodes into one. There is no direct conversion of binary to quaternary logic gates in conventional CMOS, since the binary circuits use the available power rails to represent the binary symbols. For quaternary logic there are two more intermediate levels, which cannot be obtained directly using the same techniques. A LUT is an array indexing operator, where the output is mapped by the input, based on the configuration memory. The configuration values are initially stored in the LUT configuration memory, and according to the input, the logic value in the addressed position is assigned to the output. By properly programming the LUT configuration memory, the LUT can implement any logic function with the given number of inputs and outputs, making it very practical to implement reconfigurable hardware, such as All Rights Reserved 133

4 . A quaternary function implemented by a QLUT is defined as g : Qk Q, over a set of quaternary input variables Y = (y0,..., yk 1), where the values of a variable yi and the function g(y ) are defined in Q = {0, 1, 2, 3}. In general, if l is the number of logic levels, the total number of different functions F that can be implemented in a LUT is given by F = l n lk where n is the number of outputs and k is the number of inputs. For a LUT with a single output (n = 1), the number of different functions for binary (l = 2) and quaternary (l = 4) representations are given, respectively, by: F2 = 2 2^k = 4 k F4 = 4 4^k = 256 k. The number of possible functions that may be represented in a quaternary LUT is much larger than in a binary LUT with the same number of inputs and outputs. Therefore, apart from reducing the total number of connections, MVL also leads to a reduction of the total number of gates when compared with a binary implementation. B. QLUT TOPOLOGY AND IMPLEMENTATION Fig 2: Quaternary LUT [1] The 2-input 1-output QLUT is shown in Fig For this given QLUT complexity, 16 quaternary configuration inputs are necessary, one for each possible combination of the two quaternary inputs. The configuration word defines the reconfigurable quaternary function. In practice, the input signals are used to select which one of the configuration inputs is connected to the output. This QLUT is composed of two main blocks: a 16-1 multiplexer using an array of switches, that establishes a low-resistance path between one configuration input and the output according to the input values; and a quaternary-to-binary decoder, consisting of a 2-bit analog-to-digital (ADC) frontend followed by combinational logic used to generate the control signals feeding the All Rights Reserved 134

5 Fig 3: Two input QLUT [10] C MULTIPLEXER Due to the quaternary nature of its inputs, the 16-1 multiplexer shown in Fig.3 may be thought of as an analog multiplexer. The output is assumed to be of a capacitive nature and its value is defined by the interconnection network to which the QLUT output is connected. For a binary FPGA this value can go up to tens of pf [10]. We used the typical value for a binary FPGA (10 pf), since it allows us to consider that maintaining the same number of wires, we can increase the functionality within the FPGA. The multiplexer path is usually implemented by Transmission G ates (TGs), which can be modelled by a simple RC circuit, as shown in Fig. 4. Fig 4: Multiplexer path RC model [2] D. QUATERNARY TO BINARY DECODER The 2-bit quaternary-to-binary decoder allows the use of a single row of transmission gates to drive the input configuration signals to the output of the QLUT. To do so, it is necessary to generate 16 control signals, to be applied inputs of each transmission gate. These transmission gates are employed to connect one quaternary configuration input to the output. To generate the required control signals, the quaternary variables are decoded into binary, allowing the use of binary logic All Rights Reserved 135

6 Thus, an ADC frontend is necessary, considering the analog nature of the quaternary signals. Inverting self-referenced comparators implemented is shown in Fig. 4, where Qi is a quaternary input of the QLUT. The main advantage of this structure, over previously proposed implementations is that it only uses standard CMOS structures. Fig 5: Self Referenced Comparators [3] Table 1: Q Decoder output as a function of quaternary input Table 1 shows the Q-decoder binary output logic values as function of the quaternary input Q. Outputs Q0 to Q3 determine which transmission gates in Fig.6 are propagating the configuration value ci ϵ C to the QLUT output w. The values for the controlling signals Q0, Q1, Q2 and Q3 are binary values, meaning 0 (0V) or 12 (VDD). Fig 6: Quaternary Decoder logic structure [1] The Q-decoder outputs may be considered as flags that determine which quaternary value is applied to Q-decoder input. Once we are able to determine the quaternary value in the Q-decoder input Q, the transmission gates connected to the Q-decoder outputs may be properly controlled. In other words, with the Q-decoder structure we are able to convert a quaternary input to a 4-bit word in one-hot codification and its inverted value. The CP and CN are self-reference analog comparators shown in Fig.5. For our quaternary device, we need three voltage references in order to determine a quaternary value, at 1/6VDD, 3/6VDD and 5/6VDD, as depicted in Fig.1 IV. SIMULATION AND RESULTS In order to analyse the performance of LUT implemented using quaternary logic, the working of a half adder made of Quaternary as well as binary is simulated and parameters such as delay, transistor count, power dissipation were observed and compared. A. QLUT All Rights Reserved 136

7 Fig 7: Simulation set up of Q Decoder The Q-decoder was implemented with the TSMC180nm technology. Simulations waveforms are shown in Fig. 2, where Q-decoder outputs are shown as expected and described in Table 1. The largest propagation delay from the Q-decoder input to the outputs (Q to Q2) is 196ps for this technology. This result is very important, because an inverter connected to the same transmission gates (i.e., same output load) presents a 81ps propagation delay, and the transmission gates are the main contributors to the look-up table propagation delay B. QUATERNARY HALF ADDER IMPLEMENTATION Fig 8: Quaternary half adder high level All Rights Reserved 137

8 Fig 9: Simulation set up of quaternary half adder The adder is just a prototype to explain the logical function of quaternary logic. The adder designed using mux is used. in quaternary logic can be converted to binary logic and addition can be performed in binary logic. Binary results of addition can be displayed in quaternary logic after conversion. C. SIMULATION RESULTS OF HALF ADDER USING QUATERNARY AND BINARY Fig 10: Simulation waveform of half adder using binary logic Fig 11: Simulation Waveform of half adder using quaternary logic From the above shown fig 10 and fig 11, It is clear that a delay difference of about 10 nano seconds is observed. Table 2: Comparison of device performance of binary V/s Quaternary Half All Rights Reserved 138

9 Table 2 exhibits the differences in various parameters obtained from the simulation results. For the same applied frequency of 100 MHz, and a supply voltage of 1.8 V, the reduction shown in the transistor count, delay, rise/fall time and power consumption is large. Experimental results are shown in Table 2, where the quaternary structure proposed in this paper outperforms the binary implementation in both power consumption and propagation delay. The propagation delay is simply the largest delay from an input to the output of each LUT. In a practical implementation of a FPGA, there will be a smaller number of interconnections due to the quaternary representation, and hence we will also be able to reduce the wire length, and the parasitic capacitance will be smaller, as a consequence. For this reason, we expect to have better results than the ones presented in this paper, when developing a complete FPGA, based on the proposed circuits, to implement the quaternary logic. Fig 12: Consumption V/s Output load capacitance[2] D. VARIABILITY AND NOISE MARGIN IN QUATERNARY CIRCUITS In current sub-micron and future technologies, process variability and reduced noise margin are important challenges for the development of multiple-valued devices. Voltage-mode multiple-valued logic devices present reduced voltage levels to represent logic values in comparison to binary circuits, and for this reason they may be, in theory, more susceptible to errors. Noise levels are indeed reduced in quaternary circuits due to the fact that there are four voltage levels while keeping the same supply voltage. In the last years, supply voltages have been reduced from 5V to 3.3V and recently to 1V. This is a huge reduction in the noise margin and circuits have successfully coped with it. V. CONCLUSION This work has aimed at the design and implementation of an innovative QLUT design that can be used for multiple valued combinational logic or as a building block in FPGAs. The QLUT internal functionality is implemented using simple standard CMOS structures. This feature is achieved through a quaternary-to-binary decoder that quantizes the input signals. This decoder is based on voltage-mode self-referenced comparators that allows the use of a standard CMOS technology and overcomes previous design drawbacks. One important factor on the implementation of circuits in quaternary FPGAs is related to the obtained results in terms of the expected circuit performance and power consumption. The reduced number of transistors and wires will have direct impact on the circuit area and power consumption. Indirectly, reduced wire length associated to smaller interconnection capacitances will be the key for the development of faster circuits. As a All Rights Reserved 139

10 extension, a Clock Boosting technique can be used instead of transmission gates to decrease the switches resistance and increase the operation frequency, while at the same time, achieving low power consumption. Therefore, the presented design is a valid solution to reduce the interconnections impact, with reduced power consumption or losing performance. REFERENCES 1. Diogo Brito, Quaternary Logic Lookup Table in Standard CMOS,IEEE transactions on VLSI systems, Vol. 23, No. 2, February J. Rabaey, Low Power Design Essentials (Integrated Circuits and Systems), NY, USA: Springer-Verlag, L. Shang, A. S. Kaviani, and K. Bathala, Dynamic power consumption in virtex-ii FPGA family, in Proc. ACM/SIGDA Int. Symp. Field-Program. Gate Arrays, 2002, pp Z. Zilic and Z. Vranesic, Multiple-valued logic in FPGAs, in Proc. Midwest Symp. Circuits Syst., 1993, pp E. Ozer, R. Sendag, and D. Gregg, Multiple-valued logic buses for reducing bus energy in low-power systems, IEE Comput. Digital Tech., vol. 153, no. 4, pp , Jul K. Current, Current-mode CMOS multiple-valued logic circuits, IEEE J. Solid-State Circuits, vol. 29, no. 2, pp , Feb J. Kim, An area efficient multiplier using current-mode quaternary logic technique, in Proc. 10th IEEE Int. Solid- State Integr. Circuit Technol., Nov. 2010, pp W. S. Chu and W. Current, Current-mode CMOS quaternary multiplier circuit, Electron. Lett., vol. 31, no. 4, pp , R. Silva, C. Lazzari, H. Boudinov, and L. Carro, CMOS voltage mode quaternary look-up tables for multi-valued FPGAs, Microelectron.J., vol. 40, no. 10, pp , C. Lazzari, J. Fernandes, P. Flores, and J. Monteiro, An efficient low power multiple-value look-up table targeting quaternary FPGAs, in Integrated Circuit and System Design. Power and Timing Modeling,Optimization, and Simulation 11. J. H. Anderson and F. N. Najm, Power estimation techniques for FPGAs, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 10, pp , Oct J. Uyemura, Circuit Design for CMOS VLSI. Boston, MA, USA: Kluwer Academic Publishers, T. G. Rabuske, C. R. Rodrigues, and S. Nooshabadi, A 5MSps 8-bit SAR ADC with single-ended or differential input, Microelectron. J.,vol. 43, no. 10, pp , WU, X.W. and PROSSER, F.P: CMOS Ternary sequential circuit IEEE Proceedings of ISMVL, 1988, pp. All Rights Reserved 140