Dual, Low-Voltage Linear Regulator Controllers with External MOSFETs

Transcription

1 19-375; Rev ; 5/5 EVLUTION KIT VILLE ual, Low-Voltage Linear Regulator ontrollers General escription The dual high-power linear regulator controllers use external n-channel MOSFETs to generate two independent low-voltage supplies for notebook computers. The delivers low output voltages from. to 2. (±5mV no-load accuracy). The external components allow scalable current design with loads up to 5 with excellent load regulation (1%). The regulator operates from a low input voltage, which also reduces the power dissipation in the external n-channel MOSFET. The controller powers the external MOSFET gate driver from the standard system supply. The includes current and thermal limits to prevent damage to the linear regulator. The uses an external resistive divider to fold back the current limit, reducing the overall power dissipation. The uses an external resistive-divider in series with the current-sense input (S_), providing foldback current-limit protection, and effectively reducing the short-circuit power dissipation. n output undervoltage timeout is available for low-cost applications that omit the current-sense resistor. The output undervoltage (UVP) timing depends on the magnitude of the voltage at V OUT. The UVP detects and shuts down the LO if the output voltage drops out of regulation. The controller uses an adjustable reference input (REFIN_) to set the nominal output voltage (V OUT_ ), which minimizes the cost and makes the stability independent of the output voltage. Each linear regulator features an adjustable soft-start function, and generates a delayed power-good (PGOO) signal that signals when the linear regulator is in regulation. The is a low-cost solution requiring few external components and is available in a small, 4mm x 4mm, 16-pin thin QFN package. Notebook and esktop omputers Point-of-Load Regulators V MH and V P PU Supplies Low-Voltage ias Supplies Servers pplications Features Low-ost ual Linear Regulators Output Voltage ccuracy ±5mV Independent. to 2. Reference Inputs Foldback urrent-limit Protection Output Undervoltage-Lockout Protection Thermal Limit (Internal Sensor) 1.V to 5. Input Supply Voltage (External FET rain) ias Supply Voltage Independent Power-Good Open-rain Outputs Independent Enable Inputs Soft-Shutdown Output ischarge Low Supply urrent (.5m) 5µ (max) Shutdown Supply urrent PRT ETE TOP VIEW RV2 N.. GN RV N.. Ordering Information TEMP RNGE PIN-PKGE -4 to Thin QFN-EP* 4mm x 4mm ETE+ -4 to Thin QFN-EP* 4mm x 4mm *EP = Exposed pad. +enotes lead-free packaging. S2 OUT2 REFIN Pin onfiguration EN1 EN2 PGOO1 PGOO V S1 OUT1 REFIN1 4mm x 4mm TQFN Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/allas irect! at , or visit Maxim s website at

2 SOLUTE MXIMUM RTINGS V to GN...-.3V to +6V OUT1, OUT2 to GN...-.3V to +6V REFIN1, REFIN2, PGOO1, PGOO2, EN1, EN2 to GN...-.3V to +6V RV1, RV2, S1, S2 to GN...-.3V to (V +.3V) ontinuous Power issipation (T = +7 ) 16-Pin 4mm x 4mm Thin QFN (derated 25mW/ above +7 )...2mW Operating Temperature Range ETE...-4 to +85 Junction Temperature Storage Temperature Range to +15 Lead Temperature (soldering, 1s)...+3 Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELETRIL HRTERISTIS (V =, EN_ = S_ = V, V REFIN = 1.V, T = to +85, unless otherwise noted. Typical values are at T = +25.) PRMETER SYMOL ONITIONS MIN TYP MX UNITS Supply Voltage Range V V V Undervoltage Lockout Threshold Rising edge, 2mV hysteresis (typ) V V Quiescent Supply urrent I EN1 = EN2 = V.5 1 m V Shutdown Supply urrent EN1 = EN2 = GN.1 5 µ REFIN to OUT Offset Voltage V OUT _ mv OUT_ Input ias urrent I OUT _ µ RIVERS RV_ Output Voltage Swing (Note 1) Output high; V OUT _ = V REFIN _ - 25mV, I LO = 1m Output low; V OUT _ = V REFIN _ + 25mV, I LO = 1m V -.3 V RV_ Maximum Sourcing urrent V OUT _ = V REFIN _ - 25mV; V RV = 3V 6 14 m RV_ Maximum Sinking urrent V OUT _ = V REFIN _ + 25mV; V RV = 3V 6 14 m OUT_ to RV_ Transconductance (Large Signal) RV_ Power-Supply Rejection Ratio G MRV.8 S 1Hz < f < 1kHz, I RV = 1m, RV = 1nF V -8 d RV_ Soft-Start harging urrent I SOFT µ REFERENE INPUT REFIN_ Voltage Range V REFIN _ V = 4.7 to V REFIN_ Input ias urrent I REFIN _ V REFIN _ = to n FULT PROTETION Thermal Shutdown Threshold T SHN Hysteresis = urrent-limit Threshold V ILIM V S _ - V OUT _ T = to T = S_ Input urrent µ Linear Regulator UVP Threshold (Slow) UVP (SLOW) With respect to V REFIN ; S_ = V % mv 2

3 ELETRIL HRTERISTIS (continued) (V =, EN_ = S_ = V, V REFIN = 1.V, T = to +85, unless otherwise noted. Typical values are at T = +25.) PRMETER SYMOL ONITIONS MIN TYP MX UNITS Linear Regulator UVP Threshold (Fast) UVP (FST) With respect to V REFIN ; S_ = V % Slow Short-ircuit Timer uration t UVP(SLOW) With respect to V REFIN ; S_ = V 75 µs Fast Short-ircuit Timer uration t UVP(FST) With respect to V REFIN ; S_ = V 5 µs ischarge-mode On-Resistance OUT_ Pin INPUTS N OUTPUTS R OUT 1 Ω EN_ Input Low Level.6 V EN_ Input High Level Rising edge, 2mV (typ) hysteresis 1.6 V Enable Leakage urrent µ Power-Good Trip Threshold (Lower) With respect to error comparator threshold, hysteresis = 4% (falling edge) % Power-Good Startup elay 2 ms Power-Good Propagation elay t PGOO OUT_ forced 2% beyond PGOO_ trip threshold 1 µs Power-Good Output Low Voltage I SINK = 4m.3 V Power Good Leakage urrent I V OUT _ = 1.V (PGOO_ high impedance), 1 µ ELETRIL HRTERISTIS (V =, EN_ = S_ = V, V REFIN = 1.V, T = -4 to +85, unless otherwise noted.) (Note 2) PRMETER SYMOL ONITIONS MIN TYP MX UNITS Supply Voltage Range V V V Undervoltage Lockout Threshold Rising edge 2mV hysteresis (typ) V V Quiescent Supply urrent I EN1 = EN2 = V 1.5 m V Shutdown Supply urrent EN1 = EN2 = GN 5 µ REFIN to OUT Offset Voltage V OUT _ mv RIVERS RV_ Output Voltage Swing (Note 1) Output high; V OUT _ = V REFIN _ - 25mV; I LO = 1m Output low; V OUT _ = V REFIN _ + 25mV: I LO = 1m RV_ Maximum Sourcing urrent V OUT _ = V REFIN _ - 25mV; V RV = 3V 3.5 m RV_ Maximum Sinking urrent V OUT _ = V REFIN _ + 25mV; V RV = 3V 3.5 m RV_ Soft-Start harging urrent I SOFT 4 4 µ V V 3

4 ELETRIL HRTERISTIS (continued) (V =, EN_ = S_ = V, V REFIN = 1.V, T = -4 to +85, unless otherwise noted.) (Note 2) PRMETER SYMOL ONITIONS MIN TYP MX UNITS REFERENE INPUT REFIN_ Voltage Range V REFIN _ V = 4.7 to V FULT PROTETION urrent-limit Threshold V ILIM V S _ - V OUT _ mv Linear Regulator UVP Threshold (Slow) Linear Regulator UVP Threshold (Fast) INPUTS N OUTPUTS UVP (SLOW) With respect to V REFIN ; S_ = V % UVP (FST) With respect to V REFIN ; S_ = V % EN_ Input Low Level.6 V EN_ Input High Level 1.6 V Power-Good Trip Threshold (Lower) With respect to error comparator threshold, hysteresis = 4% (falling edge) % Power-Good Output Low Voltage I SINK = 4m.3 V Note 1: Low threshold n-channel MOSFET is required for 2. (±2%) output. Note 2: Specifications to -4 are guaranteed by design, not production tested. (ircuit of Figure 1, T = +25, unless otherwise noted.) Typical Operating haracteristics OUTPUT-VOLTGE EVITION (mv) OUTPUT-VOLTGE EVITION vs. LO URRENT V OUT = LO URRENT () toc1 URRENT LIMIT () FOLK URRENT LIMIT vs. OUTPUT VOLTGE toc2 3V 1. SOFT-STRT (EN RISING EGE) ms/div OUTPUT VOLTGE (V). EN1, /div. RV1, 2V/div NO LO toc3. LO1 OUTPUT, 1V/div. PGOO1, /div 4

5 Typical Operating haracteristics (continued) (ircuit of Figure 1, T = +25, unless otherwise noted.) 3V 1. SOFT-STOP (EN FLLING EGE) toc4 3V 1. SOFT-STRT (UVLO RISING EGE) toc5 3V 1. SOFT-STOP (UVLO FLLING EGE) toc6 1µs/div 2ms/div 2ms/div. EN1, /div. RV1, 2V/div NO LO. LO1 OUTPUT, 1V/div. PGOO1, /div. IS (V ), /div. RV1, 2V/div NO LO, EN = V. LO1 OUTPUT, 1V/div. PGOO1, /div. IS (V ), /div. RV1, 2V/div NO LO, EN = V. LO1 OUTPUT, 1V/div. PGOO1, /div LO TRNSIENT (.1 TO 2.1) toc7 LO TRNSIENT (NO LO TO 2) toc8 LO TRNSIENT (NO LO TO 2) toc V 2.8V 1.51V V 1µs/div. ONTROL SIGNL. LO URRENT, 2/div. RV1, 5mV/div. LO1 OUTPUT VOLTGE, 1mV/div 2 3.2V 2.7V 1.7V µs/div. ONTROL SIGNL. LO URRENT, 2/div. RV1, 1V/div. LO1 OUTPUT VOLTGE, 5mV/div 2 3.2V 2.7V µs/div. ONTROL SIGNL. LO URRENT, 2/div. RV1, 1V/div. LO1 OUTPUT VOLTGE, 5mV/div 5

6 Typical Operating haracteristics (continued) (ircuit of Figure 1, T = +25, unless otherwise noted.) SMPLE PERENTGE (%) 1V 3V FOLK URRENT LIMIT (SHORT-IRUIT RESPONSE) OUT1 OUT2 2µs/div. GTE OF FET LO, 1V/div. RV1, 1V/div. MOSFET URRENT, 2/div toc1. L1 OUTPUT VOLTGE, 2V/div E. PGOO1, /div RV TRNSONUTNE ISTRIUTION SMPLE SIZE = TRNSONUTNE (S) E toc13 SMPLE PERENTGE (%) OUTPUT-VOLTGE EVITION (mv) OUT1 OUT2 OUTPUT OFFSET VOLTGE ISTRIUTION SMPLE SIZE = OUTPUT OFFSET VOLTGE (mv) OUTPUT-VOLTGE EVITION vs. TEMPERTURE toc14 GIN N PHSE (OUT1) toc TEMPERTURE ( ) FREQUENY (MHz) GIN N PHSE 1. OUTPUT, 1 LO, OUT = (1) 1µF V ERMI (OUT2) toc16 toc11 GIN (d) SMPLE PERENTGE (%) OUT1 OUT2 URRENT-LIMIT THRESHOL ISTRIUTION SMPLE SIZE = URRENT LIMIT (mv) toc12 GIN (d) PHSE ( ) FREQUENY (MHz) 1. OUTPUT, 2 LO, OUT = (1) 22µF 126 6V ERMI 6 PHSE ( )

7 PIN NME FUNTION Pin escription 1 V nalog and river Supply Input. onnect to the system supply voltage (+5.V). ypass V to analog ground with a 1µF or greater ceramic capacitor. 2 S1 3 OUT1 Positive urrent-sense Input for LO1. To enable (foldback) current limit, connect S1 to the positive terminal of the current-sense element as shown in Figure 1. The driver reduces the gate voltage when the 1mV (typ) current-limit threshold is exceeded. When S1 is connected to V, the disables the current-limit protection and enables the output undervoltage protection (see the UVP Short-ircuit Protection section). Outp ut Feed b ack- S ense, N eg ati ve ur r ent- S ense, and i schar g e Inp ut for L O 1. onnect d i r ectl y to the l i near r eg ul ator outp ut. W hen L O1 i s d i sab l ed, OU T1 i s d i schar g ed thr oug h an i nter nal 1Ω FE T to GN. 4 REFIN1 External Reference Input for LO1. REFIN1 sets the main output regulation voltage (V OUT1 = V REFIN1 ). 5 PGOO2 6 PGOO1 7 EN2 8 EN1 9 REFIN2 Open-rain Power-Good Output for LO2. PGOO2 is low when the output voltage is more than 12% (typ) below the normal regulation point, during soft-start, and in shutdown. pproximately 2ms (typ) after OUT2 reaches the regulation voltage (REFIN2), PGOO2 becomes high impedance as long as the output remains in regulation. Open-rain Power-Good Output for LO1. PGOO1 is low when the output voltage is more than 12% (typ) below the normal regulation point, during soft-start, and in shutdown. pproximately 2ms (typ) after OUT1 reaches the regulation voltage (REFIN1), PGOO1 becomes high impedance as long as the output remains in regulation. Enable Input for LO2. onnect EN2 to Vcc for always ON. When EN2 is pulled low, the linear regulator shuts down and pulls the output to ground. Enable Input for LO1. onnect EN1 to Vcc for always ON. When EN1 is pulled low, the linear regulator shuts down and pulls the output to ground. External Reference Input for the Secondary Regulator (LO2). REFIN2 sets the main output regulation voltage (V OUT2 = V REFIN2 ). 1 OUT2 Output Sense, Negative urrent-sense Input, and ischarge Input for the Secondary Regulator (LO2). onnect directly to the linear regulator output. When the LO2 is disabled, OUT2 is discharged through an internal 1Ω FET to GN. 11 S2 Positive urrent-sense Input for LO2. To enable (foldback) current limit, connect S2 to the positive terminal of the current-sense element as shown in Figure 1. The driver reduces the gate voltage when the 1mV (typ) current-limit threshold is exceeded. When S2 is connected to V, the disables the current-limit protection and enables the output undervoltage protection (see the UVP Short-ircuit Protection section). 12, 14 N.. Not Internally onnected 13 RV2 External N-hannel Gate rive for LO2 15 GN Ground. onnect the thin QFN backside pad to GN. 16 RV1 External N-hannel Gate rive for LO1 EP Exposed Pad. onnect the thin QFN backside pad to GN. 7

8 etailed escription The is a dual, low-dropout, external n-channel linear regulator controller for low-voltage notebook computer power supplies. The linear regulator provides a. to 2. (±5mV no-load) output for powering the low-voltage supplies to desktop and notebook PU chipsets (V P and V _ MH ). The regulator operates from low input voltage, which also reduces the power dissipation in the external n-channel MOSFET. The controller powers the external MOSFET gate driver from the standard system supply. The controller features independent enable inputs (EN_), PGOO outputs (PGOO_), input undervoltage lockout (UVLO), and output undervoltage protection (UVP). The controller uses an adjustable reference input (REFIN_) to set the nominal output voltage (V OUT ), which minimizes the cost and makes the stability independent of the output voltage. n output UVP timing depends on the magnitude of the voltage at V OUT. The UVP detects and shuts down the LO if the output voltage drops below the nominal output voltage (V REFIN ). Each linear regulator features an adjustable soft-start function, and generates a delayed PGOO signal that signals when the linear regulator is in regulation. The uses an external resistor-divider in series with the current-sense input (S_), providing foldback current-limit protection, and effectively reducing the short-circuit power dissipation. The is available in a thin QFN package to reduce the thermal impedance, and improve the thermal coupling between the controller and the external MOSFETs. REFIN Input The low-cost linear regulator uses an adjustable reference input (REFIN_) to set the nominal output voltage, which minimizes cost and simplifies the stability the stability calculation is independent of V OUT. The output voltage accuracy depends on the accuracy of the source generating the REFIN voltage. Multiple accurate references are typically available elsewhere in the system (such as the switching regulator providing the lowvoltage input supply). If lower output accuracy is acceptable, divide down and filter another regulated output voltage supply. To set output voltage, select R2 = 1kΩ and select R1 using the following formula: V R1= REF 1 R2 V REFIN_ Soft-Start When the LO is activated, the respective RV_ is pulled up from GN with a typical soft-start current of 17µ. The soft-start current limits the output voltage slew rate and also limits the initial current spike through the external n-channel MOSFET. The slew rate is also limited by the compensation capacitance used at the RV_ pin. The maximum drain current during startup is the ratio of OUT to OMP, multiplied by the soft-start current I SOFT of 17µ (typ). Enable and Power Good The has independent enable control inputs (EN1, EN2). rive EN1 high to enable output 1. rive EN2 high to enable output 2. When EN_ is driven low, the corresponding RV_ and PGOO_ pins are pulled to GN, and the output is discharged through a 1Ω switch. There are two independent PGOO_ outputs indicating the supply status. PGOO_ is pulled high 2ms after the controller is enabled (EN_ is pulled high and V exceeds its UVLO threshold), and the output is in regulation. If either output is out of regulation, the respective PGOO_ goes low immediately. The pulls PGOO_ low if the output voltage drops below the lower trip threshold of -12% (typ) or when V is in UVLO or when EN_ is pulled low. Soft-Stop The enables a soft-stop function that discharges the output through an internal 1Ω switch when EN_ is driven low or V is in UVLO. The discharge time of the output depends on the output capacitance, output load, and the exact resistance of the internal discharge switch. To slow down the discharge rate, add resistance in series with the OUT_ pin. 5.V ias Supply (V ) The linear regulator operates with very low input voltages. V IN may be as low as 1.2V, so a secondary supply is required to provide sufficient bias to the gate drivers. Locally decouple the V input with 1µF or greater of ceramic capacitance. urrent Limit The features a current limit that monitors the voltage across the current-sense resistor, which limits V S _ - V OUT _ to 1mV (typ). However, in case of a short-circuit condition, the power dissipation across the external FET will be extremely high. To protect the external FET, the uses an external resistive divider (see Figure 1) to fold back the current limit, reducing the overall power dissipation. The foldback 8

9 IS SUPPLY POWER GOO µF R6 1kΩ PGOO1 V PGOO2 R6 1kΩ POWER GOO 2 N1/N2: Si 4922Y INPUT 1.8V TO (MX) SYS1 * 1µF OUT1 1µF IN1 1µF R S1 2mΩ R4 1Ω R5 34Ω N1 R3 27Ω 2.1µF RV1 S1 RV2 S2 R3 33Ω N2 2.22µF R4 1Ω R5 15Ω IN2 1µF R S2 2mΩ INPUT 1.2 TO 1. SYS2 * 1µF OUT2 22µF 1. 3 (MX) OFF ON OUT1 EN1 OUT2 EN2 ON OFF SYSTEM REF (2.V) R1 33.2kΩ REFIN1 REFIN2 R1 9kΩ SYSTEM REF (2.V) R2 1kΩ GN R2 1kΩ * LOL 1µF ERMI PITOR WILL E SUFFIIENT FOR MOST PPLITIONS. IF THE IS POWERE FROM HIGH-IMPENE SOURE, ITIONL LOW-ESR POLYMER PITORS RE REOMMENE ON THE INPUT. NOTE: THE SYSTEM REFERENE IS TYPILLY GENERTE Y THE STEP-OWN ONVERTER USE TO POWER THE UL LOW-VOLTGE LINER REGULTORS. Figure 1. Typical Operating ircuit with urrent Limit resistor network is calculated using the short-circuit current (I SHORT ), the maximum load current (I MX ), current-sense resistor (R S ), the 1mV (±3mV) currentlimit threshold (V ILIM ), and the external reference input (REFIN_). See Figure 3: 1) Pick the R S requirement for maximum short-circuit current: RS = VILIM / ISHORT 2) Select R1 = 1Ω and select R2 using the following formula: ( V V R R REFIN + ILIM ) 1 2 = IMXRS VILIM UVP Short-ircuit Protection There are two levels of short-circuit UVP available in the controller. When the current-limit protection is not used (S_= V ), the output undervoltage timeout protection is enabled, which protects the regulator against short circuits. Output UVP timing depends on the magnitude of the output voltage drop. To clear the UVP fault latch, toggle the respective EN_ input, or cycle V below its UVLO threshold. 9

10 INPUT 1.V TO 5. IN N1 R3 2 R S OUT 4.7µF/ OUTPUT OUT RV S.4V 1Ω RSON EN IS SUPPLY 1 V ILIM_EN URRENT SENSE OFF ON LOGI SUPPLY EN THERML SHN ONTROL LOK ERROR MPLIFIER REFIN R2 R1 REF POWER GOO R6 PGOO ELY LOGI ILIM_EN 88% Q S R 75µs ELY 8% EN 6% GN THE INLUES TWO LOs S SHOWN OVE. Figure 2. Functional iagram 1

11 RV R3 2 R S IN INPUT OUT V OUT RV R3 2 R S R1 IN INPUT OUT V OUT S S OUT R2 OUT I MX I MX 1mV R S 1mV R S V OUT SIMPLE URRENT-LIMIT PROTETION FOLK URRENT-LIMIT PROTETION V OUT Figure 3. urrent-limit Protection Slow UVP If the output drops below 8% of the nominal output voltage (V REFIN ) for 75µs, the shuts down the LO and pulls the RV_ pin to ground. If the output voltage returns above 8% of the nominal output voltage (V REFIN ) within the 75µs, the controller ignores the load transient. Fast UVP If the output voltage drops below 6% of the nominal output voltage (V REFIN ) for approximately 5µs, the immediately shuts down and pulls the RV_ pin to ground. If the output voltage returns above 8% of the nominal output voltage (V REFIN ) within the 5µs, the controller ignores the load transient. Thermal Protection The is available in a thin QFN package to reduce the thermal impedance, and improve the thermal coupling between the controller and the external MOSFETs. When the controller s junction temperature exceeds T J = +125 (max), a thermal sensor turns off the external pass transistor, allowing the system to cool. The thermal sensor turns the pass transistor back on once the controller s junction temperature drops by approximately 2. esign Procedure Input apacitor Selection ( IN ) Typically, the is powered from the output of a step-down regulator, effectively providing a low-impedance source. local 1µF ceramic capacitor at V IN and a 1.µF ceramic capacitor at V IS should be sufficient for most applications. If the linear regulator is connected to a high-impedance input, low-esr polymer capacitors are recommended on the input. Output apacitor Selection ( OUT ) To maintain stability and provide good transient response, the requires 4.7µF/ (4.7µF minimum) of low ESR ceramic capacitor at the output. The regulator remains stable with capacitances higher than the minimum. When selecting the output capacitor to 11

12 provide good transient response, the capacitor s ESR should be minimized: V OUT = I OUT x ESR where I OUT is the maximum peak-to-peak load current step, and V OUT is the transient output-voltage tolerance. Regulator ompensation The compensation network (R3_, 2_) is customizable and depends on load and MOSFET characteristics: Use of ceramic output capacitors with low R ESR to ensure stability and minimize ESR voltage drop at load step Strength of the external n-channel MOSFET (g M ), its forward transconductance (g FS ), and the gate-tosource capacitance ( GS ) The driver transconductance (G MRV ) of the integrated circuit driver Load current range (including the minimum load): I MIN to I MX Recommended Procedure Use the GS,g FS, I from the chosen transistor data sheet and use the equation below to translate the measured g FS to g M for normal operation: 1) etermine the LO transconductance using the MOSFET s forward transconductance (g FS ), and the drain current (I ) used to test the selected MOSFET: 2) alculate the compensation resistor based on the output capacitor ( OUT ), the MOSFET s gate-tosource capacitance ( GS = ISS - RSS ), and the minimum driver transconductance: R3 = I gm = gfs MX I OUT GSgM x 5. S Example: The example below is used to demonstrate the stability calculation for the application circuit in Figure 1. 1) hoose V OUT = 1. and I MX = 3 and the minimum load can be determined from the foldback current-limit resistance: 2) For the selected MOSFET (Si4922Y), GS = 2pF at 1., and g FS = 3S at I = 8.8: 3) The output capacitor must be at least 4.7µF/. Therefore the design must use a minimum 14.1µF capacitor. The closest standard capacitor value is 22µF. 4) ased on the above operating conditions and component selection, the compensation resistor value should be: R3 = V IMIN = OUT m R1+ R2 6 gm = 3 3 S S 88 = µ F = 35Ω 2nF 17. 5S. 5S 5) Finally, select the compensation capacitor value: 2 25mV 22µ F 2 = 2 6m 1S ( 35Ω) = 15. µ F External MOSFET Selection The uses an n-channel MOSFET as the series pass transistor instead of a p-channel MOSFET to reduce cost. The selected MOSFET must have a gate threshold voltage (at the required max load) that meets the following criteria: 3) alculate the compensation capacitance using the minimum load current (I MIN ) and compensation resistor value calculated above: where V T = 25mV. 2V 2 = T OUT IMINGMRV( R3) 2 VGS_ MX V VOUT where V is the controller bias voltage, and V GS_MX is the maximum gate voltage required to yield the onresistance (R S_ON ) specified by the manufacturer s data sheet. Make sure that input-to-output voltage meets the condition below to avoid entering dropout, where output voltage starts to decrease and any ripple on the input also passes through to the output. R SON has a positive temperature coefficient (approximately 12

13 .5%/ ); therefore, the value of R SON at the highest operating junction temperature should be used: VIN_ MIN VOUT_ MX IMX( RSON_ MX + RS) where V IN_MIN is the minimum input voltage at the drain of the MOSFET. MOSFET Power issipation The maximum power dissipation of the depends on the thermal resistance of the external n- channel MOSFET package, the board layout, the temperature difference between the die and ambient air, and the rate of airflow. The power dissipated in the MOSFET is: P IS = I OUT (V IN - V SP ) The maximum allowable power dissipation is determined by the following formula: TJ( MX) T RIS( MX) = θj + θ where T J(MX) is the maximum junction temperature (+15 ), T is the ambient temperature, θ J is the thermal resistance from the die junction to the package case, and θ is the thermal resistance from the case through the P board, copper traces, and other materials to the surrounding air. Standard 8-pin SO MOSFETs are typically rated for 2W, while new power packages (PowerPK, irectfet, etc.) can achieve power dissipation ratings as high as 5W. For optimum power dissipation, use a large ground plane with good thermal contact to ground and use wide input and output traces. Extra copper on the P board increases thermal mass and reduces the thermal resistance of the board. See Figure 4. P oard Layout Guidelines ue to the high-current paths and tight output accuracy required by most applications, careful P board layout is required. n evaluation kit (EVKIT) is available to speed design. It is important to keep all traces as short as possible to minimize the highcurrent trace dimensions to reduce the effect of undesirable parasitic inductance. The MOSFET dissipates a fair amount of heat due to the high currents involved, especially during large input-to-output voltage differences. To dissipate the heat generated by the MOSFET, make power traces very wide with a large amount of copper area. n efficient way to achieve good power dissipation on a surface-mount package is to lay out copper areas directly under the MOSFET package on multiple layers and connect the areas through vias. Use a ground plane to minimize impedance and inductance. In addition to the usual high-power considerations, here are four tips to ensure high output accuracy: Ensure that the feedback connection to OUT is short and direct. Place the reference input resistors next to the REFIN_ pin. Place R and next to the RV_ pin. Ensure REFIN_ and RV_ traces are away from noisy sources to ensure tight accuracy. PowerPK is a registered trademark of Vishay Siliconix. irectfet is a trademark of International Rectifier orp. 13

14 IS SUPPLY POWER GOO µF R6 1kΩ S1 PGOO1 V S2 PGOO2 R6 1kΩ N1/N2: Si 4922Y * LOL 1µF ERMI PITOR IS SUFFIIENT FOR MOST PPLITIONS. IF THE IS POWERE FROM HIGH-IMPENE SOURE, ITIONL LOW-ESR POLYMER PITORS RE REOMMENE ON THE INPUT. POWER GOO 2 INPUT 1.8V TO 2. SYS1 * 1µF IN1 1µF N1 RV1 RV2 N2 IN2 1µF INPUT 1.2 TO 1. SYS2 * 1µF 1. 2 (MX) OUT1 1µF R3 27Ω 2.1µF R3 33Ω 2.22µF OUT2 22µF 1. 3 (MX) OUT1 OUT2 OFF ON R7 47.5kΩ EN1 EN2 ON OFF SYSTEM REF (2.V) REFIN1 R8 42.2kΩ GN REFIN2 R9 1kΩ NOTE: THE SYSTEM REFERENE IS TYPILLY GENERTE Y THE STEP-OWN ONVERTER USE TO POWER THE UL LOW-VOLTGE LINER REGULTORS. Figure 4. Typical Operating ircuit with Output Undervoltage Protection hip Information TRNSISTOR OUNT: 1562 PROESS: imos 14

15 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 24L QFN THIN.EPS PKGE OUTLINE, 12, 16, 2, 24, 28L THIN QFN, 4x4x.8mm PKGE OUTLINE, 12, 16, 2, 24, 28L THIN QFN, 4x4x.8mm Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel rive, Sunnyvale, Maxim Integrated Products Printed US is a registered trademark of Maxim Integrated Products, Inc.