Part I: Degradation in 3.2 nm Gate Oxides: Effects on Inverter Performance and MOSFET Characteristics. Oxide Degradation

Transcription

1 Part I: Degradation in 3.2 nm Gate Oxides: Effects on Inverter Performance and MOSFET Characteristics Part II: Noise in Circuits Effects on Ultra-Thin Gate Oxide Degradation Bill Knowlton and Jake Baker Department of Electrical and Computer Engineering, Boise State University, Boise, ID 1

2 2 Acknowledgments University and Industry Involvement Betsy Cheek (G), ECE Nate Stutzke (UG), ECE Santosh Kumar, Cypress Semiconductor Amy Moll, ME Faculty Dr. Amr Haggag, Motorola Carrie Lawrence (G), ECE University and Industry Involvement Michael Ogas (UG), ECE Tim Lawrence (G), ECE Richard G. Southwick III (UG), ECE Kloy Debban (G), ECE Terry Lowman (UG), ECE Miles Wiscombe (UG), ECE Funding 21 DOD Multidisciplinary Research Initiative (MURI) NSF-Idaho EPSCoR Program Cypress Semiconductor NSF Major Research Instrumentation Grant DARPA Grant Governor s Higher Education Initiative - Idaho State Board of Education 23 Micron Campus Engineering Research Program

3 Part I: Degradation in 3.2 nm Gate Oxides: Effects on Inverter Performance and MOSFET Characteristics Bill Knowlton and Jake Baker Department of Electrical and Computer Engineering, Boise State University, Boise, ID 3

4 4 Outline Motivation and Statement of work Introduction & Background Experimental Circuit Stress Induced Dielectric Breakdown Circuit Implications Circuit Model Summary and Conclusion

5 Reliability of Ultrathin Gate Oxides in MOS Devices Motivation: As gate oxides become thinner, new degradation modes appear and may cause reliability issues. Worldwide semiconductor market is over $2 billion/year. Cost of reliability & functionality assurance is estimated >$25 billion/year. Green et al., J. Appl. Phys., 9 (21) 257 5

6 6 Background: Reliability of Ultrathin Gate Oxides in MOS Devices Question: As a device is used, what occurs to the oxide over time? Answer: It wears out. Known as wearout. Occurs prior to dielectric breakdown. Causes oxide degradation increased gate oxide leakage current Defects or traps are generated inside & at interfaces of Si/SiO 2 Trap generation caused by: Electric fields applied across the oxide Tunneling current through the oxide Dielectric breakdown eventually occurs

7 Background: Reliability of Ultrathin Gate Oxides in MOS Devices E e- Fowler-Nordheim Tunneling MOSCAP Band Diagram Direct Tunneling E f,s E f,s E f,m Al SiO 2 (9eV) p-type Si E f,m Al SiO 2 p-type Si Triangular barrier Modified Carrier Affinity e - : ~ 3.1 ev h + : ~ 4.9 ev Trapezoidal barrier Band diagrams not to scale 7

8 Background: Reliability Test Methods Oxide Reliability: Study Wearout Degradation Mechanisms in Ultrathin Oxides Induce wearout prematurely Use Stress Testing: Constant Voltage Stress (CVS): typically used Constant Current Stress (CCS) Pulsed Voltage Stress (PVS) Ramped Voltage Stress (RVS) I G New/Fresh device Pre-stress (sense) V G Stress Test: CVS CCS PVS* RVS I G stressed device POST-stress (sense) V G *Lawrence, C.E., B.J. Cheek, T.E. Lawrence, Santosh Kumar, A. Haggag, R.J. Baker, and W.B. Knowlton, Gate Dielectric Degradation Effects on nmos Devices Using a Noise Model Approach, in Proceedings of the 15th Biennial IEEE UGIM Symposium (23), pp

9 I G -V G Sense Results: Degradation Mechanisms I GATE (A) PVS t ox = 3.2 nm A ox = 2.1x1-4 cm V GATE (V) softer SBD? SILC HBD LHBD SBD fresh JGATE (A/cm2 ) Knowlton, W.B., T. Caldwell, J.J. Gomez, and S. Kumar. On the nature of ultrathin gate oxide degradation during pulse stressing of nmoscaps in accumulation. in IEEE International Integrated Reliability Workshop, (21) pp

10 Metrics Technology Interactive Characterization Software (Controls 4156C system) Agilent 4156C Precision Semiconductor Parameter Analyzer Agilent 1644A SMU/Pulse Generator Selector Agilent E525A Low Leakage Switch Matrix 8 Cascade Mirotech DCM-Series MicroManipulators and Micromanipulator Probe station & Camera Materials Characterization & Device & IC Reliability Lab W. Knowlton & A. Moll, Boise State University Betsy Cheek, Grad Student Electrical Engineering 1

11 11 Materials Characterization & Device & IC Reliability Lab W. Knowlton & A. Moll, Boise State University Agilent 8111A Pulse/Pattern Generator Unit (2 channels) Keithley 595 Quasistatic CV Meter Keithley 42 Semiconductor Characterization System High Speed Oscilloscope HP 4284A LCR meter 4 Cascade Mirotech DCM-Series MicroManipulators and Wafer Top and Bottom Probestation

12 12 Equipment Capability Femto-Ampere and milli-ohm resolution at room temperature nmosfet 3.2 nm Gate Oxide Tunneling Current I GATE (A) 2.x x x x x x x x1-14 Knowlton's Group Boise State University RGS [L22U MOD21 & 2 W5SD RAM7 17 Sept 23] t ox = 3.2 nm A ox = 6.25x1-6 cm 2 Room Temp V GATE (V) nmos Agilent 4156C 3.x x1-9 2.x x1-9 1.x1-9 5.x x x x x x x1-9 J GATE (A/cm 2 )

13 Equipment Capability Probes: Top and bottom of wafers < 5 um contacts IV Meter Through-wafer Cu vias: 5um dia. & 5 um length 13

14 Motivation Oxide Reliability MOS Devices Integrated Circuit Reliability Extensive studies on MOSCAPs and some on MOSFETs Gate oxide breakdown related circuit reliability? Minimal work reported 1-3 Consequences are uncertain 1,2 Future scaling of high-performance CMOS ICs 4,5 Word lines in a DRAM cell are pumped to a voltage above V 6 DD Increased stress? Breakdown mechanisms? 1 J. H. Stathis et al, WoDim, R. Rodriguez et al, Transactions on Device Letters, pp , B. Kaczer et al, Transactions on Electron Devices, pp. 5-56, H. Iwai et al, IEDM., pp , J. H. Stathis et al, IEDM, pp , B. Keeth et al, IEEE Press, pp. 1-33,21. 14

15 15 Statement of Work Gate Oxide degradation in CMOS Inverters Stress at Circuit Level V DD V IN V OUT What happens to circuit operation? What happens to MOSFET characteristics? SPICE circuit model Physical description

16 Experimental Inverter parameters defined pmos on Voltage Output High (V OH ) Sample voltage transfer characteristics (VTC) V OUT (V) increased pmosfet V th,p Voltage Switching Point ( V SP ) increased nmosfet V th,n 1.8 pmos on Input Voltage (V IN ) Output Voltage (V OUT ).3 Fresh Voltage Output Low ( V OL ) V IN (V) Sample voltage-time (V-t) domain nmos on Voltage (V) t f II Falling signal V OUT Min Time (µs) nmos on t r V OUT Max I Rising signal 16

17 17 Experimental MOSFET Schematics Devices fabricated in a.16-µm CMOS technology t ox : 3.2 nm A ox : 6.25 x 1-6 cm 2 W P /L P : 25 µm /25 µm W N /L N : 25 µm /25 µm pmosfet G S B Inverter Circuit Schematic Nominal operating voltage V DD : 1.8 V Voltage transfer characteristics (VTC) V IN : to 1.8 V sweep Voltage-time domain response (V-t) V IN : 1.8 V Frequency: 2.5 khz Duty cycle: 5 % V DD D D nmosfet G B V IN V OUT S

18 18 Experimental Setup Inverter configuration Off-wafer via switch matrix Stressing and characterization at transistor and circuit level V OUT V V DD V IN Stress Configuration Stress applied from input to output Stress test Ramped Voltage Stress (RVS) Test conditions Positive and negative stress V IN : 8 V, 1 V, 12 V, 14 V V OUT : V V DD and GND nodes floating 1 V DD V IN -+ V OUT GND 1 J. H. Stathis et al, WoDim, 22.

19 19 Experimental Procedure Pre-Stress Response Post-Stress Response Measure MOSFET: I G -V G I D -V D, I D -V G Induce Stress Configure Inverter Measure: VTC, V-t Both MOSFETs Simultaneously n Disconnect Circuit /Isolate MOSFET Both MOSFETs Individually y End Test n Stress Testing? y n 1 MOSFET Individually y

20 I g Circuit Stress Induced Breakdown - MOSFETs MOSFET gate leakage currents (LHBD = limited hard breakdown 1, 2, 3 ) 1-3 Positive Voltage Stress nmosfet Negative Voltage Stress nmosfet HBD I G (A) ACC INV LHBD Fresh JG (A/cm 2 ) I G (A) ACC INV LHBD Fresh JG (A/cm2 ) V G (V) V G (V) I G (A) INV pmosfet V G (V) 1 B. P. Linder et al, VLSI Technology Digest of Technical Papers, pp , 2. ACC Fresh HBD LHBD SILC JG (A/cm 2 ) I G (A) Fresh 8 V 1 V 12 V 14 V pmosfet W. B. Knowlton et al, Proc. of the IRW, pp , B. Cheek et al, Workshop on Microelectronics and Electronic Devices, Boise, 22. INV ACC V G (V) HBD LHBD? Fresh J G (A/cm2 ) V g 2

21 21 Circuit Stress Induced Breakdown - MOSFETs MOSFET log I D -V G Characteristics nmosfet pmosfet Fresh V Stress = -8 V V Stress = +8 V V D = 1.8 V I On Fresh V Stress = -8 V V Stress = +8 V V D = -1.8 V I D (A) I Off I On = 38 µa, -V I = On 37 µa, +V I Off = 1.9 pa, -V =.2 pa, +V V G (V) I D (A) I Off I On I On = 8.8 µa, -V = 5.6 µa, +V I Off = 1.1 pa, -V = 2.2 pa, +V V G (V)

22 22 Circuit Stress Induced Breakdown - MOSFETs nmosfet I D -V D Characteristics: Positive stress voltage Negative stress voltage 1.x1-4 1.x1-4 8.x1-5 6.x1-5 A1 A2 8.x1-5 6.x1-5 I D (A) 4.x1-5 2.x1-5 Inc. (+) Stress I D (A) 4.x1-5 2.x1-5 A1 Inc. (-) Stress A2-2.x x1-5 Inc. (+) Stress V D (V) V G = 1.8 V -2.x1-5 Inc. (-) V Stress G = 1.8 V -4.x V D (V) Fresh 8 V 1 V 12 V 14 V

23 23 Circuit Stress Induced Breakdown - Inverter Inverter voltage transfer characteristics (VTC) Positive Voltage Stress Negative Voltage Stress V OH 1.8 V OH 1.8 V OUT (V) Fresh +8 V +1 V +12 V +14 V V SP Inc. (+) Stress V OUT (V) Fresh Inc. (-) Stress.3 Fresh V IN (V) V OL V IN (V) V OL Fresh 8 V 1 V 12 V 14 V

24 VTC Comparison of Only Other Publication Inverter voltage transfer characteristics (VTC) What about time domain? Individual MOSFETS? 1 J.H. Stathis, R. Rodriguez, B.P. Linder, Circuit Implications of Gate Oxide Breakdown, Proceedings WoDIM,,

25 25 Circuit Stress Induced Breakdown - Inverter Inverter voltage-time domain (V-t) response Positive Voltage Stress Negative Voltage Stress II I 1.5 II I Voltage (V) Inc. (+) Stress Inc. (+) Stress Time (µs) Voltage (V) Inc. (-) Stress Inc (-) Stress Time (µs) Fresh 8 V 1 V 12 V 14 V

26 Circuit Implications Problem Consequence Increased off-state leakage current Increased gate leakage current Increased power consumption 1 Circuit failure (>1 billion transistors on a chip) Loading of circuit stages 1 Increased rise/fall/delay times Timing issues in high-speed circuits 1 1 R. J. Baker, H. W. Li, and D. E. Boyce, "CMOS: Circuit design, layout, and simulation," IEEE Press,

27 Circuit Model V DD Circuit elements Resistor-diode pairs Connected from gate-drain Resistors Connected from gate-source V IN V OUT Diode emission equation 2 I D = I S [exp( V D / N Vt ) 1] I S (saturation current), V D (diode voltage), N (emission coefficient), V T (thermal voltage) MOSFET threshold voltage (V th ) 1 T.-S. Yeoh et al, ICSE, Bangi, Malaysia, R. J. Baker, H. W. Li, and D. E. Boyce, "CMOS: Circuit design, layout, and simulation," IEEE Press,

28 28 Data Vs Model Inverter voltage transfer characteristics (VTC) V OUT (V) V OH Positive Voltage Stress Line = Data Symbol = Model V SP Fresh V IN (V) Inc. (+) Stress V OL V OH V OUT (V) Negative Voltage Stress Line = Data Symbol = Model V SP Fresh Inc. (-) Stress V IN (V) V OL Fresh 8 V 1 V 12 V 14 V

29 Circuit level stress Conclusion Determine degradation in individual devices Ability to connect device degradation to circuit degradation VTC measurements may show negligible inverter degradation Suggests Oxide degradation effects in Inverters are not a reliability issue Time-domain behavior may be severely degraded! Suggests Oxide degradation effects in Inverters are a reliability issue V-t data introduces another characteristic for digital circuit reliability Need for more suitable reliability criterion 1-3 Study suggests that the time domain is the more suitable criteria 1 J. H. Stathis et al, WoDim, J. H. Stathis et al, IEDM, pp , B. Kaczer et al, IEEE Transactions on Electron Devices, vol. 49, pp. 5-56,

30 Future Publications and Work Betsy J. Cheek, Nate Stutzke, Miles Wiscombe, Terry Lowman, Santosh Kumar, R. Jacob Baker, Amy J. Moll and William B. Knowlton Effects of Circuit-Level Stress on Inverter Performance and MOSFET Characteristics oral presentation at the 23 IEEE International Integrated Reliability Workshop, Oct, 2-23, 23. Betsy J. Cheek, Student Member, IEEE, Nate Stutzke, Student Member, Santosh Kumar, Member, IEEE, R. Jacob Baker, Senior Member, IEEE, Amy J.Moll, William B. Knowlton, Member, IEEE Investigation of Gate Oxide Reliability: Consequences of Dielectric Breakdown on MOSFET Characteristics and CMOS Inverter Performance submitted September 23 IEEE Transactions on Electron Devices in review. Other SICBBs: T-gates, current mirrors, etc. Thinner gate dielectrics: 2.1 nm & thinner, high-k (Cypress & Semitech) Determine Trap identity WRT Oxide Degradation Mechanism Penn State Interconnect coupling/crosstalk effects on oxides 3

31 Part II: Noise in Circuits Effects on Ultra-Thin Gate Oxide Degradation Bill Knowlton and Jake Baker Department of Electrical and Computer Engineering, Boise State University, Boise, ID 31

32 Project Definition and Motivation Investigate the effects of noise in circuits using MWPVS Model noise as a voltage spike constructively interfering with a carrier signal due to superposition of waves V V gate spike + = t Noise on signal lines due to: Electromagnetic radiation (space applications) Very close interconnect proximity Capacitive coupling Baker et. al., CMOS: Circuit Design, Layout, and Simulation (Wiley, 1998). 32

33 33 Reliability Test Methods CVS (constant voltage stress) NOT typical for digital circuit operation Voltage PVS (pulse voltage stress) Better mimics digital device behavior Voltage Time Time MWPVS Represents circuit operation with noise Voltage Time

34 34 Experimental Setup Continued Combined signals from two Waveform Generators (WFG) programmed with: Frequency 5 khz Voltage Amplitude Carrier Signal: -5 V Noise Signal: V -1 V, -3 V, -5 V Duty Cycle Carrier Signal: 75 % Noise Signal: 5 % & 25 % Voltage (V) Noise Signal Carrier Signal Time (s)

35 35 I G -V G Sense Results J GATE (A/cm 2 ) LHBD SILC Fresh 4 t ox = 3.2 nm A ox = 2.1x1-4 cm MWPVS: (carrier & noise) -2 V ~.1 A V GATE (V) khz(-5 V & V) 3 5 khz(-5 V & -3 V) 2 5 khz(-5 V & -1 V) 4 5 khz(-5 V & -5 V) IGATE (A)

36 36 MWPVS Weibull Distribution ln[-ln(1-f)] β 1 β β time-to-breakdown (s) MWPVS: 5 khz Carrier signal: 5 V Noise signal: 1 V (baseline) D. C. 5 %: V 3 V 5 V D. C. 25 %: CVS: β 1 V 3 V 5 V 5 V

37 Preliminary Noise Model for MWPVS Initial data indicates that increasing the noise signal decreases device lifetime exponentially t d, constant proportional to DC BASE of carrier signal d, constant proportional to DC SPIKE of noise signal c, voltage accelerator factor dv, noise amplitude 1 bd,2 d e c V + d' e c ( V + dv ) t bd, 75% / t bd, 75% Preliminary noise model for a spike voltage with a DC SPIKE of 2% Noise Voltage (V) Lawrence, C.E., et al, Gate Dielectric Degradation Effects on nmos Devices Using a Noise Model Approach, in Proc. of the 15th Biennial IEEE UGIM Symposium, June 3 - July 2, 23, pp

38 Experimental Setup for MWPVS Carrier signal parameters: 2 khz and 1 khz frequency (F) 75% duty cycle (DC BASE ) -5 V base amplitude (V BASE ) Noise signal parameters: Voltage (V) % D.C. Pulse Setup 75% D.C. Carrier Signal Noise Spike -1.µ -5.µ 5.µ 1.µ Time (s) Stress effects: Monitored through gate leakage current (I GATE -V GATE ) End test when leakage current reaches 1 ma (Limited Hard Breakdown) 1-2 Devices: nmoscaps t ox = 3.2nm A ox = 2.1x1-4 cm 2 1 B. P. Linder et al, VLSI Technology Digest of Technical Papers, pp , 2. 2 W. B. Knowlton et al, Proc. of the IRW, pp ,

39 39 Experimental Results Pre- and post- MWPVS I GATE- V GATE results: Degradation mechanisms observed Example of nmoscap degradation at V BASE = - 5 V, V SPIKE = -1 V, F = 2 khz, DC BASE = 75%, DC SPIKE = 25%. SILC (Stress Induced Leakage Current) 3-4 SBD and Softer SBD (Soft Breakdown) 5 LHBD (Limited Hard Breakdown) 2 3 T. N. Nguyen et al, "A new failure mode of very thin (<5Å) thermal SiO2 films," presented at 25th Annual International Reliability Physics Symposium, San Diego, P. Olivo, et al, "High-field-induced degradation in ultra-thin SiO2 films," IEEE Transaction on Electron Devices, vol. 35, pp , S.-H. Lee, et al, Choi, "Quasi-breakdown of ultrathin gate oxide under high field stress," presented at IEDM Techn. Digest, 1994

40 4 MWPVS Vs. CVS Weibull plots indicate device lifetime decreases by orders of magnitudes when compared to preliminary CVS data 1.5 Cumulative Distribution or Failure Function, F: F = (n f -.3)/(n+.4) (median ranks) 1.5 Cumulative Distribution or Failure Function, F: F = (n f -.3)/(n+.4) (median ranks) 1. MWPVS: 2 khz 1. MWPVS: 1 khz.5 β V GATE : -5V β CVS.5 β V GATE : -5V β CVS ln[-ln(1-f)] β β DC SPIKE : 25% (base, spike) (-5V & -1V) (-5V & -3V) (-5V & -5V) ln[-ln(1-f)] β β DC SPIKE : 25% (base, spike) (-5V & -1V) (-5V & -3V) (-5V & -5V) t bd (s) t bd (s)

41 41 Conclusions Designed a MWPVS technique to simulate noise Reliability Issues Constructive Interference occurs due Superposition of waveforms o Electromagnetic radiation o Capacitive Coupling o Mixed Signals Device lifetime shorter for MWPVS than PVS Data corresponds to the noise model: : Device lifetime exponentially decreases with increase in noise voltage

42 42 Future Work Further testing of 2 khz and 1 khz with PVS method Further testing of 2 khz and 1 khz with spike duty cycle of 5% with MWPVS method Lower Stress Voltage to replicate lower voltages being used in circuits Breakdown mechanisms as a function of higher frequency noise Accumulation breakdown effects on inversion

43 43 Thank You Questions?

44 Traps The (1) Si/SiO 2 Interface: Two closely related interface state defects P b and P b1 SiO 2 Trapping Centers: Intrinsic oxygen deficient silicon E centers (some coupled to hydrogen) Many extrinsic defects: We know about these centers from electron spin resonance (ESR) studies. Courtesy: Patrick Lenahan, Penn State 44

45 Courtesy: Patrick Lenahan, Penn State 45

46 P b1 Courtesy: Patrick Lenahan, Penn State 46

47 TEOS BPSG Trapping Centers P1 Spin density decreases with hole injection Hole Trap P2 Spin density decreases with hole injection Hole Trap P4 Spin density decreases with electron injection E Spin density generally increases with hole injection; generally decreases with electron injection Neutral Electron Trap Neutral Hole Trap Methanol Radical One of several organic radicals present in these films. Some organic spin densities increase with hole injection other increase with electron injection Electron and Hole Trap Courtesy: Patrick Lenahan, Penn State 47

48 48 Effects of Dielectric Breakdown MOSFET linear I D -V G Characteristics nmosfet pmosfet 1.2x1-5 1.x1-5 8.x1-6 Fresh V Stress = -8 V V Stress = +8 V V D = 5 mv 1.2x1-5 1.x1-5 8.x1-6 4.x1-6 3.x1-6 Fresh V Stress = -8 V V Stress = +8 V V D = -5 mv 3.x x1-6 2.x1-6 g m (S) 6.x1-6 4.x1-6 2.x1-6 6.x1-6 4.x1-6 2.x1-6 ID (A) g m (S) 2.x1-6 1.x x1-6 1.x1-6 5.x1-7 ID (A) V G (V) V G (V)

49 49 Circuit Stress Induced Breakdown - MOSFETs MOSFET I D -V D Characteristics: Negative voltage stress nmosfet pmosfet 1.x x1-5 8.x x1-5 -6x1-6 I D (A) 6.x1-5 4.x1-5 2.x1-5 Inc. (-) Stress I D (A) -1.2x x1-6 A1 A2-4x1-6 -2x1-6 Inc. (-) Stress 2x A1 A2-2.x1-5 Inc. (-) V Stress G = 1.8 V -4.x V D (V) -4.x1-6 V G = -1.8 V V D (V) Fresh 8 V 1 V 12 V 14 V

50 5 Circuit Stress Induced Breakdown - Inverter Inverter input leakage current results (CLHBD = circuit limited hard breakdown) Positive Voltage Stress Negative Voltage Stress I Input (A) CLHBD Fresh JInput (A/cm2 ) I Input (A) CLHBD HBD? Fresh JInput (A/cm2 ) V IN (V) V IN (V) Fresh 8 V 1 V 12 V 14 V

51 51 Equipment Capability Resistance resolution: mω resolution (Cu vias) 4x1-4 3x1-4 2x1-4 Four Point Probe Measurement on Cu TWI Voltage (V) 1x1-4 -1x1-4 -2x1-4 -3x1-4 -4x1-4 Boise State University DARPA Resistance mω mω mω mω mω mω mω mω 3.17 mω mω -9x1-2 -6x1-2 -3x1-2 3x1-2 6x1-2 9x1-2 Current (A)

52 nm Gate Oxides Tunneling current is Direct nmosfet, I G -V G 3.x x x1-12 t ox = 2.1 nm A ox = 6.25 x 1-6 cm 2 Room Temp. 4.5x1-7 4.x x1-7 3.x1-7 I GATE (A) 1.5x x x1-13 Fresh I G -V G 2.5x1-7 2.x x1-7 1.x1-7 5.x1-8 J GATE (A/cm 2 ) -5.x x x x x1-7 Knowlton's Group Boise State University MO [RAM 9 MOD2238 nmosfet ] Accumulation V GATE (V) Inversion

53 53 Summary What type of oxide degradation has been introduced into the gate oxide to cause these types of VTCs? MOSFET LHBD Inverter CLHBD Similar to the MOSFET degradation mechanism LHBD Suggests oxide degradation mechanisms in simple circuits are similar to MOSFETs How do the individual devices respond to this type of degradation? Increased off-state leakage current Increased gate leakage currents Decreased g m, increased V th

54 54 Summary Importantly, how does this affect the time domain? Reduced output swing V OH decreases Positive or negative stress V OL Positive, increases with increasing stress Negative, decreases with increasing stress Increased rise- and fall-times Circuit model Observed both Ohmic and non-ohmic (exponential) behavior in data Physical Explanation Resistor = Ohmic Diode = non-ohmic Result: Both Positive and negative data fit well