A New Control Method for Balancing of DC-Link Voltage and Elimination of Common Mode Voltage in Multi-level Inverters

Transcription

1 A New Control Method for Balancing of DC-Link Voltage and Elimination of Common Mode Voltage in Multi-level Inverters P. Satish Kumar Department of Electrical Engineering University College of Engineering, Osmania University Hyderabad, INDIA Ch. Lokeshwar Reddy Department of Electrical & Electronics Engineering Hyderabad Institute of Technology and Management Hyderabad, INDIA Abstract In this paper a new control method is proposed for balancing the dc-link voltage and common mode voltage elimination in multi-level inverters and implemented for a threelevel neutral point clamped inverter, while providing enhanced ride-through and common-mode voltage (CMV) elimination. This method uses dc-dc converter technology on the dc link for balancing and ride-through enhancement and a modified PWM switching algorithm for common mode voltage elimination. The dwelling time vectors of multi-level inverter are obtained from the dwelling time vectors of two-level inverter by using a linear transformation and a novel classification of voltage vectors is also proposed to determine the switching pattern. This method can be easily extended to five or more level inverters also. The validity of the proposed method has been verified from the simulation results of a three-level inverter. Keywords- Common mode voltage, DC link voltage, NPC multilevel inverter, SVPWM. T I. INTRODUCTION HE multilevel power conversion technology is a very rapidly growing area of power electronics with good potential for further development. The most attractive applications of this technology are in the medium- to highvoltage range (2-13kV), and include motor drives, power distribution, power quality and power conditioning applications. In general, multilevel power converters can be viewed as voltage synthesizers, in which the high output voltage is synthesized from many discrete smaller voltage levels. The most significant advantages of space vector pulse width modulation (SVPWM) technique are fast dynamic response and wide linear range of fundamental voltage compared with the conventional PWM. But as the number of level increasing, the SVPWM is more and more complexity. A. Neutral-Point-Clamped Multilevel Inverter The main circuit of the Neutral Point Clamped three-level Inverter [1] is as shown in Fig. 1 and the relationship between switching states and output voltages in one phase are shown in Table I. The three-level inverter has 3 3 =27 kinds of switching, because each phase can output three kinds of voltage as shown in Table I. The neutral point clamped inverter [2] is capable of reducing the harmonics in the output voltage and current considerably. If the potential of the neutral point is kept at the center potential of the dc link voltage, the applied voltage of each switching device equals half of the dc link voltage. Therefore, the NPC inverter is suitable for high voltage and high power applications. TABLE I. Switching Symbols Figure 1. Schematic diagram of three-level NPC inverter SWITCHING STATES AND VOLTAGES (X = U,V,W) Switching states S 1x S 2x S 3x S 4x Terminal voltages P ON ON OFF OFF V dc/2 O OFF ON ON OFF N OFF OFF ON ON -V dc/2 B. Variation of Neutral Point Potential Neutral point voltage variation is the inherent issue in NPC inverters. The main reason is that there is the necessary split point in the capacitor bank of the dc-bus. This neutral-point is a floating point where the potential will change if there is any NP current. Again, NP voltage variations need to be mitigated because they may cause start-up failure, CMV and overvoltage across the switching devices. The equivalent circuit of the dc bus can be shown as the left circuit model in Fig. 2. If just the NP voltage and neutral current I n are concerned. The right portion of Fig. 2 shows the ac model (or small signal model) of the NP voltage V np versus the neutral current I n. 1

2 Hence, the voltage V np can be express as V np = 1/(C 1 +C 2 ) I n (t) dt =1/(2C) I n (t) dt (1) Where C 1 =C 2 =C Because the I n is the inherent current in the NPC inverter, the NP voltage V np cannot be minimized to zero without some additional compensation currents added to the NP point to cancel the neutral current I n. Hence to reduce NP voltage variation V np, two methods can be applied according to the above equation. One is to reduce the neutral current I n by inducing a compensation current and the second is increase the dc bus capacitance C 1 and C 2, if the maximum I n and the inverter output frequency are determined. that the normalized output voltages and un-normalized currents are sinusoidal as follows: V a = M sin (ωt) (4) V b = M sin (ωt-12 o ) () V c = M sin (ωt+12 o ) (6) i a = I sin (ωt-φ) (7) i b = I sin(ωt-φ-12 o ) (8) i c = I sin(ωt-φ+12 o ) (9) Where, ω is output frequency. I is output load peak current and φ is load phase angle. The modulation index is expressed as M. The total dc-bus voltage is V dc. The NP current can be expressed as I n = i na +i nb +i nc (1) Where i na, i nb and i nc are the phase a, b and c neutral currents, respectively. Figure 2. Equivalent dc bus circuit and voltage (V np) variation The first method is widely investigated in the inverter topologies and arithmetical methods including PWM modification and closed loop control of the NP voltage. For the second, it is fit for the fixed higher output frequency inverter because a reasonable capacitance value can be applied. Note that fundamental frequency of the NP current in equation (1) is three times the inverter frequency. Hence V np =1/ (2C) I n (t) dt =1/(2C) I n_fund sin(3ωt+θ) dt (2) V np =I n / (6Cω) (3) where ω is the fundamental output frequency. From equation (3), the NP voltage will become very large if the inverter runs at very low output frequency. For example, for a 46V NPC inverter with some fixed capacitance, if its normal NP voltage variation is 1V peak-to-peak with output frequency 6Hz, the NP voltage variation will be 1V pp with output frequency 6Hz, ten times as big as before. So for the very low output frequency, a very big capacitor bank must be applied if a small NP voltage is desired. This will increase the inverter size and cost. C. Neutral-Point Current Analysis The neutral point currents can be generated by the unbalanced load. The common-mode voltage caused by varying dc bus voltage or the NPC inverter itself. Even if the load is balanced and the NP potential is not varied, there still are NP-currents. In the following analysis, it is assumed that there is no NP voltage variation and the load is balanced. The schematic of the NP current analysis is shown as Fig. 3. In Fig. 3, the load is balanced. Furthermore, it is assumed Figure 3. The schematic of NP current analysis When any phase output is clamped to the neutral-point, the neutral-point current related to that clamped phase goes into or out of the neutral-point. The main disadvantage is the neutral point (NP) voltage variation problem. It is an inherent problem because the dcbus capacitor bank consists of two series-connected sub capacitor banks as shown in Fig. 1. When the three-phase load is not completely balanced, there will be unequal charging of the dc-bus capacitors that induces an NP voltage variation. The load unbalance and therefore the NP voltage variation can be significant during the startup of the inverter driving the ac motor or when the inverter drives the ac motor at a low speed. In those cases, the lower frequency NP current causes a larger NP voltage variation. The fluctuation of the NP voltage can cause the switching devices to operate unsafely if the unbalance continues to degrade. If this happens during motor startup, the startup may sometimes fail. If this happens in the low speed operation, it can induce more distortion in the output voltage and cause the ac motor to produce torque ripple. Thus, the fluctuation of NP voltage is a very important problem that needs to be solved for NPC inverters. D. Common Mode Voltages and Bearing Currents The conventional inverters and other switching mode 2

3 inverters generate common- mode voltages in the motor windings because of the instantaneous unbalanced inverter outputs and unbalanced impedances of the motor. Due to PWM frequency of common voltages and capacitive coupling into the rotor, this kind of common- mode voltage will be built up as shaft voltages and can cause damaging currents to flow through the motor bearings. Bearing current is the main reason for motor bearings to fail prematurely in high frequency PWM inverter applications. Common-mode voltages (shaft voltages), bearing currents and the causes of motor bearing failures have been widely investigated [-7]. The shaft voltage and bearing current problems have once more taken people s interests because the high frequency switching devices and methods induce common-mode voltage, exert high dv/dt and high voltage to the motor s windings and cause serious problems with shaft voltage and bearing currents. Common-Mode Voltages The common-mode voltage is defined as V com =1/3(V a + V b + V c ) Figure 4. Illustration of common-mode voltage Because of 12 switches in the NPC inverter shown in Figure 4, there are 27 switching states. If the sum of output voltages is not zero, then common-mode voltage results. The NP voltage variations cause the added variations of three-phase output voltage and induce some harmonics in the output. V a1 = V sin(ωt) + V np (11) V b1 = V sin (ωt-12 o ) + V np (12) V c1 = V sin (ωt+12 o ) + V np (13) V com = 1/3(V a1 +V b1 +V c1 ) = V np (14) Finally, the Neutral Point voltage variations generate common-mode voltage at three times the fundamental output frequency, which occurs even if the high frequency and high dv/dt switching common-mode voltage is mitigated by some techniques such as filtering. When the common-mode voltage and resulting shaft voltage caused by the NP voltage variation are large enough to break the oil film insulation in the bearings, bearing currents are generated, which by erosion may cause premature failures of the motor bearings. Hence the NP voltage control is important not only for the NPC inverter operation but also for common-mode voltage mitigation. The shaft voltage is measured between the motor shaft and the motor frame, which is usually grounded. It is generated by the common-mode voltage coupling through the path that consists of the motor stator windings, rotor windings and the distributed capacitance between them. Its magnitude is dependent on not only the magnitudes of the common-mode voltage but also the coupling impedance. Bearing Currents The bearing currents are generated through the path between the inner face of the motor bearing and its outer face by the shaft voltage. Because there is a film of lubricant grease in the bearing, the path from the shaft to the motor frame is insulated by the grease film when the motor is running at a high speed. However, the shaft voltage can be established due to the lubricant grease dielectric ability. Its magnitude may be large enough to break down the grease depending on the drive type, the motor structure and the bearings. It has been observed that even 3V peak shaft voltage may break down the lubricant grease film and cause bearing currents. The bearing currents are generated repeatedly and become the major cause of premature failures of the motor bearings. In order to prevent premature bearing failures, several methods can be used including: mitigating common-mode voltages, short-circuiting the bearing currents and blocking the bearing currents. II. MODULATION SCHEME FOR NP VOLTAGE BALANCING AND COMMON MODE VOLATGE ELIMINATION The commonly used modulation schemes still result in non zero common-mode voltages. In this paper a simple method is proposed for balancing the NP voltage. This method can effectively balance the NP voltage without the limitations of modulation methods and load conditions. It also provides increased ride-through capabilities for the inverter during input voltage sags, and because of the NP balancing, the necessary size of the dc-bus capacitors is reduced. A. Operating Principle of Balancing Circuits The buck converter topology is widely applied in the switching mode power supplies due to its simplicity and high efficiency. It is designed to produce a lower voltage from a higher voltage supply. In the power supplies such as for current generation microprocessors, the developed buck converter topology, multiphase buck converters are successfully used to supply low voltage, high current and fast response performance. The major advantage of the buck converter is its low power losses and good control stability. For high voltage applications, the efficiency of the buck converter can be much higher than that in the low voltage applications, dependant on the voltage & power range and switching frequency. In addition, its control stability is very easy to be achieved. 3

4 Boost converters can produce a higher voltage from a lower voltage source. The main features include topology simplicity, high efficiency and low losses. But the controller for the boost converter needs to be carefully designed to meet the requirement of stability. It is widely used in power factor correction applications. The following discussion is to combine the buck and boost converters into a NP voltage balancing circuit. regulating the voltage of C 1. When V c1 is equal to half of V dc, the variation of the NP voltage is zero. Design of the Parameters of the Circuit Because the maximum NP current is nearly equal to the inverter output current, in the worst case condition, the current rating of the two additional switching devices is the same as the rating of the multilevel inverter switching devices. The voltage rating of the additional switching devices is twice that of the output switching devices. The size of the inductance and capacitance are determined by the voltage ripple requirement across the capacitors. The design process can be referenced to the boost and buck converter design. Figure. Schematic of the Buck converter Figure 7. Schematic of the NP voltage balancing circuit Figure 6. Schematic of the Boost converter B. Theoretical Operation of Buck and Boost Balancing Circuit Neutral Point Voltage Balancing Circuit The NP voltage balancing topology is shown in Fig. 7. The circuit consists of buck and boost converters. In the balancing mode, the buck and boost converters work in complementary periods. In the schematic diagram, V dc is the equivalent dc bus voltage. C 1 and C 2 are the dc-link capacitors. In the left dash line box, U 1, D 1, L 1 and C 2 consist of a buck dc-dc converter. U 2, D 2, L 2 and C 1 work in boost dc-dc converter mode in the right dash line frame. The balancing circuit operation will be described in the following section. From the analysis of the neutral current in the maximum of the neutral current is almost same as the load current at the worst operating condition. The switching device rating, which is the same as the switching devices used in the power end of the NPC inverter, is enough for the practical application. The current flows from C 2, L 2 and U 2 to ground. The energy is stored in L 2 when the switch U 2 is on. When the switch is off, the energy stored in L 2 is transmitted into C 1 through D 2. Thus, during this period, the balancing voltage is controlled by Figure 8. Schematic of NP voltage balancing circuit with reduced devices From Fig. 7, a reduced-device balancing circuit is obtained as shown in Fig. 8, when an additional ride-through performance is not an issue. In Fig. 8, D 1, D 2 and L 2 are eliminated. The feedback diodes of U 1 and U 2 operate as D 2 and D 1 in Fig. 7 respectively. The performance and operation of the circuit shown in Fig. 8 is the same as in Fig. 6. Thus, a simpler balancing circuit can be applied to the neutral point voltage control, however, without increased ride-through capabilities. Neutral Point Voltage and Ride-Through Control 4

5 A modified NP voltage balancing circuit with ride-through capabilities is shown in Fig. 9, through the addition of switching device U 3. When there is no voltage sag, the switch U 3 is on, and modified circuit works as described in Fig. 6. When a voltage sag occurs on the supply input that causes V dc to decrease below the under voltage protection/trip setting, if no additional ride-through operation mode is available, the Multilevel Inverter will trip offline. For applying the technology of SVPWM, firstly it is requested to determine the sector which the voltage vector is within. Considering that the expression of vector in the α-β coordinate is suitable for controlling implementation, the following procedure is used for determining the sector. When V β >, A = 1; when 3V α V β >, B=1; when 3V α +V β <, C = 1. Then, the sector containing the voltage vector can be decided according to N = A+2B+4C, listed in Table II and Fig. 1 shows the corresponding model. TABLE II. THE SECTOR CONTAINING THE VOLTAGE VECTOR VERSUS N Sector I II III IV V VI N Figure 9. Modified schematic of the NP voltage balancing circuit with ridethrough capabilities However, with the auxiliary ride-through circuit shown in Fig. 9, the switch U 3 will turn off and the circuit will operate in the ride-through mode as follows: The boost and buck converters work together to balance the NP voltage and maintain the dc-link voltage. The buck converter regulates the voltage of the capacitor C 2. The current from V dc flows through U 1, L 1 and C 2 when switch U 1 is on. The energy is stored in L 1 and C 1. When the switch U 1 is off, the energy in L 1 is transferred to C 2. Meanwhile, the boost converter boosts the energy from the capacitor C 2 to C 1 and regulates the voltage of C 1. Note that the rating of the switching devices used during ride through operation will be dependent on the desired ride-through performance. Furthermore, the size of the inductor L 1 and the capacitor C 2 are determined by the voltage and current ripple, since the power is supplied through the lower capacitor C 2. Thus L 1 and C 2 are different from L 2 and C 1 in order to maintain the same voltage ripple of V c2 and V c1. III. COMMON MODE VOLTAGE ELIMINATION The CMV in three-level NPC inverters can be eliminated by modifying the MLI switching algorithm in such a way that the states producing CMV are not used [9]. It was proved by simulation.that work by adding the additional features of dclink balancing and ride- through enhancement. A. Generation of Space Vector PWM Pulses for Three Level Inverter Based on the principle of space vector PWM, the simulation models for generating space vector PWM waveforms mainly include the sector judgment model, calculation model of operation, time of fundamental vectors, calculation model of switching time, and generation model of space vector PWM waveforms. Sector Judgment ii. Calculation of Operation s of Fundamental Vectors Table II lists the operation times of fundamental vectors against N, where T 1 and T m refer to the operation times of two adjacent non-zero voltage space vectors in the same zone. Table III the operation times of fundamental vectors, where Z=T( 3V α +V β )/(2V dc ),Y=T(3V α +V β )/(2V dc ), X=2T(V β /(2V dc )]. The sum of T 1 and T m must be smaller than or equal to T (PWM modulation period). The over saturation state must be judged: if T 1 +T m >T, take T 1 = T 1 [T/(T 1 +T m )], T m =T m [T/(T 1 +T m )]. TABLE III. THE OPERATION TIMES OF FUNDAMENTAL VECTORS AGAINST N, WHERE T 1 AND T M Operation time of fundamental vector N T 1 Z Y -Z -X X -Y T m Y -X X Z -Y -Z iii. Generation of Space Vector PWM Waveform The relation between N and switch operation times is shown in Table II. Where T a = (T T 1 T m )/4, T b =T a +T 1 /2 and T c =T b +T m /2, T cm1, T cm2 and T cm3 are the operation times of the three phases respectively. TABLE IV. RELATION BETWEEN N, T CM, T A, T B AND T C T cm1 T b T a T a T c T c T b T cm2 T a T c T b T b T a T c T cm3 T c T b T c T a T b T a Calculation Model of Switch Operation By comparing the computed T cm1, T cm2 and T cm3 with the equilateral triangle diagram, a symmetrical space vector PWM waveform can be generated. The waveforms of PWM2, PWM4 and PWM6 are obtained by reversing those of PWM1, PWM3 and PWM, respectively. The PMSM is controlled by switching on or off the power electronic parts. A simple method for balancing the NP voltage is proposed, that allows enhanced ride-through performance and enables the SVPWM algorithm to be modified to eliminate the CMV. This method can effectively balance the NP voltage without the limitations of modulation methods and load conditions. It also

6 cmv under conventional svpwm I(phase) I(phase) Inp Vdc voltage across capcitor1 I(L1)-I(L2) Vc1 withnpcontrol provides increased ride-through capabilities for the inverter during input voltage sags, and because of the NP balancing, the necessary size of the dc-bus capacitors is reduced. B. Proposed Algorithm Step 1: Sector identification. Step 2: Calculation of operation times of fundamental vectors using Table III. Step 3: Translation of the active vector switching time periods T1 and Tm into the inverter leg switching timings. Step 4: Generation of the gating signals for the individual power devices using the inverter leg switching timings T com1, T com2 and T com3. IV. SIMULATION RESULTS A. Output Waveforms of an Multilevel Inverter without Neutral Point Voltage Control B. Output Waveforms of an Multilevel Inverter with Neutral Point Voltage Control by Using Buck Boost Converter (a) Capacitor voltage (V C1) (b) Inductor current [I L1-I L2] Figure 12. Wave forms with neutral point voltage control using buck-boost converter (msec) (a) Capacitor voltage (V C1) (b) Neutral point current (I NP) I(load) (sec) (a) Total dc voltage (V dc) during 4% of sag (c) Load current (I phase1) Figure 1. Voltage and current wave forms without NP voltage control (b) Differential voltage of the capacitors (V C2-V C1) time Figure 11. Common mode vector under conventional SVPWM (c) Load current (I phase1) 6

7 Vdc torque (N.m) Vc1 rotor speed(rpm) common mode voltage rotor current(a) I(phase) CMV with CMV cancellation SVPWM I(phase) Vc1-Vc2 I(L1) (d) Controller inductor current (I L1) Figure 13. Wave forms with NP control in ride-through mode C. Output waveforms of an multilevel inverter with neutral point voltage providing ride through enhancement x 1-3 (b) Differential voltage of two capacitors (V c1-v c2) (a) Common mode voltage (c) Load current (I ph1) Figure 16. Wave forms with NP control and CMV cancellation during ride through ir (A) (b) Load current (I ph1) Figure 14. Waveforms with CMV-cancellation SPVWM is (A) (a) Common mode voltage (a) Rotor current (i r) and stator current (i s) (b) Capacitor voltage (V c1) Figure 1. Waveforms for the proposed NP balancing scheme with CMV cancellation (b) Speed <Electromagnetic torque Te (N*m)> (sec) (a) Total dc link voltage (V dc) (c) Torque Figure 17. Wave forms of induction motor 7

8 Fig. 17 shows the induction motor performance after the elimination of common mode voltage in the multilevel inverter. V. CONCLUSIONS A simple approach to balancing the dc-link voltage has been presented, which provides enhanced ride-through performance and enables the MLI switching algorithm to be modified for CMV cancellation. Simulation results with SVPWM control techniques verified the proposed concepts. With the appropriate design of the balancing controller, the NP voltage variation is shown to be significantly reduced, while allowing enhanced ride-through performance and CMV cancellation. The added features of NP balancing and ridethrough enhancement do come with additional components, which increase the cost and complexity of the MLI hardware, the extent of which is dependent on the application. REFERENCES [1] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point clamped PWM inverter, IEEE Trans. Ind. Applications., vol. 17, Sept./Oct. 1981, pp [2] K. R. M. N. Ratnayake, Y. Murai, and T. Watanabe, Novel PWM scheme to control neutral point voltage variation in three-lever voltage source inverter, in Conf. Rec. IEEE-IAS Annual Meeting, 1999, pp [3] J.H. Suh, C.H. Choi and D.-S. Hyun, A new simplified space-vector PWM method for three-lever inverters, in Conf. Rec. IEEE-IAS Annual Meeting, 1999, pp [4] Y.-H. Lee, R.-Y. Kim, and D.-S. Hyum, A novel SVPWM strategy considering dc-link balancing for a multi-level voltage source inverter, in Proc. IEEE APEC 99, 1999, pp [] A. Von Jouanne, P. Enjeti and W. Gray, Application Issues for PWM Adjustable Speed AC Motor Drives, IAS Magazine, September/October, 1996, pp [6] J. M. Erdman, R. J. Kerkman, D. W. Schlegel and G. L. Skibinski, Effect of PWM Inverters on AC Motor Bearing Currents and Shaft Voltages, IEEE Transactions on Industry Applications, Vol. IA-32, No. 2, 1996, pp [7] X. Yuan and I. Barbi, Soft-switched three level capacitor clamping inverter with clamping voltage stabilization, in Conf. Rec. IEEE-IAS Annu. Meeting, 1999, pp [8] N. Celanovic and D. Boroyevich, A comprehensive study of neutral point voltage balancing problem in three-lever neutral-point-clamped voltage source PWM inverters, IEEE Trans. Power Electron., vol. 1, March 2, pp [9] H. Zhang, A. von Jouanne, S. Dai, A. Wallace, and F. Wang, Multilevel inverter modulation schemes to eliminate common-mode voltages, IEEE Trans Ind. Applications, vol. 36, Nov/Dec. 2, pp [1] F.Wang, Motor shaft voltages and bearing currents and their reduction in multilevel medium-voltage PWM voltage-source-inverter drive applications, IEEE Trans Ind. Applications, vol. 36, Sept/Oct 2, pp [11] R. A. Hanna and S. Prabhu, Medium-voltage adjustable-speed drives Users and manufacturers experiences, IEEE Trans. Ind. Applicat., vol. 33, Nov./Dec. 1997, pp [12] J. F. Silva, A. Galhardo, and J. Palma, High-efficiency ripple-free power converter for nuclear magnetic resonance, in Proc. IEEE PESC, 2, pp