EVALUATION KIT AVAILABLE Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies TOP VIEW DPRSLPVR 45

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1 ; Rev ; 1/9 EVALUATION KIT AVAILABLE Dual-Phase, Quick-PWM Controller General Description The MAX1741 is a 2-/1-phase interleaved Quick- PWM step-down VID power-supply controller for notebook IMVP6+ CPUs. True out-of-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The Quick-PWM control scheme provides instantaneous response to fast load current steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. The MAX1741 is intended for two different CPU core applications: either bucking down the battery directly to create the core voltage, or bucking down the +5V system supply. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, 2-stage conversion (stepping down the +5V system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. A slew-rate controller allows controlled transitions between VID codes. A thermistor-based temperature sensor provides programmable thermal protection. A power monitor provides a buffered analog voltage output proportional to the power delivered to the load. The MAX1741 is available in a 48-pin, 7mm x 7mm TQFN package. Features Dual-/Single-Phase Interleaved Quick-PWM Controller ±.5% V OUT Accuracy Over Line, Load, and Temperature 7-Bit IMVP6+ DAC Dynamic Phase Selection Optimizes Active/Sleep Efficiency Transient Phase Overlap Reduces Output Capacitance Active Voltage Positioning with Adjustable Gain Accurate Lossless Current Balance Accurate Droop and Current Limit Remote Output and Ground Sense Adjustable Output Slew-Rate Control Power-Good Window Comparator Power Monitor Programmable Thermal-Fault Protection Phase Fault Output (PHASEGD) Drives Large Synchronous Rectifier FETs 4.5V to 26V Battery Input Range Output Overvoltage and Undervoltage Protection Soft-Startup and Soft-Shutdown Integrated Boost Switches Low-Profile 7mm x 7mm, 48-Pin TQFN Package MAX1741 Applications IMVP6+ Core Supply Multiphase CPU Core Supply Voltage-Positioned, Step-Down Converters Notebook/Desktop Computers Ordering Information PART TEMP RANGE PIN-PACKAGE MAX1741GTM+ -4 C to +15 C 48 TQFN-EP* +Denotes a lead(pb)-free/rohs-compliant package. *EP = Exposed pad. TOP VIEW D 37 D1 38 D2 39 D3 4 D4 41 D5 42 D6 43 SHDN 44 DPRSLPVR 45 DPRSTP 46 CLKEN 47 V3P3 48 Pin Configuration BST1 DH1 LX1 PGND1 DL1 VDD DL2 PGND2 LX2 DH2 BST2 N.C CSP1 23 CSP2 22 V CC 21 GND 2 IN 19 CSPAVG MAX CSN1 17 CSN2 16 CCI 15 GNDS 14 OUTS 13 ILIM Quick-PWM is a trademark of Maxim Integrated Products, Inc. PWRGD PSI PMON THRM VRHOT NTC PHASEGD PGDIN THIN QFN FB VPS SGND TIME Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 MAX1741 ABSOLUTE MAXIMUM RATINGS V CC, V DD, V3P3 to GND...-.3V to +6V D D6, PSI, DPRSLPVR, DPRSTP to GND...-.3V to +6V CSPAVG, CSP_, CSN_, ILIM to GND...-.3V to +6V PWRGD, PHASEGD, VRHOT to GND...-.3V to +6V FB, OUTS, CCI, TIME, PMON to GND...-.3V to (V CC +.3V) PGDIN, NTC, THRM to GND...-.3V to (V CC +.3V) CLKEN to GND...-.3V to (V 3P3 +.3V) VPS to OUTS...-.3V to +.3V SHDN to GND (Note 1)...-.3V to +3V IN to GND...-.3V to +3V GNDS, SGND, PGND_ to GND...-.3V to +.3V DL_ to GND...-.3V to (V DD +.3V) BST_ to V DD...-.3V to +3V LX_ to BST_...-6V to +.3V DH_ to LX_...-.3V to (V BST - +.3V) Continuous Power Dissipation (48-pin, 7mm x 7mm TQFN) Up to +7 C mW Derating Above +7 C mW/ C Operating Temperature Range...-4 C to +15 C Junction Temperature C Storage Temperature Range C to +165 C Lead Temperature (soldering, 1s)...+3 C Note 1: SHDN may be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Input Voltage Range DC Output Voltage Accuracy V OUT V CC, V DD V3P IN Measured at FB with respect to GNDS, includes load regulation error (Note 2) DAC codes from.8125v to 1.5V DAC codes from.375v to.8v DAC codes from to.3625v % Boot Voltage V BOOT V Line Regulation Error V CC = 4.5V to 5.5V, V IN = 4.5V to 26V.1 % OUTS Input Bias Current VPS floating, T A = +25 C μa OUTS-to-VPS Resistance SGND-to-AGND Resistance 2.5 GNDS Input Range mv GNDS Gain A GNDS V OUT / V GNDS V/V GNDS Input Bias Current I GNDS V(OUTS, GNDS) = 1.V μa TIME Regulation Voltage V TIME R TIME = 71.5k V V mv 2

3 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIME Slew-Rate Accuracy R TIME = 71.5k (12.5mV/μs nominal) R TIME = 35.7k (25mV/μs nominal) to 178k (5mV/μs nominal) Soft-start and soft-shutdown: R TIME = 35.7k (3.125mV/μs nominal) to 178k (.625mV/μs nominal) Slow: V DPRSTP = V DPRSLPVR = 5V, 1/4 normal slew rate, R TIME = 35.7k (6.25mV/μs nominal) to 178k (1.25mV/μs nominal) On-Time Accuracy t ON V DIODE ), measured at DH_, 3kHz per V IN = 1V, V FB = 1.V, V CCI = (1.V + phase nominal (Note 3) % ns Minimum Off-Time t OFF(MIN) Measured at DH_ (Note 3) ns BIAS CURRENTS Quiescent Supply Current (V CC ) I CC Measured at V CC, V DPRSLPVR = 5V, FB forced above the regulation point 3 6 ma MAX1741 Quiescent Supply Current (V DD ) I DD Measured at V DD, V DPRSLPVR =, FB forced above the regulation point, T A = +25 C Quiescent Supply Current (V3P3) I 3P3 Measured at V3P3, FB forced within the CLKEN power-good window, T A = +25 C.2 1 μa.1 1 μa Quiescent Supply Current (IN) I IN Measured at IN, V IN = 1V μa Shutdown Supply Current (V CC ) I CC,SDN Measured at V CC, SHDN = GND, T A = +25 C.1 1 μa Shutdown Supply Current (V DD ) I DD,SDN Measured at V DD, SHDN = GND, T A = +25 C.1 1 μa Shutdown Supply Current (V3P3) I 3P3,SDN Measured at V3P3, SHDN = GND, T A = +25 C.1 1 μa Shutdown Supply Current (IN) I IN,SDN Measured at IN, V IN = 26V, SHDN = GND, V CC = V or 5V, T A = +25 C FAULT PROTECTION Output Overvoltage- Protection Threshold Output Overvoltage- Propagation Delay V OVP Skip mode after output reaches the regulation voltage or PWM mode, measured at FB with respect to the voltage target set by the VID code (see Table 4) Soft-start, soft-shutdown, skip mode, and output has not reached the regulation voltage; measured at FB.1.1 μa mv Minimum OVP threshold; measured at FB.8 t OVP FB forced 25mV above trip threshold 1 μs V 3

4 MAX1741 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Undervoltage- Protection Threshold Output Undervoltage- Propagation Delay V UVP Measured at FB with respect to the voltage target set by the VID code; see Table mv t UVP FB forced 25mV below trip threshold 1 μs CLKEN Startup Delay and Boot Time Period t BOOT Measured from the time when FB reaches the boot target voltage (Note 2) μs PWRGD Startup Delay Measured at startup from the time when CLKEN goes low ms CLKEN and PWRGD Threshold Measured at FB with respect to the voltage target set by the VID code; see Table 4, 2mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) mv CLKEN and PWRGD Delay FB forced 25mV outside the PWRGD trip thresholds 1 μs PHASEGD Delay CLKEN, PWRGD, and PHASEGD Transition Blanking Time (VID Transitions) PHASEGD Transition Blanking Time (Phase 2 Enable Transitions) t BLANK V(CCI, FB) forced 25mV outside trip thresholds Measured from the time when FB reaches the target voltage (Note 2) Number of DH2 pulses for which PHASEGD is blanked after phase 2 is enabled 1 μs 2 μs 32 Pulses CLKEN Output Low Voltage Low state, I SINK = 3mA.4 V CLKEN Output High Voltage High state, I SOURCE = 3mA V3P3 -.4 V PWRGD, PHASEGD Output Low Voltage Low state, I SINK = 3mA.4 V PWRGD, PHASEGD Leakage Current CSN_ Pulldown Resistances in Shutdown V CC Undervoltage-Lockout Threshold THERMAL PROTECTION High-impedance state; PWRGD, PHASEGD forced to 5V; T A = +25 C SHDN =, measured after soft-shutdown completed (DL = low) V UVLO(VCC) Rising edge, 65mV typical hysteresis, controller disabled below this level 1 μa V THRM, NTC Pullup Current I THRM, I NTC V THRM = V NTC = 1V μa Ratio of NTC Pullup Current to THRM Pullup Current I NTC /I THRM V THRM = V NTC = 1V μa/μa 4

5 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VRHOT Trip Threshold Measured at NTC with respect to THRM, V THRM = 1V, falling edge; typical hysteresis = 1mV VRHOT Delay t VRHOT V NTC forced 25mV below V THRM, V THRM = 1V, falling edge mv 1 μs VRHOT Output On-Resistance R ON(VRHOT) Low state 2 8 VRHOT Leakage Current High-impedance state, VRHOT forced to 5V, T A = +25 C 1 μa Thermal-Shutdown Threshold T SHDN Typical hysteresis = 15 C +16 C VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Positive) V TIME - V ILIM = 1mV V LIMIT V CSP_ - V CSN_ V TIME - V ILIM = 5mV ILIM = V CC mv MAX1741 Current-Limit Threshold Voltage (Negative) Accuracy Current-Limit Threshold Voltage (Zero Crossing) CSPAVG, CSP_, CSN_ Common-Mode Input Range V LIMIT(NEG) V CSP_ - V CSN_, nominally -125% of V LIMIT mv V ZERO V AGND - V LX_, DPRSLPVR = 5V 1 mv 2 V Phase 2 Disable Threshold Measured at CSP2 3 V CC - 1 V CC -.4 V CSPAVG, CSP_, CSN_ Input Current I CSPAVG, I CSP_, I CSN_ T A = +25 C μa ILIM Input Current I ILIM T A = +25 C μa Droop Amplifier Offset [V CSPAVG - (V CSN1 + T A = +25 C V CSN2 )/2] at I FB = T A = C to +85 C mv Droop Amplifier Transconductance Power Monitor Output Voltage for Typical HFM Conditions Power Monitor Gain Referred to Output Voltage V(OUTS, GNDS) Power Monitor Gain Referred to [V CSPAVG - (V CSN1 + V CSN2 )/2] G m(fb) I FB / [V CSPAVG - (V CSN1 + V CSN2 )/2], V FB = V CSN_ =.45V to 1.5V V PMON V(OUTS, GNDS) = 1.2V, I PMON = μa A PMON/ V OUT [V CSPAVG - (V CSN1 + V CSN2 )/2] = 15mV, V(TIME, ILIM) = 225mV [V CSPAVG - (V CSN1 + V CSN2 )/2] = 15mV, V(TIME, ILIM) = 5mV [V CSPAVG - (V CSN1 + V CSN2 )/2] = 15mV, V(TIME, ILIM) = 225mV, I PMON = μa A PMON/ V CS V(CSN, GNDS) = 1.2V, V(TIME, ILIM) = 225mV, I PMON = μa ms V V/V V/V 5

6 MAX1741 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Monitor Load Regulation Measured at PMON I PMON = to 5μA -6 μv/μa with respect to unloaded voltage I PMON = -1μA 5 mv Current Balance Amplifier Offset (V CSP1 - V CSN1 ) - (V CSP2 - V CSN2 ) at I CCI = mv Current Balance Amplifier Transconductance GATE DRIVERS G m(cci) I CCI / [(V CSP1 - V CSN1 ) - (V CSP2 - V CSN2 )], V CSN_ =.45V to 1.5V 2 μs BST_ - LX_ forced High state (pullup) DH_ Gate-Driver On-Resistance R ON(DH_) to 5V Low state (pulldown).7 2. High state (pullup).7 2. DL_ Gate-Driver On-Resistance R ON(DL_) Low state (pulldown).25.7 DH_ Gate-Driver Source Current I DH_(SOURCE) DH_ forced to 2.5V, BST_ - LX_ forced to 5V 2.2 A DH_ Gate-Driver Sink Current I DH_(SINK) DH_ forced to 2.5V, BST_ - LX_ forced to 5V 2.7 A DL_ Gate-Driver Source Current I DL_(SOURCE) DL_ forced to 2.5V 2.7 A DL_ Gate-Driver Sink Current I DL_(SINK) DL_ forced to 2.5V 8 A Driver Propagation Delay DL_ Transition Time DH_ Transition Time Internal BST_ Switch On-Resistance LOGIC AND I/O t DH_DL_ DH_ low to DL_ high 2 t DL_DH_ DL_ low to DH_ high 2 DL_ falling, C DL_ = 3nF 2 DL_ rising, C DL_ = 3nF 2 DH_ falling, C DH_ = 3nF 2 DH_ rising, C DH_ = 3nF 2 R ON(BST_) 1 2 Logic Input High Voltage V IH SHDN, PGDIN, DPRSLPVR 2.3 V Logic Input Low Voltage V IL SHDN, PGDIN, DPRSLPVR 1. V Low-Voltage Logic Input High Voltage V IHLV PSI, D D6, DPRSTP.67 V ns ns ns Low-Voltage Logic Input Low Voltage V ILLV PSI, D D6, DPRSTP.33 V Logic Input Current T A = +25 C, PGDIN T A = +25 C, SHDN, DPRSLPVR, PSI, DPRSTP, D D6 = or 5V μa 6

7 ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = -4 C to +15 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Input Voltage Range DC Output Voltage Accuracy V OUT V CC, V DD V3P IN Measured at FB with respect to GNDS, includes load regulation error (Note 2) DAC codes from.8125v to 1.5V DAC codes from.375v to.8v DAC codes from to.3625v % Boot Voltage V BOOT V OUTS to VPS Resistance GNDS Input Range mv GNDS Gain A GNDS V OUT / V GNDS V/V GNDS Input Bias Current I GNDS V(OUTS, GNDS) = 1.V μa TIME Regulation Voltage V TIME R TIME = 71.5k V R TIME = 71.5k (12.5mV/μs nominal) V mv MAX1741 R TIME = 35.7k (25mV/μs nominal) to 178k (5mV/μs nominal) TIME Slew-Rate Accuracy Soft-start and soft-shutdown: R TIME = 35.7k (3.125mV/μs nominal) to 178k (.625mV/μs nominal) % Slow: V DPRSTP = V DPRSLPVR = 5V, 1/4 normal slew rate, R TIME = 35.7k (6.25mV/ μs nominal) to 178k (1.25mV/μs nominal) On-Time Accuracy t ON V DIODE ), measured at DH_, 3kHz per V IN = 1V, V FB = 1.V, V CCI = (1.V + phase nominal (Note 3) ns Minimum Off-Time t OFF(MIN) Measured at DH_ (Note 3) 375 ns BIAS CURRENTS Quiescent Supply Current (V CC ) I CC Measured at V CC, V DPRSLPVR = 5V, FB forced above the regulation point 6 ma Quiescent Supply Current (IN) I IN Measured at IN, V IN = 1V 25 μa 7

8 MAX1741 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = -4 C to +15 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FAULT PROTECTION Output Overvoltage-Protection Threshold V OVP Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to the voltage target set by the VID code (see Table 4) Soft-start, soft-shutdown, skip mode, and output has not reached the regulation voltage; measured at FB mv V Output Undervoltage-Protection Threshold V UVP Measured at FB with respect to the voltage target set by the VID code (see Table 4) mv CLKEN Startup Delay and Boot Time Period t BOOT Measured from the time when FB reaches the boot target voltage (Note 2) 2 1 μs PWRGD Startup Delay CLKEN and PWRGD Threshold Measured at startup from the time when CLKEN goes low Measured at FB with respect to the voltage target set by the VID code (see Table 4), 2mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) 3 1 ms CLKEN Output Low Voltage Low state, I SINK = 3mA.4 V mv CLKEN Output High Voltage High state, I SOURCE = 3mA V3P3 -.4 V PWRGD, PHASEGD Output Low Voltage Low state, I SINK = 3mA.4 V PWRGD, PHASEGD Leakage Current High-impedance state; PWRGD, PHASEGD forced to 5V; T A = +25 C 1 μa V CC Undervoltage-Lockout Threshold THERMAL PROTECTION V UVLO(VCC) Rising edge, 65mV typical hysteresis, controller disabled below this level V THRM, NTC Pullup Current I THRM, I NTC V THRM = V NTC = 1V 4 6 μa Ratio of NTC Pullup Current to THRM Pullup Current I NTC /I THRM V THRM = V NTC = 1V μa/μa VRHOT Trip Threshold Measured at NTC with respect to THRM, V THRM = 1V, falling edge; typical hysteresis = 1mV mv VRHOT Output On-Resistance R ON(VRHOT) Low state 8 8

9 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = -4 C to +15 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Positive) Current-Limit Threshold Voltage (Negative) Accuracy V TIME - V ILIM = 1mV 7 13 V LIMIT V CSP_ - V CSN_ V TIME - V ILIM = 5mV ILIM = V CC 2 25 V LIMIT(NEG) V CSP_ - V CSN_-, nominally -125% of V LIMIT mv mv MAX1741 CSPAVG, CSP_, CSN_ Common-Mode Input Range 2 V Phase 2 Disable Threshold Measured at CSP2 3 Droop Amplifier Offset V CC -.4 [V CSPAVG - (V CSN1 + T A = +25 C V CSN2 )/2] at I FB = T A = C to +85 C V mv Droop Amplifier Transconductance G m(fb) I FB / [V CSPAVG - (V CSN1 + V CSN2 )/2], V FB = V CSN- =.45V to 1.5V ms Power Monitor Output Voltage for Typical HFM Conditions [V CSPAVG - (V CSN1 + V CSN2 )/2] = 15mV, V(TIME, ILIM) = V(OUTS, GNDS) = 225mV V PMON 1.2V, I PMON = μa [VCSPAVG - (V CSN1 + V CSN2 )/2] = 15mV, V(TIME, ILIM) = 5mV V Power Monitor Gain Referred to Output Voltage V(OUTS, GNDS) A PMON/VOUT [V CSPAVG - (V CSN1 + V CSN2 )/2] = 15mV, V(TIME, ILIM) = 225mV, I PMON = μa V/V Power Monitor Gain Referred to [V CSPAVG - (V CSN1 + V CSN2 )/2] Power Monitor Load Regulation A PMON/VCS V(CSN, GNDS) = 1.2V, V(TIME, ILIM) = 225mV, I PMON = μa Measured at PMON with respect to unloaded voltage V/V I PMON = to 5μA -6 μv/μa Current Balance Amplifier Offset (V CSP1 - V CSN1 ) - (V CSP2 - V CSN2 ) at I CCI = mv 9

10 MAX1741 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V IN = 1V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V V3P3 = 3.3V, V DPRSLPVR = V DPRSTP = V GNDS = V PGND_ =, CSPAVG = CSP_ = CSN_ = OUTS = 1.V, R FB = 3.57kΩ from FB to VPS, [D6 D] = [11]; T A = -4 C to +15 C, unless otherwise noted.) GATE DRIVERS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BST_ - LX_ forced High state (pullup) 2.5 DH_ Gate-Driver On-Resistance R ON(DH_) to 5V Low state (pulldown) 2. High state (pullup) 2. DL_ Gate-Driver On-Resistance R ON(DL_) Low state (pulldown).7 Internal BST_ Switch On-Resistance R ON(BST_) I BST_ = 1mA 2 LOGIC AND I/O Logic Input High Voltage V IH SHDN, PGDIN, DPRSLPVR 2.3 V Logic Input Low Voltage V IL SHDN, PGDIN, DPRSLPVR 1. V Low-Voltage Logic Input High Voltage V IHLV PSI, D D6, DPRSTP.67 V Low-Voltage Logic Input Low Voltage V ILLV PSI, D D6, DPRSTP.33 V Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. The output voltage has a DC regulation higher than the trip level by 5% of the output ripple. When pulse skipping, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. Note 3: On-time and minimum off-time specifications are measured from 5% to 5% at the DL_ and DH_ pins, with LX_ forced to GND, BST_ forced to 5V, and a 5pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual incircuit times might be different due to MOSFET switching speeds.s 1

11 Typical Operating Characteristics (Circuit of Figure 1, V IN = 12V, V CC = V DD = 5V, SHDN = V CC, D D6 set for 1.15V, T A = +25 C, unless otherwise specified.) OUTPUT VOLTAGE (V) 2-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (V OUT(HFM) = 1.75V) MAX1741 toc1 EFFICIENCY (%) PHASE EFFICIENCY vs. LOAD CURRENT (V OUT(HFM) = 1.75V) 7V 2V 12V MAX1741 toc2 OUTPUT VOLTAGE (V) 1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (V OUT(HFM) =.875V) PWM MODE SKIP MODE MAX1741 toc3 MAX LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A) EFFICIENCY (%) SUPPLY CURRENT (ma) PHASE EFFICIENCY vs. LOAD CURRENT (V OUT(LFM) =.875V) 7V 2V 12V 4 SKIP MODE PWM MODE LOAD CURRENT (A) NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE AT SKIP MODE (V OUT(HFM) = 1.75V) I CC + I DD DPRSLPVR = V CC I IN INPUT VOLTAGE (V) MAX1741 toc4 MAX1741 toc7 SWITCHING FREQUENCY (khz) SAMPLE PERCENTAGE (%) SWITCHING FREQUENCY vs. LOAD CURRENT V OUT(LFM) =.875V V OUT(HFM) = 1.75V 5 DPRSLPVR = V CC DPRSLPVR = GND LOAD CURRENT (A).8125V OUTPUT-VOLTAGE DISTRIBUTION C SAMPLE SIZE = C OUTPUT VOLTAGE (V) 11 MAX1741 toc5 MAX1741 toc8 SUPPLY CURRENT (ma) SAMPLE PERCENTAGE (%) NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (V OUT(HFM) = 1.75V) I IN I CC + I DD DPRSLPVR = GND PSI = V CC INPUT VOLTAGE (V) Gm(FB) TRANSCONDUCTANCE DISTRIBUTION C SAMPLE SIZE = C TRANSCONDUCTANCE (μs) MAX1741 toc6 MAX1741 toc9

12 MAX1741 Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = 12V, V CC = V DD = 5V, SHDN = V CC, D D6 set for 1.15V, T A = +25 C, unless otherwise specified.) V(CSP-CSN)1,2 (mv) CURRENT BALANCE vs. LOAD CURRENT MAX1741 toc V OUT = 1.75V V CSPN1 - V CSPN2 V CSP1 - V CSN1 V -.4 CSP2 - V CSN LOAD CURRENT (A) ΔV(CSP-CSN)1,2 (mv) 5V 3.3V 1.75V SOFT-START WAVEFORM (UP TO CLKEN) A. SHDN, 5V/div B. CLKEN, 3.3V/div C. V OUT, 5mV/div 2μs/div MAX1741 toc11 D. I LX1, 1A/div E. I LX2, 1A/div I OUT = A B C D E 5V 3.3V 3.3V 3.3V 1.75V SOFT-START WAVEFORM (UP TO PWRGD) MAX1741 toc12 A B C D E 5V 3.3V 3.3V 5V 1.75V SHUTDOWN WAVEFORM MAX1741 toc13 A B C D E 47A 9A 1.75V 1V 25A LOAD-TRANSIENT RESPONSE (HFM MODE) MAX1741 toc14 A B C F G F G 5A 5A D 1ms/div A. SHDN, 1V/div B. CLKEN, 6.6V/div C. PWRGD, 1V/div D. PHASEGD, 1V/div E. V OUT, 5mV/div F. I LX1, 1A/div G. I LX2, 1A/div I OUT = A. SHDN, 1V/div B. PWRGD, 1V/div C. CLKEN, 6.6V/div D. DL1, 5V/div 1μs/div E. V OUT, 5mV/div F. I LX1, 1A/div G. I LX2, 1A/div A. I OUT = 9A 47A B. V OUT, 5mV/div 2μs/div C. I LX1, 1A/div D. I LX2, 1A/div 12

13 Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = 12V, V CC = V DD = 5V, SHDN = V CC, D D6 set for 1.15V, T A = +25 C, unless otherwise specified.) 2A 5A.875V LOAD-TRANSIENT RESPONSE (LFM MODE) MAX1741 toc15 A B 5V 5V 1.75V ENTERING DEEPER SLEEP EXITING TO LFM (SLOW C4) MAX1741 toc16 A B C 5V 5V 1.75V ENTERING DEEPER SLEEP EXITING TO NEAREST VID MAX1741 toc17 A B C MAX1741 2A C.65V D.675V D 5A E E A. I OUT = 5A 2A B. V OUT, 2mV/div C. I LX1, 1A/div 2μs/div PSI = GND DPRSLPVR = GND A. DPRSTP, 5V/div B. DPRSLPVR, 1V/div C. V OUT, 2mV/div 1μs/div D. I LX2, 1A/div E. I LX1, 1A/div I OUT = 3A 4μs/div A. DPRSTP, 5V/div B. DPRSLPVR, 1V/div C. V OUT, 2mV/div D. I LX2, 1A/div E. I LX1, 1A/div I OUT = 3Av ENTERING DEEPER SLEEP EXITING TO LFM (FAST C4) MAX1741 toc18 D 12.5mV DYNAMIC VID CODE CHANGE MAX1741 toc19 D3 1mV DYNAMIC VID CODE CHANGE MAX1741 toc2 5V 5V 1.75V.65V A B C D 5V 1.75V 1.625V A B C 5V 1.75V.975V 5A A B C E D 5A D A. DPRSTP, 5V/div B. DPRSLPVR, 1V/div C. V OUT, 2mV/div 1μs/div D. I LX2, 1A/div E. I LX1, 1A/div I OUT = 3Av A. VID, 5V/div B. V OUT, 2mV/div 1μs/div C. I LX1, 1A/div D. I LX2, 1A/div A. D3, 5V/div B. V OUT, 5mV/div I OUT, = 1A 1μs/div C. I LX1, 1A/div D. I LX2, 1A/div 13

14 MAX1741 Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = 12V, V CC = V DD = 5V, SHDN = V CC, D D6 set for 1.15V, T A = +25 C, unless otherwise specified.) POWER MONITOR (V) MAX1741 POWER MONITOR vs. LOAD CURRENT V OUT = 1.75V DPRSLPVR = V CC DPRSLPVR = GND LOAD CURRENT (A) MAX1741 toc21 POWER MONITOR (V) MAX1741 POWER MONITOR vs. OUTPUT VOLTAGE V IN = 12V I OUT = 2A OUTPUT VOLTAGE (V) MAX1741 toc22 5V 1.75V.975V.35V 5A 5A A. D3, 5V/div B. V OUT, 5mV/div I OUT = 1A POWER MONITOR VID TRANSITION RESPONSE 1μs/div MAX1741 toc23 C. V PMON, 5mV/div D. I LX1, 1A/div E. I LX2, 1A/div A B C D 6A.875V 5V 3.3V 25A OUTPUT UNDERVOLTAGE FAULT MAX1741 toc24 A B C D E 1.75V 3.3V 5V OUTPUT OVERVOLTAGE WAVEFORM MAX1741 toc25 A B C 5V 1.75V 3.3V 5V BIAS SUPPLY REMOVAL (UVLO RESPONSE) MAX1741 toc26 A B C D E A. I OUT, 1A/div B. V OUT, 5mV/div C. DL, 5V/div 1μs/div D. PWRGD, 3.3V/div E. I LX1, 1A/div 1μs/div A. V OUT, 5mV/div B. PWRGD, 3.3V/div C. DL1, 5V/div DPRSLPVR = V CC 4μs/div A. 5V BIAS SUPPLY, 2V/div B. V OUT, 5mV/div C. PWRGD, 3.3V/div D. DL1, 5V/div E. I LX1, 1A/div I OUT = 5A 14

15 PIN NAME FUNCTION 1 PWRGD 2 PSI 3 PMON Pin Description Open-Drain Power-Good Output. After output voltage transitions, except during power-up and powerdown, if FB is in regulation, then PWRGD is high impedance. PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes high if FB is within the PWRGD threshold window. PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions), and continues to be forced high impedance for an additional 2μs after the transition is completed. The PWRGD upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-ratecontrolled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. A pullup resistor on PWRGD causes additional finite shutdown current. Power-State Indicator. This low-voltage logic input indicates power usage and sets the operating mode together with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if PSI is forced low, the controller is immediately set to 1-phase forced-pwm mode. The controller returns to 2-phase forced-pwm mode when PSI is forced high. DPRSLPVR PSI Mode 1 Very low current (1-phase skip) 1 1 Low current (approx 3A) (1-phase skip) Intermediate power potential (1-phase PWM) 1 Max power potential (full-phase PWM: 2-phase or 1-phase as set by user at CSP2) The controller is in 2-phase skip mode during startup, but is in 2-phase forced-pwm mode during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. The controller is also in 2-phase skip mode while in boot mode, but is in 2-phase forced-pwm mode during the transition from boot mode to VID mode, irrespective of the DPRSLPVR and PSI logic levels. However, if phase 2 is disabled by connecting CSP2 to V CC, then only phase 1 is active in the above modes. Power Monitor Output: V(PWR) = K PWR x V(OUTS, GNDS) x V(CSPAVG, CSN)/V(TIME, ILIM) where K PWR = typical. If ILIM is externally connected to a 5V rail to enable the internal default/preset current-limit threshold, then the V(TIME, ILIM) value to be used in the above equation is 225mV. Do not use the power monitor in any configuration that would cause its output V(PMON) to exceed (V CC -.5V). PMON is pulled to ground when the MAX1741 is in shutdown. MAX THRM 5 VRHOT 6 NTC Resistive Input of Thermal Comparator. Connect a resistor to ground to set the VRHOT threshold. THRM and NTC have matched 5μA current sources, so the resistance value = the NTC resistance at the desired high temperature. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. VRHOT is high impedance in shutdown. Thermistor Input of Thermal Comparator. Connect a standard thermistor to ground. THRM and NTC have matched 5μA current sources, so the resistance value = the NTC resistance at the desired high temperature. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. 15

16 MAX1741 PIN NAME FUNCTION 7 PHASEGD 8 PGDIN 9 FB Pin Description (continued) Open-Drain Phase-Good Output. Used to signal the system that one of the two phases either has a fault condition or is not matched with the other. Detection is done by identifying the need for a large (more than 4%) on-time difference between phases to achieve or move towards current balance. PHASEGD is low in shutdown, and when phase 2 is disabled by connecting CSP2 to V CC. PHASEGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions), and when phase 2 is disabled by the DPRSLPVR and/or PSI inputs. When phase 2 is reenabled, PHASEGD stays high impedance for 32 DH2 pulses, after which it monitors the difference between the on-times of the two phases. PHASEGD is also forced high impedance when V FB is below.5v. Power-Good Logic Input. Indicates the power status of other system rails and used for supply sequencing. Connect this pin to the 5V supply rail or float it if the feature is not needed. During startup, after soft-starting to the boot voltage, the output voltage remains at V BOOT, and the CLKEN and PWRGD outputs remain high and low, respectively, as long as the PGDIN input stays low. When PGDIN later goes high, the output is allowed to transition to the voltage set by the VID code, and CLKEN is allowed to go low. During normal operation, if PGDIN goes low, the controller immediately forces CLKEN high and PWRGD low, and slews the output to the boot voltage while in 2-phase skip mode at 1/8 the normal slew rate set by the TIME resistor. The output then stays at the boot voltage until the controller is turned off or power cycled, or until PGDIN goes high again. Feedback Voltage Input, and Output of the Voltage-Positioning Transconductance Amplifier. The voltage at the FB pin is compared with the slew-rate-controlled target voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator (slow, accurate regulation loop). Having sufficient ripple signal at FB that is in-phase with the sum of the inductor currents is essential for cycle-by-cycle stability. Connect resistor R FB between FB and VPS to set the droop based on the voltage-positioning gain requirements: R FB = R DROOP /[R SENSE x G m(fb) ] where R DROOP is the desired voltage-positioning slope, G m(fb) = 1.2mS typ, and R SENSE is the effective current-sense resistance that is used to provide the (CSPAVG, CSN_) current-sense voltage. If lossless sensing (inductor DCR sensing) is used, consider using a thermistor as part of the CSPAVG filter network to minimize the temperature dependence of the voltage-positioning slope. FB is high impedance in shutdown. 1 VPS Internally Shorted to OUTS Through a 1 Resistance 11 SGND Internally Shorted SGND (Pin 11) to AGND (Pin 21) 12 TIME 13 ILIM Slew-Rate Adjustment Pin. The total resistance R TIME from TIME to GND sets the internal slew rate. SLEW RATE = (12.5mV/μs) x (71.5k /R TIME ) where R TIME is between 35.7k and 178k. This normal slew rate applies to transitions into and out of the low-power pulse-skipping modes and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is always 1/8 of normal. If DPRSLPVR and DPRSTP are both high, then the slew rate is reduced to 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew rate defined above. Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_, CSN_) are precisely 1/1 the differential voltage V(TIME, ILIM) over a.1v to.5v range of V(TIME, ILIM). The valley negative current-limit thresholds are typically -125% of the corresponding valley positive current-limit thresholds. Connect ILIM to V CC to get the default current-limit threshold setting of 22.5mV typ. 16

17 PIN NAME FUNCTION 14 OUTS 15 GNDS 16 CCI 17 CSN2 18 CSN1 19 CSPAVG Pin Description (continued) Output Remote Sense. Internally shorted to VPS through a 1 resistance. OUTS is also the voltage feedback input to the power monitor. Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load. GNDS internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the regulator ground to the load ground. Current-Balance Compensation. Connect a 47pF capacitor between CCI and the positive side of the feedback remote-sense input (or between CCI and GND). CCI is internally forced low in shutdown. Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Positive Input of the Output Current-Sense Averaging Network. This input should be connected to the positive current-sense averaging network (see the standard 2-phase IMVP6+ application circuit of Figure 1) and is utilized for load line control and power monitoring (input of the transconductance amplifiers used for FB and PMON). MAX IN Input Sense for On-Time Control. An internal resistor sets the switching frequency to 3kHz per phase. IN is high impedance in shutdown. 21 GND Analog Ground Connect 22 V CC Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum. 23 CSP2 24 CSP1 Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive side of the output current-sensing resistor, or to the filtering capacitor if the DC resistance of the output inductor is used for current sensing. This pin is utilized for current limit and current balance only. Connect CSP2 to V CC to disable phase 2 and use the MAX1741 as a single-phase controller. In this configuration, connect LX2 to GND, connect BST2 to V DD, CSN2 to CSN1, and float DH2, DL2, CCI, and PHASEGD. Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of the output current-sensing resistor, or to the filtering capacitor if the DC resistance of the output inductor is used for current sensing. This pin is utilized for current limit and current balance only. 25 N.C. No Connection. Not internally connected. 26 BST2 Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 high-side gate driver. An internal switch between V DD and BST2 charges the BST2 - LX2 flying capacitor while the low-side MOSFET is on (DL2 pulled high). 27 DH2 Phase 2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown. 28 LX2 Phase 2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also used as an input to phase 2 s zero-crossing comparator. 29 PGND2 Power Ground. PGND2 is the internal lower supply rail for the DL2 low-side gate driver. 3 DL2 Phase 2 Low-Side Gate-Driver Output. DL2 swings from PGND2 to V DD. DL2 is forced low in shutdown. DL2 is forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL2 is forced low in skip mode after detecting an inductor current zero crossing. 31 V DD the BST_ - LX_ flying capacitor during the times the respective DL_ are high. Connect V DD to the Supply Voltage Input for the DL_ Drivers. V DD is also the supply voltage used to internally recharge 4.5V to 5.5V system supply voltage. Bypass V DD to GND with a 1μF or greater ceramic capacitor. 17

18 MAX1741 PIN NAME FUNCTION 32 DL1 Pin Description (continued) Phase 1 Low-Side Gate-Driver Output. DL1 swings from PGND1 to V DD. DL1 is forced low in shutdown. DL1 is forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL1 is forced low in skip mode after detecting an inductor current zero crossing. 33 PGND1 Power Ground. PGND1 is the internal lower supply rail for the DL1 low-side gate driver. 34 LX1 Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also used as an input to phase 1 s zero-crossing comparator. 35 DH1 Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. 36 BST D D6 44 SHDN 45 DPRSLPVR Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1 high-side gate driver. An internal switch between V DD and BST1 charges the BST1 - LX1 flying capacitor, while the low-side MOSFET is on (DL1 pulled high). Low-Voltage (1.V Logic) VID DAC Code Inputs. The D D6 inputs do not have internal pullups. These 1.V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the logic-level voltages on D D6 (see Table 4). Shutdown Control Input. Connect to V CC for normal operation. Connect to ground to put the IC into the 1μA (max at T A = +25 C) shutdown state. During startup, the output voltage is ramped up at 1/8 the slew rate set by the TIME resistor to the boot voltage. During the transition from normal operation to shutdown, the output voltage is ramped down at 1/8 the slew rate set by the TIME resistor. Forcing SHDN to 11V ~ 13V disables overvoltage protection, undervoltage protection, and thermal shutdown, clears the fault latches, disables transient phase overlap, disables soar suppression, and turns off the internal BST_-to-V DD switches. However, internal diodes still exist between BST_ and V DD in this state. 3.3V Logic Input. Indicates power usage and sets the operating mode together with PSI as shown in the truth table below. When DPRSLPVR is forced high, the controller is immediately set to 1- phase automatic pulse-skipping mode. The controller returns to forced-pwm mode when DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. During this blanking period, the overvoltage fault threshold is changed from a tracking [VID + 3mV] threshold to a fixed 1.8V threshold. DPRSLPVR PSI Mode 1 Very low current (1-phase skip) 1 1 Low current (approx 3A) (1-phase skip) Intermediate power potential (1-phase PWM) 1 Max power potential (full-phase PWM: 2-phase or 1-phase as set by user at CSP2) The controller is in 2-phase skip mode during startup, but is in 2-phase forced-pwm mode during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. The controller is in 2-phase skip mode while in boot mode, but is in 2-phase forced-pwm mode during the transition from boot mode to VID mode, irrespective of the DPRSLPVR and PSI logic levels. However, if phase 2 is disabled by connecting CSP2 to V CC, then only phase 1 is active in the above modes. 18

19 PIN NAME FUNCTION 46 DPRSTP 47 CLKEN 48 V3P3 EP Pin Description (continued) Low-Voltage Logic Input Signal. This is usually the logical complement of the DPRSLPVR signal. However, there is a special condition during C4 exit when both DPRSTP and DPRSLPVR could temporarily be simultaneously high. If this happens, the MAX1741 reduces the slew rate to 1/4 the normal (R TIME -based) slew rate for the duration of this condition. The slew rate returns to normal when this condition is exited. Note that only DPRSLPVR and PSI (but not DPRSTP) determine the mode of operation (PWM vs. skip and number of active phases). DPRSLPVR DPRSTP Functionality Normal slew rate, 1- or 2-phase forced-pwm mode (DPRSLPVR low DPRSTP is ignored) 1 Normal slew rate, 1- or 2-phase forced-pwm mode (DPRSLPVR low DPRSTP is ignored) 1 Normal slew rate, 1-phase automatic pulse-skipping mode 1 1 Slew rate reduced to 1/4th of normal, 1-phase automatic pulse-skipping mode Clock Enable CMOS Push-Pull Logic Output Powered by V3P3. This inverted logic output indicates when the output voltage sensed at FB is in regulation. CLKEN is forced high in shutdown and during soft-start and soft-stop transitions. CLKEN is forced low during dynamic VID transitions and for an additional 2μs after the transition is completed. CLKEN is the inverse of PWRGD, except for the 5ms PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram (Figure 9). The CLKEN upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. 3.3V Supply Input for the CLKEN CMOS Push-Pull Logic Output. Connect to the 3.V to 3.6V system supply voltage. Exposed Backplate (Paddle) of Package. Internally connected to analog ground. Connect to the ground plane through a thermally enhanced via. MAX

20 MAX V VID INPUTS ON OFF (VRON) 1kΩ R4 1kΩ AGND AGND R5 1kΩ 4.99kΩ 1kΩ NTC β = D 38 D1 39 D2 4 D3 41 D4 42 D5 43 D6 44 SHDN 45 DPRSLPVR 47 CLKEN 48 V3P3 1 PWRGD 5 VRHOT 7 PHASEGD 4 THRM 6 NTC 46 DPRSTP MAX1741 V CC GND V DD 2 IN BST1 DH1 LX1 DL1 PGND CSP1 8 PGDIN 18 CSN1 Ω 17 CSN2 1pF 16 CCI 19 CSPAVG 25 N.C. C1 1μF AGND R9 Ω R1 1Ω C4.22μF C2 1μF N LO PWR N HI.1μF D1 5V BIAS INPUT 3.32kΩ 2kΩ C IN PWR 1.5kΩ.47μF OPEN L1.36μH.82mΩ OPEN.1μF 1Ω 1kΩ NTC β = 338.1μF INPUT 7V TO 24V C OUT PWR C OUT = 4 x 33μF/4.5mΩ + 32 x 1μF MLCC CORE OUTPUT 61.9kΩ AGND C8.1μF AGND OPEN OPEN OPEN 1kΩ 1kΩ 4.2kΩ 2 PSI 3 PMON 13 ILIM 12 TIME 11 SGND 1 VPS 9 FB CSP2 BST2 DH2 LX2 DL2 PGND2 OUTS GNDS R13 Ω C8.22μF N LO PWR 2kΩ N HI D1 OPEN 3.32kΩ R2 1Ω C9 1pF AGND R21 1Ω C1 1pF AGND L2 REMOTE-SENSE FILTERS 1Ω C OUT R22 25Ω R23 25Ω PWR PWR VCC_SENSE REMOTE-SENSE INPUTS VSS_SENSE CATCH RESISTORS REQUIRED WHEN CPU NOT POPULATED Figure 1. Standard 2-Phase IMVP6+ Application Circuit 2

21 NTC THRM VRHOT CSP2 CSN2 CSP1 CSN1 1X.1X 1X MAX1741 EN2 MINIMUM OFF-TIME SECONDARY PHASE DRIVERS Q TRIG PHASE 2 ON-TIME ONE-SHOT BLANK CURRENT- BALANCE FAULT 5ms STARTUP DELAY CSN2 BST2 DH2 LX2 DL2 PGND2 PHASEGD CCI MAX1741 V CC GND SGND ILIM TIME D D6 DPRSTP REF (2.V) 2.5Ω REF DAC.1X R-TO-I CONVERTER DPRSLPVR Q TRIG ONE SHOT FB PHASE 1 ON-TIME ONE-SHOT Q R S TRIG Q FB MAIN PHASE DRIVERS G m(cci) G m(cci) CSP2 CSP1 CSN1 IN BST1 DH1 SHDN LX1 REF FAULT TARGET Q Q T PGND1 LX1 1mV S R Q V DD G m(ccv) SKIP DL1 FB TARGET - 3mV TARGET + 2mV 5ms STARTUP DELAY PGND1 PWRGD GNDS CSN1 CSN2 CSPAVG G m(fb) V CC EN2 SKIP PHASE CONTROL BLANK CSPAVG, CSN1, CSN2 1Ω OUTS - GNDS 6μs STARTUP DELAY POWER MONITOR V3P3 CLKEN PMON PGDIN DRPSLPVR PSI OUTS VPS Figure 2. Functional Diagram 21

22 MAX1741 Table 1. Component Selection for Standard Applications DESIGN PARAMETERS IMVP6+ SV IMVP6+ LV Circuit Figure 1 Figure 1 Input Voltage Range 7V to 2V 7V to 2V Maximum Load Current Transient Load Current 44A (34A) 35A (1A/μs) 23A (19A) 18A (1A/μs) Load Line -2.1mV/A -4mV/A Inductance (L) High-Side MOSFET (N H ) Low-Side MOSFET (N L ) Output Capacitors (C OUT ) NEC/Tokin MPC155LR36.36μH, 32A,.8m Siliconix 1x Si4386DY 7.8m /9.5m (typ/max) Siliconix 2x Si4642DY 3.9m /4.7m (typ/max) 3x 33μF, 6m, 2.5V Panasonic EEFSXDD331XR 28x 1μF, 6V ceramic (85) NEC/Tokin MPC155LR36.36μH, 32A,.8m Siliconix 1x Si4386DY 7.8m /9.5m (typ/max) Siliconix 2x Si4642DY 3.9m /4.7m (typ/max) 3x 33μF, 6m, 2.5V Panasonic EEFSXDD331XR 28x 1μF, 6V ceramic (85) Input Capacitors (C IN ) 4x 1μF, 25V ceramic (121) 4x 1μF, 25V ceramic (121) TIME-ILIM Resistance (R1) 1k 6.19k ILIM-GND Resistance (R2) 61.9k 64.9k FB Resistance (R FB ) 4.2k 7.68k LX-CSP Resistance (R5) 2k 2k CSP-CSN Series Resistance (R6) 1.5k 1.5k Parallel NTC Resistance (R7) open open DCR Sense NTC (NTC1) 1k NTC B = 338 TDK NTCG163JH13F 1k NTC B = 338 TDK NTCG163JH13F DCR Sense Capacitance (C SENSE ).47μF, 6V ceramic (85).47μF, 6V ceramic (85) Table 2. Component Suppliers MANUFACTURER WEBSITE AVX Corporation BI Technologies Central Semiconductor Corp. Fairchild Semiconductor International Rectifier KEMET Corp. NEC/TOKIN America, Inc. Panasonic Corp. MANUFACTURER Pulse Engineering Renesas Technology Corp. SANYO Electric Co., Ltd. Sumida Corp. Taiyo Yuden TDK Corp. TOKO America, Inc. Vishay/Siliconix WEBSITE

23 MAX1741 Detailed Description Free-Running, Constant On-Time PWM Controller with Input Feed-Forward The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 2). This architecture relies on the output filter capacitor s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to the input voltage, and directly proportional to the output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot section). Another one-shot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley current-limit threshold, and the minimum off-time one-shot times out. The controller maintains 18 out-ofphase operation by alternately triggering the main and secondary phases after the error comparator drops below the output-voltage set point. Dual 18 Out-of-Phase Operation The two phases in the MAX1741 operate 18 out-ofphase to minimize input and output filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count reducing cost, board space, and component power requirements making the MAX1741 ideal for high-power, cost-sensitive applications. Typically, switching regulators provide power using only one phase instead of dividing the power among several phases. In these applications, the input capacitors must support high instantaneous current requirements. The high RMS ripple current can lower efficiency due to I 2 R power loss associated with the input capacitor s effective series resistance (ESR). Therefore, the system typically requires several low- ESR input capacitors in parallel to minimize input voltage ripple, to reduce ESR-related power losses, and to meet the necessary RMS ripple current rating. With the MAX1741, the controller shares the current between two phases that operate 18 out-of-phase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input current of either phase is effectively halved, resulting in reduced input voltage ripple, ESR power loss, and RMS ripple current (see the Input Capacitor Selection section). Therefore, the same performance may be achieved with fewer or less expensive input capacitors. +5V Bias Supply (V CC and V DD ) The Quick-PWM controller requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook s 95% efficient +5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V bias supply can be generated with an external linear regulator. The +5V bias supply must provide V CC (PWM controller) and V DD (gate-drive power), so the maximum current drawn is: ( ) IBIAS = ICC + fsw QG( LOW) + QG( HIGH) where I CC is provided in the Electrical Characteristics table, f SW is the switching frequency, and Q G(LOW) and Q G(HIGH) are the MOSFET data sheet s total gatecharge specification limits at V GS = 5V. V IN and V DD can be connected together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup. Switching Frequency IN (Pin 2) Open-Circuit Protection The MAX1741 input sense (IN) is used to adjust the ontime. An internal resistor sets the switching frequency to 3kHz per phase. IN is high impedance in shutdown. On-Time One-Shot The core of each phase contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFET s on-time. The one-shot for the main phase varies the ontime in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (V FB ): ( ) tsw VFB +. 75V ton( MAIN) = VIN where the switching period (t SW = 1/f SW ) is set to 3.3μs internally, and.75v is an approximation to accommodate the expected drop across the low-side MOSFET switch. MAX