MAX14759/MAX14761/MAX14763 Above- and Below-the-Rails Low On-Resistance Analog Switches

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1 // General Description The // analog switches are capable of passing bipolar signals that are beyond their supply rails. These devices operate from a single +3.V to +5.5V supply and support signals in the -25V to +25V range. The is a single-pole/single-throw (SPST) analog switch, while the is a dual-spst analog switch. The is a single-pole/double-throw (SPDT) analog switch. The features 1I (max) on-resistance with a Q2n (max) on-leakage current. The / feature 2I (max) on-resistance with a Q1n (max) on-leakage current. The low on-resistance and high bandwidth allow use in digital- and analog-signal switching applications. The / are available in an 8-pin (3mm x 3mm) TDFN package. The is available in a 1-pin (3mm x 3mm) TDFN package. These devices are specified over the -4NC to +85NC extended temperature range. Ordering Information/Selector Guide appears at end of data sheet. For related parts and recommended products to use with this part, refer to Benefits and Features S Simplify Power-Supply Requirements +3.V to +5.5V Supply Range -25V to +25V Signal Range S High Performance Low 1I (max) or 2I (max) On-Resistance Low 2.4mI (typ) and 5.1mI (typ) R ON Flatness 5m (max) Switch Current for Thermal Shutdown Protection -4NC to +85NC Operating Temperature Range High Bandwidth: 1MHz (typ) Insertion Loss High-ESD Protection Up to 2kV S Save Board Space Small 8-Pin and 1-Pin TDFN Packages Industrial Measurement Systems Instrumentation Systems RS-485 Termination Switching CN Bus Termination Switching Opto-Relay Replacement Medical Systems TE Systems udio Signal Routing and Switching pplications Functional Diagrams/Truth Tables V P SUPPLY GENERTION V N V P SUPPLY GENERTION V N V P SUPPLY GENERTION V N EN B 1 EN1 B1 1 2 COM 2 B2 SEL EN2 EN EN1 1 EN2 2 SEL 1 2 OPEN CLOSED OPEN CLOSED OPEN 1 CLOSED 1 OPEN 1 CLOSED 1 OPEN CLOSED For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at ; Rev 1; 8/12

2 BSOLUTE MXIMUM RTINGS (ll voltages referenced to, unless otherwise noted.)...-.3v to +6V EN, EN1, EN2, SEL...-.3V to + ( +.3V), B, 1, 2, B1, B2, COM... (V N -.3V) to Lesser of (V P +.3V) or (V N + 52V) V P V to Lesser of (+52V) or (V N + 7V) V N...Greater of ( - 4V) or (V P - 7V) to +.3V V P to V N...-.3V to +7V Continuous Current Through Switch ()... Q5m 8-Pin TDFN Junction-to-mbient Thermal Resistance (q J )...48 C/W Junction-to-Case Thermal Resistance (q JC )...8 C/W // Continuous Current Through Switch (, )... Q25m Continuous Power Dissipation (T = +7NC) 8-Pin TDFN Package (derate 24.4mW/NC above +7NC) mW 1-Pin TDFN Package (derate 24.4mW/NC above +7NC) mW Operating Temperature Range... -4NC to +85NC Storage Temperature Range NC to +16NC Lead Temperature (soldering, 1s)...+3NC Soldering Temperature (reflow)...+26nc Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PCKGE THERML CHRCTERISTICS (Note 1) 1-Pin TDFN Junction-to-mbient Thermal Resistance (q J )...41 C/W Junction-to-Case Thermal Resistance (q JC )...9 C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to ELECTRICL CHRCTERISTICS ( = +3.V to +5.5V, T = -4 C to +85 C, unless otherwise noted. Typical values are at = 5V and T = +25 C.) (Note 2) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS DC CHRCTERISTICS Power Supply Range V Continuous Current Through Switch Supply Current I CC 4.7V nalog-signal Range () I _ (/) > 4.7V V EN_ = V EN_ = / V EN_ = V EN_ = / V COM, V _, V B_ Switch open or closed V On-Resistance R ON I COM or I B_ = Q25m, V _ = Q25V (/) I B = Q5m, V = Q25V ().6 1 On-Resistance Flatness DR ON -25V < V _ < +25V, I B_ or I COM = Q25m (/) V < V < +25V, I B = Q5m () 2.4, 1, 2 Off-Leakage Current I _(OFF) V _ = +25V, V COM or V B_ = V, Figure 1 (/) V = +25V, V B = V, Figure 1 () COM, B, B1, B2 Off-Leakage Current I COM(OFF), I B_(OFF) V COM or V B = 15V, V _ = V, Figure 1 (/) V B_ = 15V, V _ = V, Figure 1 () m m I mi n n 2

3 // ELECTRICL CHRCTERISTICS (continued) ( = +3.V to +5.5V, T = -4 C to +85 C, unless otherwise noted. Typical values are at = 5V and T = +25 C.) (Note 2) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS V = ±25V, B1, B2, or COM are unconnected, Figure 1 () On-Leakage Current DIGITL LOGIC Input-Voltage Low Input-Voltage High I ON V IL V IH V = ±25V, B1, B2, or COM are unconnected, Figure 1 () V = ±25V, B1, B2, or COM are unconnected, Figure 1 () = 3.V.7 = 3.6V.7 = 4.5V.8 = 5.5V.8 = 3.V 1.7 = 3.6V 1.9 = 4.5V 2. = 5.5V 2.1 Input Current I L µ C CHRCTERISTICS Power-On Time t PWRON C VP = C VN = 1nF (Note 3) 5 ms Enable Turn-On Time t ON ) V _ = Q1V, R L = 1kI, Figure 2 (/ n V V Fs V _ = Q1V, R L = 1kI, Figure 2 () ms Enable Turn-Off Time t OFF V _ = Q1V, R L = 1kI, Figure Fs Break-Before-Make Interval t BBM V _ = 1V RMS, R L = 1kI, Figure 3 () 74 Fs Off-Isolation V ISO V _ = 1V RMS, f = 1kHz, R L = 5I, C L = 15pF, Figure 4 Crosstalk V CT R S = R L = 5I, f = 1kHz, V COM = 1V RMS, Figure 5 () -77 db -83 db -3dB Bandwidth BW R S = 5I, R L = 5I, V _ = 1V P-P, Figure 6 1 MHz Total Harmonic Distortion Plus Noise THD+N R S = R L = 1kI, f = 2Hz to 2kHz.12 % Charge Injection Q V _ =, C L = 1nF, Figure pc Input Capacitance C IN t, 1, 2, B, B1, B2, and COM pins 58 pf THERML PROTECTION Thermal Shutdown Temperature t HYST +154 NC Shutdown Temperature Hysteresis t SHUT 24 NC ESD PROTECTION ll Pins Human Body Model Q2 kv Note 2: ll devices are 1% production tested at T = +25NC. Specifications over operating temperature range are guaranteed by design. Note 3: The power-on time is defined as the settling time for the charge pump s output to reach steady-state value within 1%. 3

4 // Test Circuits/Timing Diagrams 1µF 1µF _ B_/COM _ B_/COM UNCONNECTED EN_/SEL EN_/SEL SWITCH OPEN SWITCH CLOSED OFF-LEKGE CURRENT ON-LEKGE CURRENT Figure 1. Leakage Current Measurement 1µF LOGIC INPUT 5% t ON 5% t OFF +1V LOGIC INPUT _ EN_/SEL B_/COM R L V OUT SWITCH OUTPUT (V OUT ).9 x V OUT.1 x V OUT Figure 2. Switching Time 4

5 // Test Circuits/Timing Diagrams (continued) 1µF +1V LOGIC INPUT 1 2 SEL COM R L 1kI C L V OUT LOGIC INPUT V SWITCH OUTPUT (V OUT ) 5%.8 x V OUT C L INCLUDES FIXTURE ND STRY CPCITNCE. t BBM Figure 3. Break-Before-Make 1µF OFF-ISOLTION = 2LOG V B_/COM V B_/COM NLYZER SIGNL GENERTOR SWITCH OPEN EN_/SEL R L C L Figure 4. Off-Isolation 5

6 // Test Circuits/Timing Diagrams (continued) 1µF CROSSTLK = 2LOG V COM V 2 2 NLYZER COM R L C L SIGNL GENERTOR 1 SEL 5I Figure 5. Crosstalk 1µF EN_/SEL _ V IN NETWORK NLYZER R S R S V IN ON-LOSS = 2LOG V OUT V IN B_/COM V OUT MES REF R L R L Figure 6. Insertion Loss 6

7 // Test Circuits/Timing Diagrams (continued) 1µF _ LOGIC INPUT V OFF ON OFF LOGIC INPUT EN_/SEL B_/COM V OUT C L = 1nF SWITCH OUTPUT (V OUT ) DV OUT Q = C L x DV OUT Figure 7. Charge Injection Typical Operating Characteristics (T = +25 C, unless otherwise noted.) ON-RESISTNCE vs. V B_/COM = 3.3V, I B_ = 25m (), I B = 5m () toc ON-RESISTNCE vs. V COM = 5V, I B_ = 25m (), I B = 5m () toc ON-RESISTNCE vs. TEMPERTURE () = 5V, I B = 5m toc3 RON (I) RON (I) RON (I) T = +85 C T = +25 C V B_/COM (V) V COM (V).3 T = -4 C V COM (V) 7

8 (T = +25 C, unless otherwise noted.) // Typical Operating Characteristics (continued) RON (I) ON-RESISTNCE vs. V COM () = 5V, I B_ = 25m T = +85 C T = +25 C T = -4 C toc4 LEKGE CURRENT (n) LEKGE CURRENT vs. TEMPERTURE () ON-LEKGE OFF-LEKGE toc5 LEKGE CURRENT (n) LEKGE CURRENT vs. TEMPERTURE () OFF-LEKGE ON-LEKGE toc V COM (V) TEMPERTURE ( C) TEMPERTURE ( C) CHRGE INJECTION (pc) CHRGE INJECTION vs. V B T = +85 C T = +25 C 1 8 T = -4 C V B (V) toc7 SUPPLY CURRENT (m) SUPPLY CURRENT vs. TEMPERTURE 5. V EN = () TEMPERTURE ( C) toc8-2 CROSSTLK vs. FREQUENCY toc9-2 OFF-ISOLTION vs. FREQUENCY toc1 CROSSTLK (db) -4-6 OFF-ISOLTION (db) FREQUENCY (MHz) FREQUENCY (MHz) 8

9 (T = +25 C, unless otherwise noted.) // Typical Operating Characteristics (continued) INSERTION LOSS (db) INSERTION LOSS vs. FREQUENCY, R L = 5I FREQUENCY (MHz) toc11 THD+N (%) THD+N vs. FREQUENCY FREQUENCY (khz) toc12-2 PSRR vs. FREQUENCY toc TURN-ON/OFF TIME vs. V B_/COM toc14 PSRR (db) -4-6 TURN-ON/OFF TIME (µs) 3 2 t OFF t ON FREQUENCY (khz) V B_/COM (V) -2 CHRGE-PUMP NOISE (SWITCHES DISBLED) toc15-2 CHRGE-PUMP NOISE (SWITCH ENBLED) toc16 MGNITUDE (dbm) MGNITUDE (dbm) FREQUENCY (MHz) FREQUENCY (MHz) 9

10 // Pin Configurations TOP VIEW EN N.C. V P EN1 EN2 1 V P 2 SEL 1 V P *EP + *EP + *EP V N B B1 V N 5 B V N COM TDFN *CONNECT EXPOSED PD (EP) TO V N. Pin Description PIN NME FUNCTION Positive-Supply Voltage Input. Bypass to with a 1FF ceramic capacitor placed as close as possible to the device Ground V N Negative Voltage Output. Bypass V N to with a.1ff, 5V ceramic capacitor placed as close as possible to the device. 4 B nalog Switch Common Terminal 4 COM nalog Switch Common Terminal 5 nalog Switch Normally Open Terminal V P Positive Voltage Output. Bypass V P to with a.1ff, 5V ceramic capacitor placed as close as possible to the device. 7 N.C. No Connection. Leave unconnected. 8 EN Switch Control Input. Drive EN high to close the switch or drive EN low to open the switch nalog Switch 1 Normally Closed Terminal 1

11 // Pin Description (continued) PIN NME 3 B1 nalog Switch 1 Common Terminal FUNCTION nalog Switch 2 Normally Open Terminal 5 B2 nalog Switch 2 Common Terminal 1 EN1 9 EN2 8 SEL EP Switch 1 Control Input. Drive EN1 high to open switch 1 or drive EN1 low to close switch 1. Switch 2 Control Input. Drive EN2 high to close switch 2 or drive EN2 low to open switch 2. Switch Control Input. Drive SEL low to connect the COM terminal to 1 or drive SEL high to connect the COM terminal to 2. Exposed Pad. Connect EP to V N. EP is not intended as an electrical connection. Detailed Description The // are analog switches capable of handling signals above and below their rails. These devices operate from a single +3.V to +5.5V supply and support signals in the -25V to +25V range. The low on-resistance and high bandwidth allow for use in digital- and analog-signal switching applications. Integrated Bias Generation The // contain a total of three charge pumps to generate bias voltages for the internal switches: a 5V regulated charge pump, a positive high-voltage (+35V) charge pump, and a negative high-voltage (-27V) charge pump. When V DD is above 4.7V (typ), the 5V regulated charge pump is bypassed, and V DD provides the input for the high-voltage charge pumps, reducing overall supply current. n external.1µf capacitor is required for each high-voltage charge pump between V P /V N and. nalog Signal Range The devices switch signals in the range from -25V to +25V that are above and below their rails. The on-resistance for these devices exhibit a high degree of flatness of 2.4mI ( typ) and 5.1mI (/ typ) over the whole input voltage range of -25V to +25V. The analog switches allow bidirectional current flow, so, 1, 2, B, B1, B2, and COM can be used as either inputs or outputs. Bypass Capacitors Bias stabilizing capacitors are required on the V P and V N pins. 1FF ceramic capacitors are suggested for effective operation. V P and V N are not intended as a power supply for other circuitry. pplications Information Nonpowered Condition The // can tolerate input voltages on the, B, or COM pins in the ±25V range when it is not powered. When V DD = V, the DC input leakage current into the, B, or COM pins is typically below 1µ. Some devices can have a larger leakage current up to the m range due to technology spread. With V DD not powered, internal diodes between the analog pins and the V P and V N charge up the external capacitors on V P and V N when positive and/or negative voltages are applied to these pins. This causes transient input current flow. Large dv/dt on the inputs causes large capacitive charging currents, which have to be limited to 3m to avoid destroying the internal diodes. Hence, the 1nF capacitors on V P and V N, the dv/dt must be limited to 3V/µs. Once the capacitors reach their final voltage, the input current decays to the leakage current levels mentioned above. 11

12 // Differential Termination Resistor Switch The can be used to switch a differential termination resistor in or out. In RS-485 and CN applications, both ends of high-speed transmission lines require termination. Figures 8 and 9 show an application of RS-485 and CN termination using two equal resistors. These switches support RS-485 s high -7V to +12V commonmode range. In RS-232/RS-485 multiprotocol applications, the can be used for switching in the line-terminating resistors for RS-485 usage, and can disable the termination resistor for RS-232 operation, as shown in Figure 1. The is ideal for switching in fail-safe biasing resistors in RS-485 applications, as shown in Figures 11 and 12. udio mplifier Switch The is used for selecting between audio amplifier sources to drive loudspeaker applications (Figures 13 and 14.) R T /2 MX1484 TERMINTION CONTROL EN B R T /2 Figure 8. RS-485 Termination Switch CNH R T /2 R T /2 EN EN MX351 CTRL CTRL B B MX351 R T/2 R T/2 CNL Figure 9. CN Termination Switch 12

13 // R T /2 MX316 RS-485/ RS-232 CONTROL EN B R T /2 B Figure 1. Multiprotocol Termination Switch R PU 1 R T B1 B2 EN1 EN2 CONTROL 2 RS-485 TRNSCEIVER R PD Figure 11. Pullup and Pulldown Resistance Switch 13

14 // R PU 1 B1 RS-485 TRNSCEIVER CONTROL EN1 EN2 2 B2 R T R PD Figure 12. Fail-Safe Biasing Network Switch UDIO MPLIFIER COM UDIO MPLIFIER SEL COM UDIO MPLIFIER 2 CONTROL SEL UDIO MPLIFIER SEL COM CONTROL Figure 13. Single-Ended mplifier Switching Figure 14. Differential mplifier Switching 14

15 // Ordering Information/Selector Guide PRT TEMP RNGE PIN-PCKGE FUNCTION R ON (MX) (I) ET+ -4NC to +85NC 8 TDFN-EP* 1 x SPST 1 ETB+ -4NC to +85NC 1 TDFN-EP* 2 x SPST 2 ET+ -4NC to +85NC 8 TDFN-EP* 1 x SPDT 2 +Denotes a lead(pb)-free/rohs-compliant package. *EP = Exposed pad. Chip Information Package Information PROCESS: BiCMOS For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PCKGE TYPE PCKGE CODE OUTLINE NO. LND PTTERN NO. 8 TDFN T TDFN T

16 // Revision History REVISION NUMBER REVISION DTE DESCRIPTION PGES CHNGED 9/11 Initial release 1 8/12 Updated Electrical Characteristics table, updated Figures 1 7, added Switch Enabled and Switch Disabled figures, updated Pin Configuration table, added Integrated Bias Generation and Nonpowered Condition sections 3 7, 9 11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 16 Rio Robles, San Jose, C US The Maxim logo and are trademarks of Products, Inc.