36-Mbit QDR-II SRAM 2-Word Burst Architecture

Transcription

1 36-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description Separate Independent Read and Write data ports Supports concurrent transactions 2-MHz clock for high bandwidth 2-Word Burst on all accesses Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 4 2 MHz Two input clocks ( and ) for precise DDR timing SRAM uses rising edges only Two output clocks ( and ) accounts for clock skew and flight time mismatching Echo clocks (Q and Q) simplify data capture in high-speed systems Single multiplexed address input bus latches address inputs for both Read and Write ports Separate Port Selects for depth expansion Synchronous internally self-timed writes Available in x8, x9, x8, and x36 configurations Full data coherency, providing most current data ore V DD =.8V (±.V); I/O V DDQ =.4V to V DD mm.-mm pitch FBGA package, 65-ball ( 5 matrix) Variable drive HSTL output buffers JTAG 49. compatible test access port Delay Lock Loop (DLL) for accurate data placement onfigurations 4M x 8 4M x 9 2M x 8 M x 36 Selection Guide The,,, and are.8v Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to turn-around the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the clock and the Write address is latched on the rising edge of the clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words () or 9-bit words () or 8-bit words () or 36-bit words () that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks ( and and and ), memory bandwidth is maximized while simplifying system design by eliminating bus turn-arounds. Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the or input clocks. All data outputs pass through output registers controlled by the or (or or in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. 25 MHz 2 MHz 67 MHz Unit Maximum Operating Frequency MHz Maximum Operating urrent TBD TBD TBD ma Shaded areas contain advance information. Please contact your local ypress Sales representative for availability of these parts. ypress Semiconductor orporation 39 North First Street San Jose, A Document #: Rev. ** Revised July 6, 24

2 Logic Block Diagram () D [7:] 8 A (2:) 2 DOFF Address Register L Gen. Write Add. Decode Write Reg 2M x 8 Array Write Reg 2M x 8 Array Read Data Read Add. Decode Address Register ontrol Logic 2 RPS A (2:) Q V REF WPS NWS [:] ontrol Logic Q [7:] Q Logic Block Diagram () D [8:] 9 A (2:) 2 DOFF Address Register L Gen. Write Add. Decode Write Reg 2M x 9 Array Write Reg 2M x 9 Array Read Data Read Add. Decode Address Register ontrol Logic 2 RPS A (2:) Q V REF WPS BWS [] ontrol Logic Q [8:] Q Document #: Rev. ** Page 2 of 23

3 Logic Block Diagram () D [7:] 8 A (9:) 2 DOFF Address Register L Gen. Write Add. Decode Write Reg M x 8 Array Write Reg M x 8 Array Read Data Read Add. Decode Address Register ontrol Logic 2 RPS A (9:) Q V REF WPS BWS [:] ontrol Logic Q [7:] Q Logic Block Diagram () D [35:] 36 A (8:) 9 DOFF Address Register L Gen. Write Add. Decode Write Reg 52 x 36 Array Write Reg 52 x 36 Array Read Data Read Add. Decode Address Register ontrol Logic 9 RPS A (8:) Q V REF WPS BWS [3:] ontrol Logic Q [35:] Q Document #: Rev. ** Page 3 of 23

4 Pin onfigurations (4M 8) 5 7 FBGA A B D E F G H J L M N P R Q DOFF TDO /72M A WPS NWS /44M A /288M NWS V SS A A A D4 V SS V SS V SS V SS Q4 V DDQ V SS V SS V SS V DDQ V DD V SS V DD D5 Q5 V DDQ V DD V SS V DD V REF V DDQ V DDQ V DD V SS V DD V DDQ V DD V SS V DD V DDQ V DD V SS V DD Q6 D6 V DDQ V SS V SS V SS V SS V SS V SS V SS D7 V SS A A A Q7 A A A T A A A A 8 9 RPS A A Q A Q3 V SS D3 V SS V DDQ D2 Q2 V DDQ V DDQ V DDQ V DDQ V REF ZQ V DDQ Q D V DDQ V DDQ Q V SS D V SS A A A TMS TDI (4M 9) 5 Balls (5 7 FBGA) A B D E F G H J L M N P R Q DOFF TDO /72M A WPS /44M A /288M BWS V SS A A A D5 V SS V SS V SS V SS Q5 V DDQ V SS V SS V SS V DDQ V DD V SS V DD D6 Q6 V DDQ V DD V SS V DD V REF V DDQ V DDQ V DD V SS V DD V DDQ V DD V SS V DD V DDQ V DD V SS V DD Q7 D7 V DDQ V SS V SS V SS V SS V SS V SS V SS D8 V SS A A A Q8 A A A T A A A A 8 9 RPS A A Q A Q4 V SS D4 V SS V DDQ D3 Q3 V DDQ V DDQ V DDQ V DDQ V REF ZQ V DDQ Q2 D2 V DDQ V DDQ Q V SS D V SS A D Q A A TMS TDI Document #: Rev. ** Page 4 of 23

5 Pin onfigurations (continued) A B D E F G H J L M N P R A B D E F G H J L M N P R Q DOFF TDO Q Q27 D27 D28 Q29 Q3 D3 DOFF D3 Q32 Q33 D33 D34 Q35 TDO (2M 8) 5 7 FBGA /44M A WPS BWS /288M RPS A /72M Q Q9 D9 A BWS A Q8 D V SS A A A V SS Q7 D8 D Q V SS V SS V SS V SS V SS D7 Q V DDQ V SS V SS V SS V DDQ D6 Q6 Q2 D2 V DDQ V DD V SS V DD V DDQ Q5 D3 Q3 V DDQ V DD V SS V DD V DDQ D5 V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ D4 V DDQ V DD V SS V DD V DDQ Q4 D4 Q4 V DDQ V DD V SS V DD V DDQ D3 Q3 Q5 D5 V DDQ V SS V SS V SS V DDQ Q2 D6 V SS V SS V SS V SS V SS Q D2 D7 Q6 V SS A A A V SS D Q7 A A A A D Q T A A A A A A TMS TDI (M 36) 5 7 FBGA /288M /72M WPS BWS 2 BWS Q8 D8 A BWS 3 BWS Q28 D9 V SS A A A D2 Q9 V SS V SS V SS V SS D29 Q2 V DDQ V SS V SS V SS Q2 D2 V DDQ V DD V SS V DD D22 Q22 V DDQ V DD V SS V DD V REF V DDQ V DDQ V DD V SS V DD Q3 D23 V DDQ V DD V SS V DD D32 Q23 V DDQ V DD V SS V DD Q24 D24 V DDQ V SS V SS V SS Q34 D25 V SS V SS V SS V SS D26 Q25 V SS A A A D35 Q26 A A A T A A A A 8 9 RPS A /44M Q A D7 Q7 Q8 V SS D6 Q7 D8 V SS Q6 D5 D7 V DDQ Q5 D6 Q6 V DDQ D4 Q4 Q5 V DDQ Q3 D3 D5 V DDQ VDDQ V REF ZQ V DDQ D2 Q4 D4 V DDQ Q2 D3 Q3 V DDQ D Q Q2 V SS D Q D2 V SS Q D9 D A Q9 D Q A A TMS TDI Document #: Rev. ** Page 5 of 23

6 Pin Definitions D [x:] WPS Pin Name I/O Pin Description NWS, NWS BWS, BWS, BWS 2, BWS 3 A Q [x:] RPS Input- Synchronous Input- Synchronous Input- Synchronous Input- Synchronous Outputs- Synchronous Input- Synchronous Input- lock Data input signals, sampled on the rising edge of and clocks during valid write operations. - D [7:] - D [8:] - D [7:] - D [35:] Write Port Select, active LOW. Sampled on the rising edge of the clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D [x:] to be ignored. Nibble Write Select, active LOW. ( Only) Sampled on the rising edge of the and clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations.nibbles not written remain unaltered. NWS controls D [3:] and NWS controls D [7:4]. All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device. Byte Write Select,, 2 and 3 active LOW. Sampled on the rising edge of the and clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. BWS controls D [8:] BWS controls D [8:], BWS controls D [7:9]. BWS controls D [8:], BWS controls D [7:9],BWS 2 controls D [26:8] and BWS 3 controls D [35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the (Read address) and (Write address) clocks during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for, 4M x 9 (2 arrays each of 2M x 9) for, 2M x 8 (2 arrays each of M x 8) for and M x 36 (2 arrays each of 52 x 36) for. Therefore, only 2 address inputs are needed to access the entire memory array of and, 2 address inputs for and 9 address inputs for. These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the and clocks during Read operations or and when in single clock mode. When the Read port is deselected, Q [x:] are automatically three-stated. Q [7:] Q [8:] Q [7:] Q [35:] Read Port Select, active LOW. Sampled on the rising edge of Positive Input lock (). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the clock. Each read access consists of a burst of two sequential transfers. Positive Output lock Input. is used in conjunction with to clock out the Read data from the device. and can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Input-lock Negative Output lock Input. is used in conjunction with to clock out the Read data from the device. and can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Input-lock Positive Input lock Input. The rising edge of is used to capture synchronous inputs to the device and to drive out data through Q [x:] when in single clock mode. All accesses are initiated on the rising edge of. Document #: Rev. ** Page 6 of 23

7 Pin Definitions (continued) Input-lock Negative Input lock Input. is used to capture synchronous inputs being presented to the device and to drive out data through Q [x:] when in single clock mode. Q Echo lock Q is referenced with respect to. This is a free running clock and is synchronized to the output clock () of the QDR-II. In the single clock mode, Q is generated with respect to. The timings for the echo clocks are shown in the A Timing table. Q Echo lock Q is referenced with respect to. This is a free running clock and is synchronized to the output clock () of the QDR-II. In the single clock mode, Q is generated with respect to. The timings for the echo clocks are shown in the A Timing table. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q, Q, and Q [x:] output impedance are set to.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input DLL Turn Off, active LOW. onnecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, DLL Operation in the QDR-II. TDO Output TDO for JTAG. T Input T pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. N/A Not connected to the die. an be tied to any voltage level. /72M N/A Not connected to the die. an be tied to any voltage level. /44M N/A Not connected to the die. an be tied to any voltage level. /288M N/A Not connected to the die. an be tied to any voltage level. V REF Pin Name I/O Pin Description Input- Reference Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as A measurement points. V DD Power Supply Power supply inputs to the core of the device. V SS Ground Ground for the device. V DDQ Power Supply Power supply inputs for the outputs of the device. Functional Overview The,, and are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to turn-around the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 8-bit data transfers in the case of, two 9-bit data transfers in the case of,two 8-bit data transfers in the case of and two 36-bit data transfers in the case of, in one clock cycle. Accesses for both ports are initiated on the rising edge of the positive Input lock (). All synchronous input timings are referenced from the rising edge of the input clocks ( and ) and all output timings are referenced to the rising edge of output clocks ( and or and when in single clock mode). All synchronous data inputs (D [x:] ) inputs pass through input registers controlled by the input clocks ( and ). All synchronous data outputs (Q [x:] ) outputs pass through output registers controlled by the rising edge of the output clocks ( and or and when in single clock mode). All synchronous control (RPS, WPS, BWS [x:] ) inputs pass through input registers controlled by the rising edge of the input clocks ( and ). is described in the following sections. The same basic descriptions apply to and. Read Operations The is organized internally as 2 arrays of Mx8. Accesses are completed in a burst of two sequential 8-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input lock (). The address is latched on the rising edge of the lock. The address presented to Address inputs is stored in the Read Document #: Rev. ** Page 7 of 23

8 address register. Following the next clock rise the corresponding lowest order 8-bit word of data is driven onto the Q [7:] using as the output timing reference. On the subsequent rising edge of, the next 8-bit data word is driven onto the Q [7:]. The requested data will be valid.45 ns from the rising edge of the output clock ( and or and when in single clock mode). Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the Output locks (/). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input lock (). On the same clock rise, the data presented to D [7:] is latched and stored into the lower 8-bit Write Data register provided BWS [:] are both asserted active. On the subsequent rising edge of the Negative Input lock (), the address is latched and the information presented to D [7:] is stored into the Write Data register provided BWS [:] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS and BWS, which are sampled with each 8-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single lock Mode The can be used with a single clock that controls both the input and output registers. In this mode, the device will recognize only a single pair of input clocks ( and ) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the / and / clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie and HIGH at power on. This function is a strap option and not alterable during device operation. oncurrent Transactions The Read and Write ports on the operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous clock rise. Depth Expansion The has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input lock only (). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±5% is between 75Ω and 35Ω, with V DDQ =.5V.The output impedance is adjusted every 24 cycles upon power-up to account for drifts in supply voltage and temperature. Echo locks Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. Q is referenced with respect to and Q is referenced with respect to. These are free-running clocks and are synchronized to the output clock (/) of the QDR-II. In the single clock mode, Q is generated with respect to and Q is generated with respect to. The timings for the echo clocks are shown in the A Timing table. DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 8 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. The DLL can also be reset by slowing the cycle time of input clocks and to greater than 3 ns. Document #: Rev. ** Page 8 of 23

9 Application Example [] Vt R SRAM # R = 25οηµσ SRAM #4 ZQ R W B Q/Q# R W B PS D PS W PS# PS# WS# Q D S# A # # # # A # ZQ Q/Q# Q # R = 25οηµσ BUS MASTER (PU or ASI) DATA IN DATA OUT Address RPS# WPS# BWS# LIN/LIN# Source Source # R Vt Vt Delayed Delayed # R R = 5οηµσ Vt = Vddq/2 Truth Table [2, 3, 4, 5, 6, 7] Operation RPS WPS DQ DQ Write ycle: Load address on the rising edge of clock; input write data on and rising edges. L-H X L D(A + )at (t) D(A + ) at (t) Read ycle: Load address on the rising edge of clock; wait one and a half cycle; read data on and rising edges. L-H L X Q(A + ) at (t + ) Q(A + ) at (t + 2) NOP: No Operation L-H H H D = X Q = High-Z D = X Q = High-Z Standby: lock Stopped Stopped X X Previous State Previous State Write ycle Descriptions ( and ) [2, 8] BWS /NWS BWS / NWS omments L L L-H During the Data portion of a Write sequence: both nibbles (D [7:] ) are written into the device, both bytes (D [7:] ) are written into the device. L L L-H During the Data portion of a Write sequence: both nibbles (D [7:] ) are written into the device, both bytes (D [7:] ) are written into the device. L H L-H During the Data portion of a Write sequence: only the lower nibble (D [3:] ) is written into the device. D [7:4] will remain unaltered, only the lower byte (D [8:] ) is written into the device. D [7:9] will remain unaltered. Notes:. The above application shows four QDR-II being used. 2. X = Don't are, H = Logic HIGH, L= Logic LOW, represents rising edge. 3. Device will power-up deselected and the outputs in a three-state condition. 4. A represents address location latched by the devices when transaction was initiated. A +, A + represents the internal address sequence in the burst. 5. t represents the cycle at which a Read/Write operation is started. t + and t + 2 are the first and second clock cycles respectively succeeding the t clock cycle. 6. Data inputs are registered at and rising edges. Data outputs are delivered on and rising edges, except when in single clock mode. 7. It is recommended that = and = = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Assumes a Write cycle was initiated per the Write Port ycle Description Truth Table. NWS, NWS, BWS, BWS, BWS 2 and BWS 3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document #: Rev. ** Page 9 of 23

10 Write ycle Descriptions ( and ) (continued)[2, 8] BWS /NWS BWS / NWS omments L H L-H During the Data portion of a Write sequence: only the lower nibble (D [3:] ) is written into the device. D [7:4] will remain unaltered, only the lower byte (D [8:] ) is written into the device. D [7:9] will remain unaltered. H L L-H During the Data portion of a Write sequence: only the upper nibble (D [7:4] ) is written into the device. D [3:] will remain unaltered, only the upper byte (D [7:9] ) is written into the device. D [8:] will remain unaltered. H L L-H During the Data portion of a Write sequence: only the upper nibble (D [7:4] ) is written into the device. D [3:] will remain unaltered, only the upper byte (D [7:9] ) is written into the device. D [8:] will remain unaltered. H H L-H No data is written into the devices during this portion of a Write operation. H H L-H No data is written into the devices during this portion of a Write operation. Write ycle Descriptions () [2, 8] BWS BWS BWS 2 BWS 3 omments L L L L L-H - During the Data portion of a Write sequence, all four bytes (D [35:] ) are written into the device. L L L L - L-H During the Data portion of a Write sequence, all four bytes (D [35:] ) are written into the device. L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D [8:] ) is written into the device. D [35:9] will remain unaltered. L H H H - L-H During the Data portion of a Write sequence, only the lower byte (D [8:] ) is written into the device. D [35:9] will remain unaltered. H L H H L-H - During the Data portion of a Write sequence, only the byte (D [7:9] ) is written into the device. D [8:] and D [35:8] will remain unaltered. H L H H - L-H During the Data portion of a Write sequence, only the byte (D [7:9] ) is written into the device. D [8:] and D [35:8] will remain unaltered. H H L H L-H - During the Data portion of a Write sequence, only the byte (D [26:8] ) is written into the device. D [7:] and D [35:27] will remain unaltered. H H L H - L-H During the Data portion of a Write sequence, only the byte (D [26:8] ) is written into the device. D [7:] and D [35:27] will remain unaltered. H H H L L-H During the Data portion of a Write sequence, only the byte (D [35:27] ) is written into the device. D [26:] will remain unaltered. H H H L - L-H During the Data portion of a Write sequence, only the byte (D [35:27] ) is written into the device. D [26:] will remain unaltered. H H H H L-H - No data is written into the device during this portion of a Write operation. H H H H - L-H No data is written into the device during this portion of a Write operation. Write ycle Descriptions () BWS omments L L-H During the Data portion of a Write sequence: the single byte (D [8:] ) is written into the device L L-H During the Data portion of a Write sequence: the single byte (D [8:] ) is written into the device, H L-H No data is written into the devices during this portion of a Write operation. H L-H No data is written into the devices during this portion of a Write operation. Document #: Rev. ** Page of 23

11 Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature to +5 Ambient Temperature with Power Applied... to +85 Supply Voltage on V DD Relative to GND....5V to +2.9V D Voltage Applied to Outputs in High-Z State....5V to V DDQ +.3V D Input Voltage [2]....5V to V DDQ +.3V Electrical haracteristics Over the Operating Range [9, 3] urrent into Outputs (LOW)... 2 ma Static Discharge Voltage... > 2V (per MIL-STD-883, Method 35) Latch-up urrent... > 2 ma Operating Range Range Ambient Temperature (T A ) V DD [3] V DDQ [3] om l to +7.8 ±. V.4V to V DD D Electrical haracteristics Over the Operating Range Parameter Description Test onditions Min. Typ. Max. Unit V DD Power Supply Voltage V V DDQ I/O Supply Voltage.4.5 V DD V V OH Output HIGH Voltage [] V DDQ /2.2 V DDQ /2 +.2 V V OL Output LOW Voltage [] V DDQ /2.2 V DDQ /2 +.2 V V OH(LOW) Output HIGH Voltage I OH =. ma, Nominal Impedance V DDQ.2 V DDQ V V OL(LOW) Output LOW Voltage I OL =. ma, Nominal Impedance V SS.2 V V IH Input HIGH Voltage [2] V REF +. V DDQ +.3 V V IL Input LOW Voltage [2].3 V REF. V I X Input Load urrent GND V I V DDQ 5 5 µa I OZ Output Leakage urrent GND V I V DDQ, Output Disabled 5 5 µa V REF Input Reference Voltage [4] Typical Value =.75V V I DD V DD Operating Supply V DD = Max., I OUT = 67 MHz TBD ma ma, f = f MAX = /t Y 2 MHz TBD ma 25 MHz TBD ma I SB Automatic Power-down Max. V DD, Both Ports 67 MHz TBD ma urrent Deselected, V IN V IH 2 MHz TBD ma or V IN V IL f = f MAX = /t Y, Inputs Static 25 MHz TBD ma Shaded areas contain advance information. Please contact your local ypress Sales representative for availability of these parts. A Input Requirements Over the Operating Range Parameter Description Test onditions Min. Typ. Max. Unit V IH Input High (Logic ) Voltage V REF +.2 V V IL Input Low (Logic ) Voltage V REF -.2 V Notes: 9. All voltage referenced to Ground.. Output are impedance controlled. I OH = (V DDQ /2)/(RQ/5) for values of 75Ω <= RQ <= 35Ωs.. Output are impedance controlled. I OL = (V DDQ /2)/(RQ/5) for values of 75Ω <= RQ <= 35Ω. 2. Overshoot: V IH (A) < V DDQ +.85V (Pulse width less than t Y /2), Undershoot: V IL (A) >.5V (Pulse width less than t Y /2). 3. Power-up: Assumes a linear ramp from V to V DD (min.) within 2 ms. During this time V IH < V DD and V DDQ < V DD. 4. V REF (Min.) =.68V or.46v DDQ, whichever is larger, V REF (Max.) =.95V or.54v DDQ, whichever is smaller. Document #: Rev. ** Page of 23

12 Switching haracteristics Over the Operating Range [5,6] ypress onsortium 25 MHz 2 MHz 67 MHz Parameter Parameter Description Min. Max. Min. Max. Min. Max. Unit t POWER V DD (Typical) to the first Access [9] ms t Y t HH lock and lock ycle Time ns t H t HL Input lock (/ and /) HIGH ns t L t LH Input lock (/ and /) LOW ns t HH t HH lock Rise to lock Rise and to Rise ns (rising edge to rising edge) t HH t HH / lock Rise to / lock Rise (rising ns edge to rising edge) Set-up Times t SA t SA Address Set-up to lock Rise ns t S t S ontrol Set-up to lock (, ) Rise (RPS, WPS) ns t SDDR t S Double Data Rate ontrol Set-up to lock (, ns ) Rise (BWS, BWS, BWS 3, BWS 4 ) t SD t SD D [X:] Set-up to lock ( and ) Rise ns Hold Times t HA t HA Address Hold after lock ( and ) Rise ns t H t H ontrol Hold after lock ( and ) Rise (RPS, ns WPS) t HDDR t H Double Data Rate ontrol Hold after lock ( ns and ) Rise (BWS, BWS, BWS 3, BWS 4 ) t HD t HD D [X:] Hold after lock ( and ) Rise ns Output Times t O t HQV / lock Rise (or / in Single lock Mode) ns to Data Valid t DOH t HQX Data Output Hold after Output / lock ns Rise (Active to Active) t QO t HQV / lock Rise to Echo lock Valid ns t QOH t HQX Echo lock Hold after / lock Rise ns t QD t QHQV Echo lock High to Data Valid ns t QDOH t QHQX Echo lock High to Data Invalid ns t HZ t HZ lock ( and ) Rise to High-Z (Active to ns High-Z) [7,8] t LZ t LZ lock ( and ) Rise to Low-Z [7,8] ns DLL Timing t Var t Var lock Phase Jitter ns t lock t lock DLL Lock Time (, ) cycles t Reset t Reset Static to DLL Reset ns Shaded areas contain advance information. Please contact your local ypress Sales representative for availability of these parts. Notes: 5. All devices can operate at clock frequencies as low as 9 MHz. When a part with a maximum frequency above 33 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 6. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of.75v, Vref =.75V, RQ = 25Ω, V DDQ =.5V, input pulse levels of.25v to.25v, and output loading of the specified I OL /I OH and load capacitance shown in (a) of A Test Loads. 7. t HZ, t LZ, are specified with a load capacitance of 5 pf as in part (b) of A Test Loads. Transition is measured ± mv from steady-state voltage. 8. At any given voltage and temperature t HZ is less than t LZ and t HZ less than t O. 9. This part has a voltage regulator internally; t POWER is the time that the power needs to be supplied above V DD minimum initially before a read or write operation can be initiated. Document #: Rev. ** Page 2 of 23

13 Thermal Resistance [2] Parameter Description Test onditions 65 FBGA Package Unit Θ JA Thermal Resistance TBD /W (Junction to Ambient) Θ J apacitance [2] Thermal Resistance (Junction to ase) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD5. Parameter Description Test onditions Max. Unit IN Input apacitance T A = 25, f = MHz, TBD pf V DD =.8V L lock Input apacitance TBD pf V DDQ =.5V O Output apacitance TBD pf A Test Loads and Waveforms V REF =.75V TBD /W V REF OUTPUT Device Under Test ZQ (a).75v Z = 5Ω RQ = 25Ω R L = 5Ω V REF =.75V V REF OUTPUT Device Under ZQ Test ILUDING JIG AND SOPE.75V RQ = 25Ω (b) R = 5Ω 5pF.25V [2] ALL INPUT PULSES.25V.75V Slew Rate = 2V / ns Note: 2. Tested initially and after any design or process change that may affect these parameters. Document #: Rev. ** Page 3 of 23

14 Switching Waveforms [2, 22, 23] Read/Write/Deselect Sequence READ WRITE READ WRITE READ WRITE NOP WRITE NOP t H t L t Y t HH RPS ts t H WPS A A A A2 A3 A4 A5 A6 t SA t HA t SA t HA D D D D3 D3 D5 D5 D6 D6 t SD t HD t SD t HD Q Q Q Q2 Q2 Q4 Q4 t LZ t DOH t DOH t QD t HZ t HH t L t O t O t H t HH t HH t Y t QO t QOH Q t QO t QOH Q DON T ARE UNDEFINED Notes: 2. Q refers to output from address A. Q refers to output from the next internal burst address following A, i.e., A Output are disabled (High-Z) one clock cycle after a NOP. 23. In this example, if address A2 = A,then data Q2 = D and Q2 = D. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document #: Rev. ** Page 4 of 23

15 IEEE 49. Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard # The TAP operates using JEDE standard.8v I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, T must be tied LOW (V SS ) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to V DD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port Test lock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of T. All outputs are driven from the falling edge of T. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of T. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP ontroller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of T. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of T. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of T. Data is output on the TDO pin on the falling edge of T. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in TAP ontroller Block Diagram. Upon power-up, the instruction register is loaded with the IDODE instruction. It is also loaded with the IDODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the apture IR state, the two least significant bits are loaded with a binary pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V SS ) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect () pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the apture-dr state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the apture-dr state when the IDODE command is loaded in the instruction register. The IDODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction ode table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDODE The IDODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDODE instruction Document #: Rev. ** Page 5 of 23

16 is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 49. mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the apture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 2 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the apture-dr state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (t S and t H ). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the and captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-dr controller state. EXTEST OUTPUT BUS THREE-STATE IEEE Standard 49. mandates that the TAP controller be able to put the output bus into a three-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the extest output bus three-state, is latched into the preload register during the Update-DR state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered-up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: Rev. ** Page 6 of 23

17 TAP ontroller State Diagram [24] TEST-LOGI RESET TEST-LOGI/ IDLE SELET DR-SAN SELET IR-SAN APTURE-DR APTURE-IR SHIFT-DR SHIFT-IR EXIT-DR EXIT-IR PAUSE-DR PAUSE-IR EXIT2-DR EXIT2-IR UPDATE-DR UPDATE-IR Note: 24. The / next to each state represents the value at TMS at the rising edge of T. Document #: Rev. ** Page 7 of 23

18 TAP ontroller Block Diagram Bypass Register TDI Selection ircuitry 2 Instruction Register Selection ircuitry TDO Identification Register Boundary Scan Register T TMS TAP ontroller [9, 2, 25] TAP Electrical haracteristics Over the Operating Range Parameter Description Test onditions Min. Max. Unit V OH Output HIGH Voltage I OH = 2. ma.4 V V OH2 Output HIGH Voltage I OH = µa.6 V V OL Output LOW Voltage I OL = 2. ma.4 V V OL2 Output LOW Voltage I OL = µa.2 V V IH Input HIGH Voltage.65V DD V DD +.3 V V IL Input LOW Voltage.3.35V DD V I X Input and OutputLoad urrent GND V I V DD 5 5 µa Notes: 25. These characteristic pertain to the TAP inputs (TMS, T, TDI and TDO). Parallel load levels are specified in the Electrical haracteristics table. Document #: Rev. ** Page 8 of 23

19 TAP A Switching haracteristics Over the Operating Range [26, 27] Parameter Description Min. Max. Unit t TY T lock ycle Time 5 ns t TF T lock Frequency 2 MHz t TH T lock HIGH 4 ns t TL T lock LOW 4 ns Set-up Times t TMSS TMS Set-up to T lock Rise ns t TDIS TDI Set-up to T lock Rise ns t S apture Set-up to T Rise ns Hold Times t TMSH TMS Hold after T lock Rise ns t TDIH TDI Hold after lock Rise ns t H apture Hold after lock Rise ns Output Times t TDOV T lock LOW to TDO Valid 2 ns t TDOX T lock LOW to TDO Invalid ns TAP Timing and Test onditions [27].9V TDO Z = 5Ω 5Ω L = 2 pf V ALL INPUT PULSES.8V.9V t TH t TL GND (a) Test lock T t TMSS t TY t TMSH Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Test Data-Out TDO t TDOV Notes: 26. t S and t H refer to the set-up and hold time requirements of latching data from the boundary scan register. 27. Test conditions are specified using the load in TAP A test conditions. t R /t F = ns. ttdox Document #: Rev. ** Page 9 of 23

20 Identification Register Definitions Instruction Field Revision Number (3:29) ypress Device ID (28:2) ypress JEDE ID (:) ID Register Presence () Scan Register Sizes Value Description Version number. Defines the type of SRAM. Register Name Bit Size Instruction 3 Bypass ID 32 Boundary Scan ells 9 Instruction odes Unique identification of SRAM vendor. Indicates the presence of an ID register. Instruction ode Description EXTEST aptures the Input/Output ring contents. IDODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z aptures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD aptures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED Do Not Use: This instruction is reserved for future use. RESERVED Do Not Use: This instruction is reserved for future use. BYPASS Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Boundary Scan Order Bit # Bump ID 6R 6P 2 6N 3 7P 4 7N 5 7R 6 8R 7 8P 8 9R 9 P P N Boundary Scan Order (continued) Bit # Bump ID 2 9P 3 M 4 N 5 9M 6 9N 7 L 8 M 9 9L 2 L J Document #: Rev. ** Page 2 of 23

21 Boundary Scan Order (continued) Bit # Bump ID J 26 J 27 H 28 G 29 9G 3 F 3 G 32 9F 33 F 34 E 35 E 36 D 37 9E D D 42 B B 45 B 46 A 47 A 48 9A 49 8B A 53 7A 54 7B 55 6B 56 6A 57 5B 58 5A 59 4A B 62 3A 63 2A 64 A 65 2B 66 3B 67 Boundary Scan Order (continued) Bit # Bump ID 68 B 69 3D D E 74 2D 75 2E 76 E 77 2F 78 3F 79 G 8 F 8 3G 82 2G 83 H 84 J 85 2J J L 9 3L 92 M 93 L 94 3N 95 3M 96 N 97 2M 98 3P 99 2N 2P P 2 3R 3 4R 4 4P 5 5P 6 5N 7 5R 8 Internal Document #: Rev. ** Page 2 of 23

22 Ordering Information Speed (MHz) Ordering ode Package Name Package Type Operating Range 25-25BZ BB65E 5 x 7 x.4 mm FBGA ommercial -25BZ -25BZ -25BZ 2-2BZ BB65E 5 x 7x.4 mm FBGA ommercial -2BZ -2BZ -2BZ 67-67BZ BB65E 5 x 7 x.4 mm FBGA ommercial -67BZ -67BZ -67BZ Shaded areas contain advance information. Please contact your local ypress Sales representative for availability of these parts. Package Diagram 65-Ball FBGA (5 x 7 x.4 mm) Pkg. Outline (.5 Ball Dia.) BB65E BOTTOM VIEW PIN ORNER TOP VIEW Ø.5 M PIN ORNER Ø.25 M A B +.4 Ø.5 (65X) A B D E F G. A B D E F G H J 7.±. 4. H J L M 7. L M N P R N P R A ±.5.4±.5.5 B. 5.±..5(4X).36 SEATING PLANE.4 MAX ** QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by ypress, Hitachi, IDT, NE, and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: Rev. ** Page 22 of 23 ypress Semiconductor orporation, 24. The information contained herein is subject to change without notice. ypress Semiconductor orporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a ypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. ypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of ypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies ypress Semiconductor against all charges. ypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with ypress.

23 Document History Page Document Title: /// 36-Mbit QDR-II SRAM 2-Word Burst Architecture Document Number: Orig. of REV. EN No. Issue Date hange Description of hange ** See EN SYT New Data Sheet Document #: Rev. ** Page 23 of 23