Select the single most appropriate response for each question.

Transcription

1 ECE 362 Final Lab Practical Practice Exam / Solution PART 1: Multiple Choice Select the single most appropriate response for each question. Note that none of the above MAY be a VALID ANSWER. (Solution at end) (1) On the 9S12C, the purpose of the PLL (phase locked loop) is to: (A) generate the OSCCLK frequency. (B) monitor the phase of the BUS CLOCK (C) multiply the BUS CLOCK frequency (D) generate periodic interrupts in phase with the bus clock (2) Based on the RTI reference chart (posted on the Homework page), the largest period with the minimum error rate can be obtained by initializing the RTICTL register to: (A) $10 (B) $13 (C) $28 (D) $38 (3) Based on the RTI reference chart (posted on the Homework page), the largest period with the minimum error rate can be obtained by initializing the RTICTL register as determined in Question 2, above, and using an RTICNT of: (A) 217 (B) 279 (C) 434 (D) 7812 (4) The resolution of an N-bit ATD is: (A) N 2 / (VRH VRL) (B) (VRH VRL) / N 2 (C) 2 N / (VRH VRL) (D) (VRH VRL) / 2 N (5) The purpose of an anti-alias filter is: (A) to prevent input signals greater than Fs/2 from folding back into the baseband (B) to remove replicas of the baseband spectrum that appear in the output spectrum centered at integer multiples of Fs (C) to improve the ATD s SQNR (D) to improve the ATD s resolution

2 ECE 362 Final Lab Practical Practice Exam / Solution (6) For an ATD operated at a sampling frequency of 20 KHz, a combination of pure tones (sine waves) at frequencies of 8 KHz, 10 KHz, and 11 KHz would produce the following spectral components in the digitized output: (A) 8 KHz, 10 KHz, and 11 KHz (B) 8 KHz, 10 KHz, and 22 KHz (C) 8 KHz, 9 KHz, and 10 KHz (D) 4 KHz, 5 KHz, and 5.5 KHz (7) The final sample time of the ATD is: (A) the amount of time the input is integrated (sampled) (B) the total amount of time to perform the conversion (C) the amount of time needed to perform the successive approximation algorithm (D) the total amount of time needed to perform the programmed sequence of conversions (8) Given that the ATD is supplied with references voltages of VRH = 4.0 volts and VRL = 0.0 volts, the output code produced in response to an input voltage of 3.5 VDC is: (A) $B0 (B) $C0 (C) $D0 (D) $E0 (9) The fast flag clear mode is most useful in applications that operate the ATD in a: (A) non-scanning, program-driven mode (B) continuous-scanning, interrupt-driven mode (C) non-scanning, interrupt-driven mode (D) continuous-scanning, program-driven mode (10) The length of time required by the SCI to transmit a 10-bit character frame at 38.4 Kbaud is approximately: (A) miliseconds (B) milliseconds (C) milliseconds (D) milliseconds (11) The SCI s RDRF flag is cleared by: (A) reading a character from SCIDR (B) reading SCISR1 and then reading the character from SCIDR (C) reading SCISR1 (D) writing a 1 to the RDRF bit of SCISR1 (12) For interrupt-driven operation of the SCI, a Digital Binky TM should be employed for: (A) the receive section only (B) the transmit section only (C) both the receive and transmit section (D) neither the receive or the transmit section

3 ECE 362 Final Lab Practical Practice Exam / Solution (13) The SCI baud rate divisor that should be used in a 24 MHz system to transmit 10-bit character frames at 38.4 Kbaud is: (A) 26 (B) 39 (C) 78 (D) 156 (14) For a 24 MHz system, the local clock error associated with transmitting 10-bit character frames at 38.4 Kbaud using the SCI is approximately: (A) 0.16% (B) 0.64% (C) 1.60% (D) 6.40% (15) Local clock error does not accumulate on an asynchronous communication link because: (A) the sampling clock is 16 times faster than the data rate (B) the receiver re-synchronizes every time a start bit is detected (C) the transmitter periodically sends sync pulses (D) the receiver re-synchronizes every time a stop bit is detected (16) Half-duplex, when applied to either an SCI or SPI interface, means: (A) data can only be transmitted in one direction (B) data can be transmitted in both directions, but not at the same time (C) data can be transmitted in both directions simultaneously (D) data transmission requires a clock signal (17) Transmission of serial data using the SPI is inherently faster than using the SCI because: (A) synchronous transmission does not require start/stop bits (B) synchronous transmission requires an accompanying clock signal (C) synchronous transmission does not require local synchronization (D) all of the above (18) The double buffering feature of the PWM unit: (A) provides a larger window of time during which the PWM registers can be written (B) provides a larger window of time during which the PWM registers can be read (C) prevents a PWM output from changing the instant its period or duty register is written (D) all of the above (19) Given a 24 MHz bus clock, in 8-bit mode the minimum frequency left-aligned 80% duty cycle square wave that can be generated by the PWM unit is approximately: (A) Hz (B) 1.15 Hz (C) 1.44 Hz (D) 2.30 Hz

4 ECE 362 Final Lab Practical Practice Exam / Solution (20) Given a 24 MHz bus clock, in 16-bit mode the minimum frequency left-aligned 80% duty cycle square wave that can be generated by the PWM unit is approximately: (A) Hz (B) Hz (C) Hz (D) Hz (21) Given a 24 MHz bus clock, in 8-bit mode the maximum frequency left-aligned 80% duty cycle square wave that can be generated by the PWM unit is: (A) 2,400,000 Hz (B) 4,800,000 Hz (C) 6,000,000 Hz (D) 12,000,000 Hz (22) Useful applications of the PWM include: (A) D.C. motor speed control (B) digital-to-analog conversion (C) controlling the intensity of an LED (D) all of the above (23) The TIM Ch 7 periodic interrupt generation capability and the pulse accumulator (PA) can be used simultaneously by: (A) disconnecting the TIM Ch 7 output from the port pin (B) re-routing the TIM Ch 7 output to a different port pin (C) continuously changing the mode of the port pin (D) re-routing the PA input to a different port pin

5 ECE 362 Final Lab Practical Practice Exam / Solution PART 2. Code Analysis For questions 24-28, refer to the file LP2_AP1.asm (available on course website). (24) The theoretical SQNR (signal to quantizing noise ratio) of the digitized input signal is: (A) 6 db (B) 8 db (C) 48 db (D) 60 db (25) The ratio of the output sampling frequency to the input sampling frequency is approximately: (A) 1:1 (B) 2:1 (C) 4:1 (D) 8:1 (26) An appropriate choice for anti-aliasing low-pass filter cut-off frequency, for the application as written, would be: (A) 500 Hz (B) 1000 Hz (C) 5000 Hz (D) 10,000 Hz (27) As the ratio of the PWM output sampling frequency is increased relative to the ATD input sampling frequency, the reconstructed (low-pass filtered) PWM output waveform is expected to: (A) stay the same (B) become more distorted (C) become less distorted (D) have a higher SQNR (28) The distortion in the reconstructed PWM signal (referred to above) is caused by: (A) uniformly sampling both the ATD input and the PWM output (B) uniformly sampling the ATD input, but naturally sampling the PWM output (C) naturally sampling the ATD input, but uniformly sampling the PWM output (D) naturally sampling both the ATD input and the PWM output

6 ECE 362 Final Lab Practical Practice Exam / Solution For questions 29-33, refer to the file LP2_AP2.asm (available on course website). (29) The duty cycle of the PT0 output waveform is: (A) 10% (B) 20% (C) 50% (D) 80% (30) The period (in milliseconds) with which the LED on PT0 blinks is approximately: (A) 1.36 ms (B) 350 ms (C) 696 ms (D) 699 ms (31) Decreasing the value initially loaded into TC0 by one modulo 2 16 (i.e., from $0000 to $FFFF): (A) shifts the blinking phase such that the LED on PT0 before the LED on PT1 (B) shifts the blinking phase such that the LED on PT1 before the LED on PT0 (C) increases the blinking rate of PT0 (D) decreases the blinking rate of PT0 (i.e., has no visible effect) (32) Increasing the value initially loaded into TC0 by one (i.e., from $0000 to $0001): (A) shifts the blinking phase such that the LED on PT0 before the LED on PT1 (B) shifts the blinking phase such that the LED on PT1 before the LED on PT0 (C) increases the blinking rate of PT0 (D) decreases the blinking rate of PT0 (i.e., has no visible effect) (33) Decreasing the value initially loaded into TSCR2 by one (i.e., from $07 to $06): (A) shifts the blinking phase such that the LED on PT0 before the LED on PT1 (B) shifts the blinking phase such that the LED on PT1 before the LED on PT0 (C) increases the blinking rate of PT0 (D) decreases the blinking rate of PT0 (i.e., has no visible effect) SOLUTION: 1-C, 2-D, 3-A, 4-D, 5-A, 6-C, 7-A, 8-D, 9-B, 10-A, 11-B, 12-B, 13-B, 14-A, 15-B, 16-B, 17-D, 18-C, 19-C, 20-A, 21-B, 22-D, 23-A, 24-C, 25-D, 26-C, 27-C, 28-B, 29-C, 30-D, 31-E, 32-A, 33-C