178ball FBGA Specification. 32Gb LPDDR3 (x32) H9CCNNNCLTMLAR-NxD

Transcription

1 178bll FBGA Specifiction 32Gb LPDDR3 (x32) H9CCNNNCLTMLAR-NxD This document is generl product description nd is subject to chnge without notice. SK hynix does not ssume ny responsibility for use of circuits described. No ptent licenses re implied. Rev 1.2 / Jul

2 Document Title FBGA 32Gb (x32, 2CS) LPDDR3 Revision History Revision No. History Drft Dte Remrk Initil Drft for Internl Review Nov Preliminry Operting temperture hs been revised Jn Preliminry Operting temperture hs been revised Sep Preliminry 1.0 Finl Version - IDD6 Spec updte Nov Pckge Totl Input/Output Cpcitnce updte Apr Chnged Refresh Commnd - Deleted DPD - Deleted IDD6 Prtil Arry Self Refresh Current Jul Rev 1.2 / Jul

3 FEATURES [ FBGA ] Opertion Temperture - 0 o C ~ 85 o C Pckge bll FBGA x11.5mm 2, 1.00t, 0.65mm pitch - Led & Hlogen Free [ LPDDR3 ] VDD1 = 1.8V (1.7V to 1.95V) VDD2, VDDCA nd VDDQ = 1.2V (1.14V to 1.30) HSUL_12 interfce (High Speed Unterminted Logic 1.2V) Double dt rte rchitecture for commnd, ddress nd dt Bus; - ll control nd ddress except CS_n, CKE ltched t both rising nd flling edge of the clock - CS_n, CKE ltched t rising edge of the clock - two dt ccesses per clock cycle Differentil clock inputs (CK_t, CK_c) Bi-directionl differentil dt strobe (DQS_t, DQS_c) - Source synchronous dt trnsction ligned to bi-directionl differentil dt strobe (DQS_t, DQS_c) - Dt outputs ligned to the edge of the dt strobe (DQS_t, DQS_c) when READ opertion - Dt inputs ligned to the center of the dt strobe (DQS_t, DQS_c) when WRITE opertion DM msks write dt t the both rising nd flling edge of the dt strobe Progrmmble RL (Red Ltency) nd WL (Write Ltency) Progrmmble burst length: 8 Auto refresh nd self refresh supported All bnk uto refresh nd per bnk uto refresh supported Auto TCSR (Temperture Compensted Self Refresh) PASR (Prtil Arry Self Refresh) by Bnk Msk nd Segment Msk DS (Drive Strength) ZQ (Clibrtion) ODT (On Die Termintion) Rev 1.2 / Jul

4 Functionl Block Digrm CS0_n CKE0 ODT Bll 8Gb x16 device (512M x 16) ZQ0 DQ0~DQ15 DQS0_t~DQS1_t, DQS0_c~DQS1_c DM0~DM1 ZQ1 CS1_n CKE1 ODT GND 8Gb x16 device (512M x 16) 8Gb x16 device (512M x 16) 8Gb x16 device (512M x 16) CA0~CA9 CK_t, CK_c VDD1, VDD2, VDDCA, VDDQ, Vref(CA/DQ) VSS, VSSCA, VSSQ DQ16~DQ31 DQS2_t~DQS3_t, DQS2_c~DQS3_c DM2~DM3 Note 1. Totl current consumption is dependent to user operting conditions. AC nd DC Chrcteristics shown in this specifiction re bsed on single die. See the section of DC Prmeters nd Operting Conditions Rev 1.2 / Jul

5 ORDERING INFORMATION Prt Number Memory Combintion Opertion Voltge Density Speed Pckge H9CCNNNCLTMLAR-NTD LPDDR3 1.8V/1.2/1.2/1.2 32Gb(x32) DDR H9CCNNNCLTMLAR-NUD LPDDR3 1.8V/1.2/1.2/1.2 32Gb(x32) DDR Bll FBGA (Led & Hlogen Free) 178Bll FBGA (Led & Hlogen Free) H 9 C C N N N C L T M L A R - N x D SK Hynix Memory MCP/PoP Product Mode : MCO LPDDR3 only Temperture : Commercil (0~85 C) DRAM Speed : LPDDR3 1600Mbps LPDDR3 1866Mbps Density, Stck, Block Size & Pge Buffer for NVM 1) : None Voltge & I/O for NVM : None Density, Stck, CH & CS for DRAM : 32Gb, QDP, 2CS NAND Speed : none Pckge Mteril : Led & Hlogen Free Pckge Type : FBGA 178 Bll 11x11.5 Genertion : 1st Voltge, I/O & Option for DRAM : 1.2v/1.2, x32, LPDDR3 Rev 1.2 / Jul

6 Bll ASSIGNMENT A DNU DNU VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD1 VDDQ DNU DNU A B DNU VSS ZQ0 ZQ1 VSS VSSQ DQ31 DQ30 DQ29 DQ28 VSSQ DNU B C D CA9 CA8 VSSCA VSSCA NC VDD2 VSS VSSQ VDD2 VDD2 DQ27 DQ26 DM3 DQ15 DQ25 DQ24 VDDQ DQS3 _t DQS3 _c VSSQ C D LPDDR3 Commend/Address LPDDR3 Dt IO E F CA7 VDDCA CA6 VSS VSS VSSQ VDDQ DQ14 DQ13 DQ12 VDDQ CA5 VSSCA VSS VSSQ DQ11 DQ10 DQ9 DQ8 VSSQ E F Power (VDD1,VDD2,VDDCA, VDDQ,VREF) G H VDDCA VSSCA VSSCA VSS VDDCA Vref (CA) VDD2 VSSQ VDD2 VDD2 DM1 VSSQ DQS1 _t DQS1 _c VDDQ VDDQ VDDQ VSSQ VDDQ VDD2 G H Ground (VSS,VSSCA,VSSQ) J CK_c CK_t VSSCA VDD2 VDD2 ODT VDDQ VDDQ Vref (DQ) VSS J K VSS CKE0 CKE1 VDD2 VDD2 VDDQ NC VSSQ VDDQ VDD2 K L VDDCA CS0_ n CS1_ n VDD2 VSS DM0 VSSQ DQS0 _t DQS0 _c VDDQ L M VDDCA CA4 VSSCA VSS VSSQ DQ4 DQ5 DQ6 DQ7 VSSQ M N CA2 CA3 VSS VSS VSSQ VDDQ DQ1 DQ2 DQ3 VDDQ N P CA1 VSSCA VDD2 VDD2 VDD2 DM2 DQ0 DQS2 _t DQS2 _c VSSQ P R CA0 NC VSS VSS VSSQ DQ20 DQ21 DQ22 DQ23 VDDQ R T DNU VSS VSS VSS VSS VSSQ DQ16 DQ17 DQ18 DQ19 VSSQ DNU T U DNU DNU VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD1 VDDQ DNU DNU U Top View 178bll x32 LPDDR3 Note 1. J8 will be used s ODT. Users who don t use ODT Function cn ssign J8 s VSSQ. Rev 1.2 / Jul

7 Pin Description SYMBOL DESCRIPTION Type CS0_n, CS1_n Chip Select Input CK_c, CK_t Differentil Clocks Input CKE0 Clock Enble Input CA0 ~ CA9 Commnd / Address Input DQ0 ~ DQ31 Dt I/O Input/Output DM0 ~ DM3 Input Dt Msk Input/Output DQS0_t ~ DQS3_t Differentil Dt Strobe (rising edge) Input/Output DQS0_c ~ DQS3_c Differentil Dt Strobe (flling edge) Input/Output ZQ Drive Strength Clibrtion Input/Output VDD1 Core Power Supply Power VDD2 Core Power Supply Power VSS Ground Ground VDDQ I/O Power Supply Power VDDCA CA Power Supply Power VSSCA CA Ground Ground VSSQ I/O Ground Ground VREF Reference Voltge Power ODT On Die Termintion Enble Input Input/Output Cpcitnce Prmeter Symbol Min Mx Unit Input cpcitnce, CK_t nd CK_c CCK pf Input cpcitnce, ll other input-only pins CI pf Input/output cpcitnce, DQ, DM, DQS_t, DQS_c CIO pf Input/Output Cpcitnce ZQ CZQ pf (TOPER; VDDQ = V; VDDCA = V; VDD1 = V, VDD2 = V) 1. This prmeter pplies to both die nd pckge. 2. This prmeter is not subject to production test. It is verified by design nd chrcteriztion. The cpcitnce is mesured ccording to JEP147 (Procedure for mesuring input cpcitnce using vector network nlyzer (VNA) with VDD1, VDD2, VDDQ, VSS, VSSCA, VSSQ pplied nd ll other pins floting). 3. CI pplies to CS_n, CKE, CA0-CA9. 4. DM loding mtches DQ nd DQS. 5. MR3 I/O configurtion DS OP3-OP0 = 0001B (34.3 Ohm typicl) 6. Mximum externl lod cpcitnce on ZQ pin, including pckging, bord, pin, resistor, nd other LPDDR3 devices: 5pF. Rev 1.2 / Jul

8 PACKAGE INFORMATION 178 Bll 0.65mm pitch 11.0mm x 11.5mm [t = 1.00mm mx] FBGA x 12 = ± Unit: mm A1 INDEX MARK DNU DNU DNU DQ6 DNU DQ6 DNU DQ6 DNU DQ6 DQ6 DQ6 A VSSQ VSSQ VSSQ VDDQ VDDQ VDDQ VSSQ VDDQ VDDQ VDDQ VDDQ VDDQ B VDD1 VDD1 VDD2 /b VDD2 /b VDD2 /b VDD1 VDD2 /b VDD2 /b VDD2 /b VDD2 /b C DQ1 DQ1 VDDQ VDDQ VDDQ DQ1 VDDQ VDDQ VDDQ VDDQ D VSSQ VSSQ DQ0 DQ0 DQ0 VSSQ DQ0 DQ0 DQ0 DQ0 E DM2 DM2 VDDQ VDDQ VDDQ DM2 VDDQ VDDQ VDDQ VDDQ F ± DQS2_t VSSQ VDDQ DQ20 DQ19 DQS2_t VSSQ VDDQ DQ20 DQ19 DQS2_c DQ23 DQ22 DQ21 VSSQ DQS2_c DQ23 DQ22 DQ21 VSSQ DQS2_c DQ23 DQ22 DQ21 VSSQ DQS2_t VSSQ VDDQ DQ20 DQ19 DQS2_c DQ23 DQ22 DQ21 VSSQ DQS2_c DQ23 DQ22 DQ21 VSSQ DQS2_c DQ23 DQ22 DQ21 VSSQ DQS2_c DQ23 DQ22 DQ21 VSSQ G H J K L x 16 = VDDQ DQ16 VDDQ DQ16 DQ18 DQ17 DQ18 DQ17 DQ18 DQ17 VDDQ DQ16 DQ18 DQ17 DQ18 DQ17 DQ18 DQ17 DQ18 DQ17 M N VDD2 b VDD2 b VDD1 b VDD1 b VDD1 b VDD2 b VDD1 b VDD1 b VDD1 b VDD1 b P VSS b VSS b CA0 b CA0 b CA0 b VSS b CA0 b CA0 b CA0 b CA0 b R VDDCA b VDDCA b VDDCA b CA1 b CA1 b CA1 b VDDCA b CA1 b CA1 b CA1 b CA1 b CA1 b T Vref (CA) b Vref (CA) b CA2 b CA2 b CA2 b CA2 b Vref (CA) b CA2 b CA2 b CA2 b CA2 b CA2 b U 178 x Ø0.300±0.050 (Post Reflow Ø0.320±0.050) Ø0.15 M C A B ± ± ± Bottom View ± Vref (CA) b Vref (CA) b CA2 b CA2 b CA2 b CA2 b Vref (CA) b CA2 b CA2 b CA2 b CA2 b CA2 b SEATING PLANE C Front View 0.10 C Rev 1.2 / Jul

9 8Gb LPDDR3 SDRAM Rev 1.2 / Jul

10 Input/Output Functionl Description SYMBOL TYPE DESCRIPTION CK_t, CK_c Input Clock: CK_t nd CK_c re differentil clock inputs. All Double Dt Rte (DDR) CA inputs re smpled on both positive nd negtive edge of CK_t. Single Dt Rte (SDR) inputs, CS_n nd CKE, re smpled t the positive Clock edge. Clock is defined s the differentil pir, CK_t nd CK_c. The positive Clock edge is defined by the crosspoint of rising CK_t nd flling CK_c. The negtive Clock edge is defined by the crosspoint of flling CK_t nd rising CK_c. CKE CS_n CA0 - CA9 DQ0 - DQ15 (x16) DQ0 - DQ31 (x32) DQS0_t, DQS1_t, DQS0_c, DQS1_c (x16) DQS0_t - DQS3_t, DQS0_c - DQS3_c (x32) DM0-DM1 (x16) DM0-DM3 (x32) Input Input Input I/O I/O Input Clock Enble: CKE HIGH ctivtes nd CKE LOW dectivtes internl clock signls nd therefore device input buffers nd output drivers. Power svings modes re entered nd exited through CKE trnsitions. CKE is considered prt of the commnd code. CKE is smpled t the positive Clock edge. Chip Select: CS_n is considered prt of the commnd code.cs_n is smpled t the positive Clock edge. DDR Commnd/Address Inputs: Uni-directionl commnd/ddress bus inputs. CA is considered prt of the commnd code. Dt Input/Output: Bi-directionl dt bus Dt Strobe (Bi-directionl, Differentil): The dt strobe is bi-directionl (used for red nd write dt) nd differentil (DQS_t nd DQS_c). It is output with red dt nd input with write dt. DQS_t is edge-ligned to red dt nd centered with write dt. For x16, DQS0_t nd DQS0_c correspond to the dt on DQ0 - DQ7; DQS1_t nd DQS1_c to the dt on DQ8 - DQ15. For x32 DQS0_t nd DQS0_c correspond to the dt on DQ0 - DQ7, DQS1_t nd DQS1_c to the dt on DQ8 - DQ15, DQS2_t nd DQS2_c to the dt on DQ16 - DQ23, DQS3_t nd DQS3_c to the dt on DQ24 - DQ31. Input Dt Msk: DM is the input msk signl for write dt. Input dt is msked when DM is smpled HIGH coincident with tht input dt during Write ccess. DM is smpled on both edges of DQS_t. Although DM is for input only, the DM loding shll mtch the DQ nd DQS_t (or DQS_c). For x16 nd x32 devices, DM0 is the input dt msk signl for the dt on DQ0-7. DM1 is the input dt msk signl for the dt on DQ8-15. For x32 devices, DM2 is the input dt msk signl for the dt on DQ16-23 nd DM3 is the input dt msk signl for the dt on DQ ODT Input On-Die Termintion: This signl enbles nd disbles termintion on the DRAM DQ bus ccording to the specified mode register settings. VDD1 Supply Core Power Supply 1 VDD2 Supply Core Power Supply 2 VDDCA Supply Input Receiver Power Supply: Power for CA0-9, CKE, CS_n, CK_t nd CK_c input buffers. VDDQ Supply I/O Power Supply: Power supply for dt input/output buffers. VREFCA Reference Voltge for CA Commnd nd Control Input Receiver: Reference voltge Supply for ll CA0-9, CKE, CS_n, CK_t nd CK_c input buffers. VREFDQ Supply Reference Voltge for DQ Input Receiver: Reference voltge for ll Dt input buffers. VSS Supply Ground VSSCA Supply Ground for Input Receivers VSSQ Supply I/O Ground: Ground for dt input/output buffers ZQ I/O Reference Pin for Output Drive Strength Clibrtion Rev 1.2 / Jul

11 Functionl Description LPDDR3-SDRAM is high-speed synchronous DRAM device internlly configured s n 8-bnk memory. These devices contin the following number of bits: 8 Gb hs 8,589,934,592 bits LPDDR3 devices use double dt rte rchitecture on the Commnd/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contins commnd, ddress, nd bnk informtion. Ech commnd uses one clock cycle, during which commnd informtion is trnsferred on both the positive nd negtive edge of the clock. These devices lso use double dt rte rchitecture on the DQ pins to chieve high speed opertion. The double dt rte rchitecture is essentilly n 8n prefetch rchitecture with n interfce designed to trnsfer two dt bits per DQ every clock cycle t the I/O pins. A single red or write ccess for the LPDDR3 SDRAM effectively consists of single 8n-bit wide, one clock cycle dt trnsfer t the internl DRAM core nd eight corresponding n-bit wide, one-hlf-clockcycle dt trnsfers t the I/O pins. Red nd write ccesses to the LPDDR3 SDRAMs re burst oriented; ccesses strt t selected loction nd continue for progrmmed number of loctions in progrmmed sequence. Accesses begin with the registrtion of n Activte commnd, which is then followed by Red or Write commnd. The ddress nd BA bits registered coincident with the Activte commnd re used to select the row nd the bnk to be ccessed. The ddress bits registered coincident with the Red or Write commnd re used to select the bnk nd the strting column loction for the burst ccess. Prior to norml opertion, the LPDDR3 SDRAM must be initilized. The following section provides detiled informtion covering device initiliztion, register definition, commnd description nd device opertion. LPDDR3 SDRAM Addressing x16 x32 Density 8Gb Number of Bnks 8 Bnk Addresses BA0 - BA2 t REFI (us) Row Addresses Column Addresses 1 Row Addresses Column Addresses 1 R0 - R14 C0 - C10 R0 - R14 C0 - C9 1. The lest-significnt column ddress C0 is not trnsmitted on the CA bus, nd is implied to be zero. 2. trefi vlues for ll bnk refresh is Tc = -30 ~ 85 C, Tc mens Operting Cse Temperture. 3. Row nd Column Address vlues on the CA bus which re not used re don t cre. 4. No memory present t ddresses with R13=R14=HIGH. ACT commnd with R13=R14=HIGH is ignored (NOP). Write to R13=R14=HIGH is ignored (NOP). Rev 1.2 / Jul

12 STATE DIAGRAM Power Applied Power On Resetting MR Reding MRR RESET Resetting Self Refreshing PD SREF SREFX Resetting Power Down PDX MRW RESET Idle 1 REF Refreshing PR, PRA MR Writing MRR Idle MR Reding ACT PDX PD Idle Power Down Active Power Down PDX MRR Active MR Reding Automtic Sequence Commnd Sequence PD Active *1 Write WR RD RD Writing Reding WRA WRA RDA RDA Writing with Autoprechrge PR, PRA Reding with Autoprechrge Prechrging PR(A) = Prechrge (All) ACT = Activte WR(A) = Write (with Autoprechrge) RD(A) = Red (with Autoprechrge) RESET = Reset is chieved through MRW commnd MRW = Mode Register Write MRR = Mode Register Red PD = Enter Power Down PDX = Exit Power Down SREF = Enter Self Refresh SREFX = Exit Self Refresh REF = Refresh Rev 1.2 / Jul

13 1. In the Idle stte, ll bnks re prechrged. 2. In the cse of MRW to enter CA Trining mode or Write Leveling Mode, the stte mchine will not utomticlly return to the Idle stte. In these cses n dditionl MRW commnd is required to exit either operting mode nd return to the Idle stte. See sections "CA Trining" or "Write Leveling". 3. Terminted bursts re not llowed. For these stte trnsitions, the burst opertion must be completed before the trnsition cn occur. 4. Use cution with this digrm. It is intended to provide floorpln of the possible stte trnsitions nd commnds to control them, not ll detils. In prticulr, situtions involving more thn one bnk re not cptured in full detil. Rev 1.2 / Jul

14 Power-up, Initiliztion nd Power-off Voltge Rmp nd Device Initiliztion The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mndtory. 1. Voltge Rmp While pplying power (fter T), CKE must be held LOW ( 0.2 VDDCA), nd ll other inputs must be between VILmin nd VIHmx. The device outputs remin t High-Z while CKE is held LOW. Following the completion of the voltge rmp (Tb), CKE must be mintined LOW. DQ, DM, DQS_t nd DQS_c voltge levels must be between VSSQ nd VDDQ during voltge rmp to void ltchup. CK_t, CK_c, CS_n, nd CA input levels must be between VSSCA nd VDDCA during voltge rmp to void ltch-up. Voltge rmp power supply requirements re provided in the tble Voltge Rmp Conditions. After... T is reched Tble. Voltge Rmp Conditions Applicble Conditions VDD1 must be greter thn VDD2-200mV. VDD1 nd VDD2 must be greter thn VDDCA-200mV. VDD1 nd VDD2 must be greter thn VDDQ-200mV. VREF must lwys be less thn ll other supply voltges. 1. T is the point when ny power supply first reches 300mV. 2. Noted conditions pply between T nd power-off (controlled or uncontrolled). 3. Tb is the point t which ll supply nd reference voltges re within their defined operting rnges. 4. Power rmp durtion tinit0 (Tb - T) must not exceed 20ms. 5. The voltge difference between ny of VSS, VSSQ, nd VSSCA pins must not exceed 100mV. Beginning t Tb, CKE must remin LOW for t lest tinit1, fter which CKE cn be sserted HIGH. The clock must be stble t lest tinit2 prior to the first CKE LOW-to-HIGH trnsition (Tc). CKE, CS_n, nd CA inputs must observe setup nd hold requirements (tis, tih) with respect to the first rising clock edge (s well s to subsequent flling nd rising edges). If ny MRR commnds re issued, the clock period must be within the rnge defined for tckb. MRW commnds cn be issued t norml clock frequencies s long s ll AC timings re met. Some AC prmeters (for exmple, tdqsck) could hve relxed timings (such s t DQSCKb) before the system is ppropritely configured. While keeping CKE HIGH, NOP commnds must be issued for t lest tinit3 (Td). The ODT input signl my be in undefined stte until tis before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signl shll be stticlly held t either LOW or HIGH. The ODT input signl remins sttic until the power up initiliztion sequence is finished, including the expirtion of tzqinit. 2. Reset Commnd After tinit3 is stisfied, the MRW RESET commnd must be issued (Td). An optionl PRECHARGE ALL commnd cn be issued prior to the MRW RESET commnd. Wit t lest tinit4 while keeping CKE sserted nd issuing NOP commnds. Only NOP commnds re llowed during time tinit4. Rev 1.2 / Jul

15 3. MRRs nd Device Auto Initiliztion (DAI) Polling After tinit4 is stisfied (Te), only MRR commnds nd power-down entry/exit commnds re supported. After Te, CKE cn go LOW in lignment with power-down entry nd exit specifictions. MRR commnds re only vlid t this time if the CA bus does not need to be trined. my only begin fter time Tf. User my issue MRR commnd to poll the DAI bit which will indicte if device uto initiliztion is complete; once DAI bit indictes completion, SDRAM is in idle stte. Device will lso be in idle stte fter tinit5(mx) hs expired (whether or not DAI bit hs been red by MRR commnd). As the memory output buffers re not properly configured by Te, some AC prmeters must hve relxed timings before the system is ppropritely configured. After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI complete), the device is in the idle stte (Tf). DAI sttus cn be determined by issuing the MRR commnd to MR0. The device sets the DAI bit no lter thn tinit5 fter the RESET commnd. The controller must wit t lest tinit5 or until the DAI bit is set before proceeding. 4. ZQ Clibrtion If CA Trining is not required, the MRW initiliztion clibrtion (ZQ_CAL) commnd cn be issued to the memory (MR10) fter time Tf. If CA Trining is required, the CA Trining my begin t time Tf. See the section of "Mode Register Write - CA Trining Mode" for the CA Trining commnd. No other CA commnds (other thn RESET or NOP) my be issued prior to the completion of CA Trining. At the completion of CA Trining (Tf'), the MRW initiliztion clibrtion (ZQ_CAL) commnd cn be issued to the memory (MR10). This commnd is used to clibrte output impednce over process, voltge, nd temperture. In systems where more thn one LPDDR3 device exists on the sme bus, the controller must not overlp MRW ZQ_CAL commnds. The device is redy for norml opertion fter tzqinit. 5. Norml Opertion After tzqinit (Tg), MRW commnds must be used to properly configure the memory (for exmple the output buffer drive strength, ltencies, etc.). Specificlly, MR1, MR2, nd MR3 must be set to configure the memory for the trget frequency nd memory configurtion. After the initiliztion sequence is complete, the device is redy for ny vlid commnd. After Tg, the clock frequency cn be chnged using the procedure described in the LPDDR3 specifiction. Tble. Timing Prmeters for initiliztion Symbol Prmeter Vlue min mx Unit tinit0 Mximum Voltge Rmp Time - 20 ms tinit1 Minimum CKE low time fter completion of voltge rmp ns tinit2 Minimum stble clock before first CKE high 5 - tck tinit3 Minimum idle time fter first CKE ssertion us tinit4 Minimum idle time fter Reset commnd 1 - us tinit5 Mximum durtion of Device Auto-Initiliztion - 10 us tzqinit ZQ Initil Clibrtion for LPDDR3 devices 1 - us tckb Clock cycle time during boot ns Rev 1.2 / Jul

16 T Tb Tc Td Te Tf Tf Tg t INIT2 = 5 t CK (min) CK_t / CK_c t INIT0 = 20 ms (mx) Supplies t INIT3 = 200 us (min) t INIT1 = 100 ns (min) CKE PD t ISCKE t INIT5 t INIT4 = 1 us (min) t ZQINIT CA* RESET MRR CA Trining ZQC Vlid DQ t IS ODT Sttic HIGH or LOW Vlid * Midlevel on CA bus mens: vlid NOP Figure. Power Rmp nd Initiliztion Sequence Notes 1. High-Z on the CA bus indictes NOP. 2. For tinit vlues, see the tble "Timing Prmeters for Initiliztion". 3. After RESET commnd (time Te), RTT is disbled until ODT function is enbled by MRW to MR11 following Tg. 4. CA Trining is optionl. Initiliztion After Reset (without Power rmp) If the RESET commnd is issued before or fter the power-up initiliztion sequence, the re-initiliztion procedure must begin t Td. Power-off Sequence The following procedure is required to power off the device. While powering off, CKE must be held LOW ( 0.2 VDDCA); ll other inputs must be between VILmin nd VIHmx. The device outputs remin t High-Z while CKE is held LOW. DQ, DM, DQS_t, nd DQS_c voltge levels must be between VSSQ nd VDDQ during the power-off sequence to void ltch-up. CK_t, CK_c, CS_n, nd CA input levels must be between VSSCA nd VDDCA during the power-off sequence to void ltch-up. Tx is the point where ny power supply drops below the minimum vlue specified. Tz is the point where ll power supplies re below 300mV. After Tz, the device is powered off (see the tble Power Supply Conditions ). Rev 1.2 / Jul

17 Between... Tx nd Tz Tble. Power Supply Conditions Applicble Conditions VDD1 must be greter thn VDD2 200mV VDD1 must be greter thn VDDCA 200mV VDD1 must be greter thn VDDQ 200mV VREF must lwys be less thn ll other supply voltges The voltge difference between ny of VSS, VSSQ, nd VSSCA pins must not exceed 100mV. Uncontrolled Power-Off Sequence When n uncontrolled power-off occurs, the following conditions must be met: At Tx, when the power supply drops below the minimum vlues specified, ll power supplies must be turned off nd ll power-supply current cpcity must be t zero, except for ny sttic chrge remining in the system. After Tz (the point t which ll power supplies first rech 300mV), the device must power off. The time between Tx nd Tz must not exceed 10ms. During this period, the reltive voltge between power supplies is uncontrolled. VDD1 nd VDD2 must decrese with slope lower thn 0.5 V/μs between Tx nd Tz. An uncontrolled power-off sequence cn occur mximum of 400 times over the life of the device. Tble. Power-Off Timing Symbol Prmeter Vlue min mx Unit tpoff Mximum power-off rmp time - 2 sec Rev 1.2 / Jul

18 Mode Register Definition Tble below shows the mode registers for LPDDR3 SDRAM. Ech register is denoted s R if it cn be red but not written, W if it cn be written but not red, nd R/W if it cn be red nd written. A Mode Register Red commnd shll be used to red mode register. A Mode Register Write commnd shll be used to write mode register. MR # MA <7:0> Tble. Mode Register Assignment Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link WL 0 00H Device Info. R RL3 set B (RFU) RZQI (RFU) DAI go to MR0 (Optionl) 1 01H Device Feture1 W nwr (for AP) (RFU) BT BL go to MR1 2 02H Device Feture 2 W WR Lev WL Select (RFU) nwre RL & WL go to MR2 3 03H I/O Config-1 W (RFU) DS go to MR3 4 04H Device Temperture R TUF (RFU) Refresh Rte go to MR4 5 05H Bsic Config-1 R Mnufcturer ID go to MR5 6 06H Bsic Config-2 R Revision ID1 go to MR6 7 07H Bsic Config-3 R Revision ID2 go to MR7 8 08H Bsic Config-4 R I/O width Density Type go to MR8 9 09H Test Mode W Vendor-Specific Test Mode go to MR9 10 0AH Clibrtion W Clibrtion Code go to MR BH ODT W (RFU) 16 10H PASR_Bnk W PASR Bnk Msk 17 11H PASR_Segment W PASR Segment Msk 32 20H 40 28H 41 29H DQ Clibrtion Pttern A DQ Clibrtion Pttern B CA Trining Entry for CA0-3, CA5-8 R R W go to 63 3FH Reset W X MR63 1. RFU bits shll be set to `0' during Mode Register writes. 2. RFU bits shll be red s `0' during Mode Register reds. 3. All Mode Registers tht re specified s RFU or write-only shll return undefined dt when red nd DQS_t, DQS_c shll be toggled. 4. All Mode Registers tht re specified s RFU shll not be written. 5. Writes to red-only registers shll hve no impcts on the functionlity of the device. PD CTL See the section DQ Clibrtion See the section DQ Clibrtion DQ ODT See the section Mode Register Write - CA Trining Mode 42 2AH CA Trining Exit W See the section Mode Register Write - CA Trining Mode 48 30H CA Trining Entry for CA4, 9 W See the section Mode Register Write - CA Trining Mode go to MR11 go to MR16 go to MR17 go to MR32 go to MR40 go to MR41 go to MR42 go to MR48 Rev 1.2 / Jul

19 MR0 Device Informtion (MA<7:0> = 00H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RL3 WL (Set B) Support (RFU) RZQI (Optionl) (RFU) DAI DAI (Device Auto-Initiliztion Sttus) Red-only OP0 0B: DAI complete 1B: DAI still in progress RZQI (Built in Self Test for RZQ Informtion) Red-only OP4:OP3 00B: RZQ self test not supported 01B: ZQ-pin my connect to VDDCA or flot 10B: ZQ-pin my short to GND 11B: ZQ-pin self test completed, no error condition detected (ZQ-pin my not connect to VDD or flot nor short to GND) WL (Set B) Support Red-only OP<6> 0B: DRAM does not support WL (Set B) 1B: DRAM supports WL (Set B) 0B : DRAM does not support RL=3, nwr=3, WL=1 RL3 Option Support Red-only OP<7> 1B : DRAM supports RL=3, nwr=3, WL=1 for frequencies <= RZQI, if supported, will be set upon completion of the MRW ZQ Initiliztion Clibrtion commnd. 2. If ZQ is connected to VDDCA to set defult clibrtion, OP[4:3] shll be set to 01. If ZQ is not connected to VDDCA, either OP[4:3]=01 or OP[4:3]=10 might indicte ZQ-pin ssembly error. It is recommended tht the ssembly error is corrected. 3. In the cse of possible ssembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 4), the LPDDR3 device will defult to fctory trim settings for RON, nd will ignore ZQ clibrtion commnds. In either cse, the system my not function s intended. 4. In the cse of the ZQ self-test returning vlue of 11b, this result indictes tht the device hs detected resistor connection to the ZQ pin. However, this result cnnot be used to vlidte the ZQ resistor vlue or tht the ZQ resistor tolernce meets the specified limits (i.e. 240-ohm +/-1%). Rev 1.2 / Jul

20 MR1 Device Feture 1 (MA<7:0> = 01H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 nwr (for AP) (RFU) BT BL BL Write-only OP<2:0> 011B: BL8 (defult) 100B: Reserved All others: reserved BT Write-only OP<3> 0B: Don t cre nwr Write-only OP<7:5> If nwre (in MR2 OP4) = 0 001B : nwr=3 (optionl) 100B : nwr=6 110B : nwr=8 111B : nwr=9 If nwre (in MR2 OP4) = 1 000B : nwr=10 (defult) 001B : nwr=11 010B : nwr=12 100B : nwr=14 110B : nwr=16 All others: reserved 1. Progrmmed vlue in nwr register is the number of clock cycles which determines when to strt internl prechrge opertion for write burst with AP enbled. It is determined by RU(tWR/tCK). Tble. Burst Sequence by BL nd BT Burst Cycle Number nd Burst Address Sequence C2 C1 C0 BT BL B 0B 0B B 1B 0B seq 8 1B 0B 0B B 1B 0B C0 inputs re not present on CA bus. Those re implied zero. 2. For BL=8, the burst ddress represents C2 - C0. Rev 1.2 / Jul

21 MR2 Device Feture 2 (MA<7:0> = 02H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 WR Lev WL Select (RFU) nwre RL & WL RL & WL Write-only OP<3:0> If OP<6> =0 (WL Set A, defult) 0001B: RL = 3 / WL = 1 ( 166 MHz, optionl 1 ) 0100B: RL = 6 / WL = 3 ( 400 MHz) 0110B: RL = 8 / WL = 4 ( 533 MHz) 0111B: RL = 9 / WL = 5 ( 600 MHz) 1000B: RL = 10 / WL = 6 ( 667 MHz, defult) 1001B: RL = 11 / WL = 6 ( 733 MHz) 1010B: RL = 12 / WL = 6 ( 800 MHz) 1100B: RL = 14 / WL = 8 ( 933 MHz) 1110B: RL = 16 / WL = 8 ( 1066 MHz) All others: reserved If OP<6> =1 (WL Set B, optionl 2 ) 0001B: RL = 3 / WL = 1 ( 166 MHz, optionl 1 ) 0100B: RL = 6 / WL = 3 ( 400 MHz) 0110B: RL = 8 / WL = 4 ( 533 MHz) 0111B: RL = 9 / WL = 5 ( 600 MHz) 1000B: RL = 10 / WL = 8 ( 667 MHz, defult) 1001B: RL = 11 / WL = 9 ( 733 MHz) 1010B: RL = 12 / WL = 9 ( 800 MHz) 1100B: RL = 14 / WL = 11 ( 933MHz) 1110B: RL = 16 / WL = 13 ( 1066MHz) All others: reserved nwre Write-only OP<4> 0B : Enble nwr progrming 9 1B : Enble nwr progrming > 9 (defult) WL Select Write-only OP<6> 0B : Select WL Set A (defult) 1B : Select WL Set B (optionl 2 ) Write Leveling Write-only OP<7> 0B : Disbled (defult) 1B : Enbled 1. See MR0, OP<7>. 2. See MR0, OP<6> Rev 1.2 / Jul

22 MR3 I/O Configurtion 1 (MA<7:0> = 03H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 (RFU) DS DS Write-only OP<3:0> 0000B: reserved 0001B: 34.3 typicl pull-down/pull-up 0010B: 40 typicl pull-down/pull-up (defult) 0011B: 48 typicl pull-down/pull-up 0100B: reserved for 60 typicl pull-down/pull-up 0110B: reserved for 80 typicl pull-down/pull-up 1001B: 34.3 typicl pull-down, 40 Typicl Pull-up (optionl 1 ) 1010B: 40 typicl pull-down, 48 Typicl Pull-up (optionl 1 ) 1011B: 34.3 typicl pull-down, 48 Typicl Pull-up (optionl 1 ) All others: reserved 1. Plese contct us, for the supportbility of the optionl feture. Rev 1.2 / Jul

23 MR4 Device Temperture (MA<7:0> = 04H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 TUF (RFU) Refresh Rte Refresh Rte Red-only OP<2:0> 000B: Low temperture operting limit exceeded 001B: 4 x trefi, 4 x trefipb, 4 x trefw 010B: 2 x trefi, 2 x trefipb, 2 x trefw 011B: 1 x trefi, 1 x trefipb, 1 x trefw ( 85 C) 100B: 1/2 x trefi, 1/2 x trefipb, 1/2 x trefw, do not de-rte AC timing 101B: 1/4 x trefi, 1/4 x trefipb, 1/4 x trefw, do not de-rte AC timing 110B: 1/4 x trefi, 1/4 x trefipb, 1/4 x trefw, de-rte AC timing 111B: High temperture operting limit exceeded Temperture Updte Flg (TUF) Red-only OP<7> 0B: OP<2:0> vlue hs not chnged since lst red of MR4 1B: OP<2:0> vlue hs chnged since lst red of MR4 1. A Mode Register Red from MR4 will reset OP7 to OP7 is reset to 0 t power-up. 3. If OP2 equls 1', the device temperture is greter thn 85 o C. 4. OP7 is set to 1 if OP2:OP0 hs chnged t ny time since the lst red of MR4. 5. LPDDR3 might not operte properly when OP[2:0] = 000B or 111B. 6. For specified operting temperture rnge nd mximum operting temperture refer to the section of Operting Temperture Rnge. 7. LPDDR3 devices shll be de-rted by dding derting vlues to the following core timing prmeters: trcd, trc, tras, trp nd trrd. tdqsck shll be de-rted ccording to the tdqsck de-rting in AC timing tble. Previling clock frequency spec nd relted setup nd hold timings shll remin unchnged. 8. See the section of Temperture Sensor for informtion on the recommended frequency of reding MR4. Rev 1.2 / Jul

24 MR5 Bsic Configurtion1 (MA<7:0> = 05H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Mnufcturer ID Compny ID Red-only OP<7:0> B: Hynix Semiconductor MR6 Bsic Configurtion2 (MA<7:0> = 06H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID 1 Revision ID1 Red-only OP<7:0> B MR7 Bsic Configurtion3 (MA<7:0> = 07H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID 2 Revision ID2 Red-only OP<7:0> B: A-version MR8 Bsic Configurtion4 (MA<7:0> = 08H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 I/O width Density Type Type Red-only OP<1:0> Density Red-only OP<5:2> I/O width Red-only OP<7:6> 11B: S8 All Others : Reserved 0110B : 4Gb 1110B : 6Gb 0111B : 8Gb 1101B : 12Gb 1000B : 16Gb 1001B : 32Gb All Others : Reserved 00B: x32 01B: x16 All Others : Reserved Rev 1.2 / Jul

25 MR9 Test Mode (MA<7:0> = 09H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Vendor-specific Test Mode MR10 Clibrtion (MA<7:0> = 0AH) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Clibrtion Code Clibrtion Code Write Only OP<7:0> B: Clibrtion commnd fter initiliztion B: Long Clibrtion B: Short Clibrtion B: ZQ Reset others: reserved 1. Host processor shll not write MR10 with Reserved vlues 2. LPDDR3 devices shll ignore clibrtion commnd when Reserved vlue is written into MR See AC timing tble for the clibrtion ltency. 4. If ZQ is connected to VSSCA through RZQ, either the ZQ clibrtion function (see "Mode Register Write ZQ Clibrtion Commnd") or defult clibrtion (through the ZQRESET commnd) is supported. If ZQ is connected to VDDCA, the device opertes with defult clibrtion, nd ZQ clibrtion commnds re ignored. In both cses, the ZQ connection shll not chnge fter power is pplied to the device. 5. LPDDR3 devices tht do not support clibrtion shll ignore the ZQ Clibrtion commnd. 6. Optionlly, the MRW ZQ Initiliztion Clibrtion commnd will updte MR0 to indicte RZQ pin connection. MR11 ODT (MA<7:0> = 0BH) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 (RFU) PD Control DQ ODT 00B : Disble (Defult) DQ ODT Write Only OP<1:0> 01B : RZQ/4 (See the Note 1.) 10B : RZQ/2 11B : RZQ/1 Power Down Control Write Only OP<2> 0B : ODT disbled by DRAM during power down 1B : ODT enbled by DRAM during power down 1. RZQ/4 shll be supported for LPDDR devices. RZQ/4 support is optionl for LPDDR nd LPDDR devices. Consult mnufcturer specifictions for RZQ/4 support for LPDDR nd LPDDR MR12:15 (Reserved) (MA<7:0> = 0CH - 0FH) Rev 1.2 / Jul

26 MR16 PASR Bnk Msk (MA<7:0> = 10H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Bnk Msk Bnk <7:0> Msk Write-only OP<7:0> 0B : refresh enble to the bnk (=unmsked, defult) 1B : refresh blocked (=msked) OP Bnk Msk LPDDR3 SDRAM 0 XXXXXXX1 Bnk 0 1 XXXXXX1X Bnk 1 2 XXXXX1XX Bnk 2 3 XXXX1XXX Bnk 3 4 XXX1XXXX Bnk 4 5 XX1XXXXX Bnk 5 6 X1XXXXXX Bnk 6 7 1XXXXXXX Bnk 7 MR17 PASR Segment Msk (MA<7:0> = 11H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Segment Msk Segment <7:0> Msk Write-only OP<7:0> 0B : refresh enble to the segment (=unmsked, defult) 1B : refresh blocked (=msked) Segment OP Segment Msk 4Gb R13:11 6Gb 2 R14:12 8Gb R14: XXXXXXX1 000B 1 1 XXXXXX1X 001B 2 2 XXXXX1XX 010B 3 3 XXXX1XXX 011B 4 4 XXX1XXXX 100B 5 5 XX1XXXXX 101B 6 6 X1XXXXXX 110B 7 7 1XXXXXXX 111B 12Gb 2 R14:12 16Gb R14:12 1. This tble indictes the rnge of row ddresses in ech msked segment. X is do not cre for prticulr segment. 2. No memory present t ddresses with R13=R14=HIGH. Segment msks 6 nd 7 re ignored. Rev 1.2 / Jul

27 MR18:31 (Reserved) (MA<7:0> = 12H - 1FH) MR32 DQ Clibrtion Pttern A (MA<7:0> = 20H): MRR only Reds to MR32 return DQ Clibrtion Pttern A. See the section of DQ Clibrtion. MR33:39 (Reserved) (MA<7:0> = 21H - 27H) MR40 DQ Clibrtion Pttern B (MA<7:0> = 28H): MRR only Reds to MR40 return DQ Clibrtion Pttern B. See the section of DQ Clibrtion. MR41 CA Clibrtion Mode Entry for CA0-3, CA5-8 (MA<7:0> = 29H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 A4 See the section of CA Clibrtion. MR42 CA Clibrtion Mode Exit (MA<7:0> = 2AH) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 A8 See the section of CA Clibrtion. MR43:47 (Reserved) (MA<7:0> = 2BH - 2FH) MR48 CA Clibrtion Mode Entry for CA4, 9 (MA<7:0> = 30H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 C0 See the section of CA Clibrtion. MR49:62 (Reserved) (MA<7:0> = 31H - 3EH) MR63 Reset (MA<7:0> = 3FH): MRW only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 X or 0xFC For dditionl informtion on MRW RESET, see Mode Register Write Commnd section. Rev 1.2 / Jul

28 TRUTH TABLES Opertion or timing tht is not specified is illegl nd fter such n event, in order to gurntee proper opertion, the LPDDR3 device must be powered down nd then restrted through the specified initiliztion sequence before norml opertion cn continue. COMMAND TRUTH TABLE SDR Commnd Pins (2) DDR CA Pins (10) Commnd CKE CK_t CS_n CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 edge CK_t(n-1) CK_t(n) L L L L L MA0 MA1 MA2 MA3 MA4 MA5 rising MRW H H X MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 flling L L L L H MA0 MA1 MA2 MA3 MA4 MA5 rising MRR H H X MA6 MA7 X flling Refresh L L L H L X rising H H (per bnk) X X flling Refresh L L L H H X rising H H (ll bnk) X X flling Enter L L L H X rising Self Refresh H L X X flling Active L L H R8 R9 R10 R11 R12 BA0 BA1 BA2 rising (bnk) H H X R0 R1 R2 R3 R4 R5 R6 R7 R13 R14 flling Write L H L L RFU RFU C1 C2 BA0 BA1 BA2 rising (bnk) H H X AP 3 C3 C4 C5 C6 C7 C8 C9 C10 C11 flling Red L H L H RFU RFU C1 C2 BA0 BA1 BA2 rising (bnk) H H X AP 3 C3 C4 C5 C6 C7 C8 C9 C10 C11 flling Prechrge L H H L H AB X X BA0 BA1 BA2 rising (per bnk, H H ll bnk) 11 X X X X X X X X X X X flling L H H H X rising NOP H H X X flling Mintin SREF, PD X H H H X rising (NOP) 4 L L X X flling H X rising NOP H H X X flling Mintin X X rising PD, SREF L L (NOP) 4 X X flling Enter H X rising Power Down H L X X flling Exit H X rising L H PD, SREF X X flling 1. All LPDDR3 commnds re defined by sttes of CS_n, CA0, CA1, CA2, CA3, nd CKE t the rising edge of the clock. 2. Bnk ddresses BA0, BA1, BA2 (BA) determine which bnk is to be operted upon. 3. AP "high" during READ or WRITE commnd indictes tht n uto-prechrge will occur to the bnk ssocited with the READ or WRITE commnd. 4. "X" mens "H or L (but defined logic level)", except when the LPDDR3 SDRAM is in PD, or SREF, in which cse CS_n, CK_t/CK_c, nd CA cn be floted fter the required tcpded time is stisfied, nd until the required exit procedure is initited s described in the respective entry/exit procedure. 5. Self refresh exit is synchronous. 6. VREF must be between 0 nd VDDQ during Self Refresh opertion. 7. CAxr refers to commnd/ddress bit "x" on the rising edge of clock. 8. CAxf refers to commnd/ddress bit "x" on the flling edge of clock. Rev 1.2 / Jul

29 9. CS_n nd CKE re smpled t the rising edge of clock. 10. The lest-significnt column ddress C0 is not trnsmitted on the CA bus, nd is implied to be zero. 11. AB "high"during Prechrge commnd indictes tht ll bnk Prechrge will occur. In this cse, Bnk Address is do-not-cre. 12. When CS_n is HIGH, LPDDR3 CA bus cn be floted. Rev 1.2 / Jul

30 CKE TRUTH TABLE Current Stte 3 CKE n-1 4 CKE n 4 CS_n 5 Commnd n 6 Opertion n 6 Next Stte Notes Active Power Down Idl Power Down Resetting Power Down Self Refresh L L X X Mintin Active Power Down Active Powe Down L H H NOP Exit Active Power Down Active 7 L L X X Mintin Idle Power Down Idle Power Down L H H NOP Exit Idle Power Down Idle 7 L L X X Mintin Resetting Power Down Resetting Power Down L H H NOP Exit Resetting Power Down Idle or Resetting 7,9 L L X X Mintin Self Refresh Self Refresh L H H NOP Exit Self Refresh Idle 8 Bnk(s) Active H L H NOP All Bnks Idle H L H NOP H L L Enter Self Refresh Resetting H L H NOP Enter Active Power Down Enter Idle Power Down Enter Self Refresh Enter Resetting Power Down H H Refer to the Commnd Truth Tble Active Power- Down Idle Power Down Self Refresh Resetting Power Down 1. All sttes nd sequences not shown re illegl or reserved unless explicitly described elsewhere in this document. 2. 'X' mens 'Don't cre'. 3. "Current stte" is the stte of the LPDDR3 device immeditely prior to clock edge n. 4. "CKEn" is the logic stte of CKE t clock rising edge n; "CKEn-1" ws the stte of CKE t the previous clock edge. 5. "CS_n" is the logic stte of CS_n t the clock rising edge n. 6. "Commnd n" is the commnd registered t clock edge N, nd "Opertion n" is result of "Commnd n". 7. Power Down exit time (txp) should elpse before commnd other thn NOP is issued. The clock must toggle t lest twice during the txp period. 8. Self-Refresh exit time (txsr) should elpse before commnd other thn NOP is issued. The clock must toggle t lest twice during the txsr time. 9. Upon exiting Resetting Power Down, the device will return to the Idle stte if tinit5 hs expired. 10. In the cse of ODT disbled, ll DQ output shll be Hi-Z. In the cse of ODT enbled, ll DQ shll be terminted to VDDQ. 10 Rev 1.2 / Jul

31 Current Stte Bnk n - Commnd to Bnk n Current Stte Commnd Opertion Next Stte Note Any NOP Continue previous opertion Current Stte Activte Select nd ctivte row Active Refresh (Per Bnk) Begin to refresh Refreshing (Per Bnk) 6 Refresh (All Bnk) Begin to refresh Refreshing (All Bnk) 7 Idle MRW Write vlue to Mode Register MR Writing 7 MRR Red vlue from Mode Register Idle MR Reding Reset Begin Device Auto-Initiliztion Resetting 8 Prechrge Dective row in bnk or bnks Prechrging 9, 12 Red Select Column, nd strt red burst Reding Row Active Write Select Column, nd strt write burst Writing MRR Red vlue from Mode Register Active MR Reding Prechrge Dectivte row in bnk or bnks Prechrging 9 Select column, nd strt new red Red Reding burst Reding 10,11 Write Select column, nd strt write burst Writing 10,11,13 Select Column, nd strt new write Write Writing burst Writing 10,11 Red Select column, nd strt red burst Reding 10,11,14 Power On Reset Begin Device Auto-Initiliztion Resetting 7, 9 Resetting MRR Red vlue from Mode Register Resetting MR Reding 1. The tble pplies when both CKE n-1 nd CKE n re HIGH, nd fter txsr or txp hs been met if the previous stte ws Power Down. 2. All sttes nd sequences not shown re illegl or reserved. 3. Current Stte Definitions: Idle: The bnk or bnks hve been prechrged, nd trp hs been met. Row Active: A row in the bnk hs been ctivted, nd trcd hs been met. No dt bursts / ccesses nd no register ccesses re in progress. Reding: A READ burst hs been initited, with Auto Prechrge disbled. Writing: A WRITE burst hs been initited, with Auto Prechrge disbled. 4. The following sttes must not be interrupted by commnd issued to the sme bnk. NOP commnds or llowble commnds to the other bnk should be issued on ny clock edge occurring during these sttes. Allowble commnds to the other bnks re determined by its current stte nd Tble Current Stte Bnk n - Commnd to Bnk n, nd ccording to Tble Current Stte Bnk n - Commnd to Bnk m. Prechrging: strts with the registrtion of PRECHARGE commnd nd ends when trp is met. Once trp is met, the bnk will be in the idle stte. Row Activting: strts with registrtion of n ACTIVE commnd nd ends when trcd is met. Once trcd is met, the bnk will be in the Active stte. Red with AP Enbled: strts with the registrtion of the READ commnd with Auto Prechrge enbled nd ends when trp hs been met. Once trp hs been met, the bnk will be in the idle stte. Write with AP Enbled: strts with registrtion of WRITE commnd with Auto Prechrge enbled nd ends when trp hs been met. Once trp is met, the bnk will be in the idle stte. 5. The following sttes must not be interrupted by ny executble commnd; NOP commnds must be pplied to ech positive clock edge during these sttes. Refreshing (Per Bnk): strts with registrtion of REFRESH (Per Bnk) commnd nd ends when trfcpb is met. Once trfcpb is met, the bnk will be in n idle stte. Refreshing (All Bnk): strts with registrtion of REFRESH(All Bnk) commnd nd ends when trfcb is met. Once trfcb is met, the device will be in n ll bnks idle stte. Idle MR Reding: strts with the registrtion of MRR commnd nd ends when tmrr hs been met. Once tmrr hs been met, the bnk will be in the Idle stte. Resetting MR Reding: strts with the registrtion of MRR commnd nd ends when tmrr hs been met. Once tmrr hs been met, the bnk will be in the Resetting stte. Rev 1.2 / Jul

32 Active MR Reding: strts with the registrtion of MRR commnd nd ends when tmrr hs been met. Once tmrr hs been met, the bnk will be in the Row Active stte. MR Writing: strts with the registrtion of MRW commnd nd ends when tmrw hs been met. Once tmrw hs been met, the bnk will be in the Idle stte. Prechrging All: strts with the registrtion of PRECHARGE ALL commnd nd ends when trp is met. Once trp is met, the bnk will be in the idle stte. 6. Bnk-specific; requires tht the bnk is idle nd no bursts re in progress. 7. Not bnk-specific; requires tht ll bnks re idle nd no bursts re in progress. 8. Not bnk-specific reset commnd is chieved through MODE REGISTER WRITE commnd. 9. This commnd my or my not be bnk specific. If ll bnks re being prechrged, they must be in vlid stte for prechrging. 10. A commnd other thn NOP should not be issued to the sme bnk while READ or WRITE burst with Auto Prechrge is enbled. 11. The new Red or Write commnd could be Auto Prechrge enbled or Auto Prechrge disbled. 12. If Prechrge commnd is issued to bnk in the Idle stte, trp shll still pply. 13. A Write commnd my be pplied fter the completion of the Red burst, burst termintes re not permitted. 14. A Red commnd my be pplied fter the completion of the Write burst, burst termintes re not permitted. Rev 1.2 / Jul

33 Current Stte Bnk n - Commnd to Bnk m Current Stte of Bnk n Commnd for Bnk m Opertion Next Stte for Bnk m Note Any NOP Continue previous opertion Current Stte of Bnk m Idle Any Any commnd llowed to Bnk m - Row Activting, Active, or Prechrging Reding (Autoprechrge disbled) Writing (Autoprechrge disbled) Reding with Autoprechrge Activte Select nd ctivte row in Bnk m Active 6 Red Select column, nd strt red burst from Bnk m Reding 7 Write Select column, nd strt write burst to Bnk m Writing 7 Prechrge Dectivte row in bnk or bnks Prechrging 8 MRR Red vlue from Mode Register Idle MR Reding or Active MR Reding 9,10,12 Red Select column, nd strt red burst from Bnk m Reding 7 Write Select column, nd strt write burst to Bnk m Writing 7,15 Activte Select nd ctivte row in Bnk m Active Prechrge Dectivte row in bnk or bnks Prechrging 8 Red Select column, nd strt red burst from Bnk m Reding 7,16 Write Select column, nd strt write burst to Bnk m Writing 7 Activte Select nd ctivte row in Bnk m Active Prechrge Dectivte row in bnk or bnks Prechrging 8 Red Select column, nd strt red burst from Bnk m Reding 7,13 Write Select column, nd strt write burst to Bnk m Writing 7,15,13 Activte Select nd ctivte row in Bnk m Active Prechrge Dectivte row in bnk or bnks Prechrging 8 Red Select column, nd strt red burst from Bnk m Reding 7,13,16 Writing with Write Select column, nd strt write burst to Bnk m Writing 7,13 Autoprechrge Activte Select nd ctivte row in Bnk m Active Prechrge Dectivte row in bnk or bnks Prechrging 8 Power On Reset Begin Device Auto-Initiliztion Resetting 11, 14 Resetting MRR Red vlue from Mode Register Resetting MR Reding 1. The tble pplies when both CKE n-1 nd CKE n re HIGH, nd fter txsr or txp hs been met if the previous stte ws Self Refresh or Power Down. 2. All sttes nd sequences not shown re illegl or reserved. 3. Current Stte Definitions: Idle: the bnk hs been prechrged, nd trp hs been met. Active: row in the bnk hs been ctivted, nd trcd hs been met. No dt bursts/ccesses nd no register ccesses re in progress. Reding: READ burst hs been initited, with Auto Prechrge disbled. Writing: WRITE burst hs been initited, with Auto Prechrge disbled. 4. REFRESH, SELF REFRESH, nd MODE REGISTER WRITE commnds my only be issued when ll bnk re idle. 5. The following sttes must not be interrupted by ny executble commnd; NOP commnds must be pplied during ech clock cycle while in these sttes: Idle MR Reding: strts with the registrtion of MRR commnd nd ends when tmrr hs been met. Once tmrr hs been met, the bnk will be in the Idle stte. Resetting MR Reding: strts with the registrtion of MRR commnd nd ends when tmrr hs been met. Once tmrr hs been met, the bnk will be in the Resetting stte. Active MR Reding: strts with the registrtion of MRR commnd nd ends when tmrr hs been met. Once tmrr hs been met, the bnk will be in the Row Active stte. MR Writing: strts with the registrtion of MRW commnd nd ends when tmrw hs been met. Once tmrw hs been met, the bnk will be in the Idle stte. 6. trrd must be met between Activte commnd to Bnk n nd subsequent Activte commnd to Bnk m. Rev 1.2 / Jul

34 7. READs or WRITEs listed in the Commnd column include READs nd WRITEs with Auto Prechrge enbled nd READs nd WRITEs with Auto Prechrge disbled. 8. This commnd my or my not be bnk specific. If ll bnks re being prechrged, they must be in vlid stte for prechrging. 9. MRR is llowed during the Row Activting stte nd MRW is prohibited during the Row Activting stte. (Row Activting strts with registrtion of n Activte commnd nd ends when trcd is met.) 10. MRR is llowed during the Prechrging stte. (Prechrging strts with registrtion of Prechrge commnd nd ends when trp is met. 11. Not bnk-specific; requires tht ll bnks re idle nd no bursts re in progress. 12. The next stte for Bnk m depends on the current stte of Bnk m (Idle, Row Activting, Prechrging, or Active). The reder shll note tht the stte my be in trnsition when MRR is issued. Therefore, if Bnk m is in the Row Activting stte nd Prechrging, the next stte my be Active nd Prechrge dependent upon trcd nd trp respectively. 13. Red with uto prechrge enbled or Write with uto prechrge enbled my be followed by ny vlid commnd to other bnks provided tht the timing restrictions in the section of Prechrge nd Auto Prechrge clrifiction re followed. 14. Reset commnd is chieved through MODE REGISTER WRITE commnd. 15. A Write commnd my be pplied fter the completion of the Red burst, burst termintes re not permitted. 16. A Red commnd my be pplied fter the completion of the Write burst, burst termintes re not permitted. Rev 1.2 / Jul

35 DATA MASK TRUTH TABLE Function DM DQ Note Write Enble L Vlid 1 Write Inhibit H X 1 1. Used to msk write dt, provided coincident with the corresponding dt. Rev 1.2 / Jul

36 Absolute Mximum DC Rtings Stresses greter thn those listed my cuse permnent dmge to the device. This is stress rting only, nd functionl opertion of the device t these or ny other conditions bove those indicted in the opertionl sections of this specifiction is not implied. Exposure to bsolute mximum rting conditions for extended periods my ffect relibility. Prmeter Symbol Min Mx Unit Notes VDD1 supply voltge reltive to VSS VDD V 1 VDD2 supply voltge reltive to VSS VDD V 1 VDDCA supply voltge reltive to VSSCA VDDCA V 1, 2 VDDQ supply voltge reltive to VSSQ VDDQ V 1, 3 Voltge on Any Pin reltive to VSS VIN, VOUT V Storge Temperture TSTG o C 4 1.See the section Power-up, Initiliztion, nd Power-off for reltionships between power supplies. 2. VREFCA 0.6 x VDDCA; however, VREFCA my be VDDCA provided tht VREFCA 300mV. 3. VREFDQ 0.7 x VDDQ; however, VREFDQ my be VDDQ provided tht VREFDQ 300mV. 4. Storge Temperture is the cse surfce temperture on the center/top side of the device. For the mesurement conditions, plese refer to JESD51-2 stndrd. Rev 1.2 / Jul

37 AC nd DC Operting Conditions Opertion or timing tht is not specified is illegl, nd fter such n event, in order to gurntee proper opertion, the LPDDR3 Device must be powered down nd then restrted through the specilized initiliztion sequence before norml opertion cn continue. Recommended DC Operting Conditions Prmeter Symbol Min Typ Mx Unit Core Power 1 VDD V Core Power 2 VDD V Input Buffer Power VDDCA V I/O Buffer Power VDDQ V Note : 1. VDD1 uses significntly less current thn VDD2. 2. The voltge rnge is for DC voltge only. DC is defined s the voltge supplied t the DRAM nd is inclusive of ll noise up to 1MHz t the DRAM pckge bll. Input Lekge Current Prmeter Symbol Min Mx Unit Note Input Lekge current IL -2 2 ua 2 VREF supply lekge current IVREF -1 1 ua 1 1. For CA, CKE, CS_n, CK_t, CK_c. Any input 0V VIN VDDCA(All other pins not under test = 0V) 2. Although DM is for input only, the DM lekge shll mtch the DQ nd DQS_t/DQS_c output lekge specifiction. 3. The minimum limit requirement is for testing purposes. The lekge current on VREFCA nd VREFDQ pins should be miniml. 4. VREFDQ = VDDQ/2 or VREFCA = VDDCA/2. (All other pins not under test = 0V) Operting Temperture Prmeter Symbol Min Mx Unit Note Operting Temperture Stndrd T 1 OPER C Extended Operting Temperture is the cse surfce temperture on the center-top side of the LPDDR3 device. For the mesurement conditions, plese refer to JESD51-2 stndrd. 2. Some pplictions require opertion of LPDDR3 in the mximum temperture conditons in the Extended Temperture Rnge between -30 C nd 105 C cse temperture. For LPDDR3 devices, derting my be neccessry to operte in this rnge. See MR4 on the section "Mode Register". 3. Either the device cse temperture rting or the temperture sensor (See the section of "Temperture Sensor") my be used to set n pproprite refresh rte, determine the need for AC timing de-rting nd/or monitor the operting temperture. When using the temperture sensor, the ctul device cse temperture my be higher thn the TOPER rting tht pplies for the Stndrd or Elevted Temperture Rnges. For exmple, TCASE my be bove 85 C when the temperture sensor indictes temperture of less thn 85 C. Rev 1.2 / Jul

38 AC nd DC Input Mesurement Levels AC nd DC Logic Input Levels for Single-Ended CA nd CS_n Signls Prmeter Symbol LPDDR LPDDR3 1600/1333 Min Mx Min Mx Unit Note AC Input Logic High VIHCA VREF Note 2 VREF Note 2 V 1,2 AC Input Logic Low VILCA Note 2 VREF Note 2 VREF V 1,2 DC Input Logic High VIHCA VREF VDDCA VREF VDDCA V 1 DC Input Logic Low VILCA VSSCA VREF VSSCA VREF V 1 Reference Voltge for VREFCA(DC) 0.49 * VDDCA 0.51 * VDDCA 0.49 * VDDCA 0.51 * VDDCA V 3,4 CA nd CS_n Inputs 1. For CA nd CS_n input only pins. VREF = VREFCA(DC). 2. See the section Overshoot nd Undershoot Specifictions. 3. The c pek noise on VREFCA my not llow VREFCA to devite from VREFCA(DC) by more thn +/-1% VDDCA (for reference: pprox. +/- 12 mv). 4. For reference: pprox. VDDCA/2 +/- 12 mv. AC nd DC Logic Input Levels for CKE Prmeter Symbol Min Mx Unit Note CKE Input High Level VIHCKE 0.65 * VDDCA Note 1 V 1 CKE Input Low Level VILCKE Note * VDDCA V 1 1. See the section Overshoot nd Undershoot Specifictions. AC nd DC Logic Input Levels for Single-Ended Dt (DQ nd DM) Signls Prmeter Symbol LPDDR LPDDR3 1600/1333 Min Mx Min Mx Unit Note AC Input High Voltge VIHDQ VREF Note 2 VREF Note 2 V 1,2 AC Input Low Voltge VILDQ Note 2 VREF Note 2 VREF V 1,2 DC Input High Voltge VIHDQ VREF VDDCA VREF VDDQ V 1 DC Input Low Voltge VILDQ VSSCA VREF VSSCA VREF V 1 Reference Voltge for DQ nd DM Inputs Reference Voltge for DQ nd DM Inputs VREFDQ(DC) (DQ ODT disbled) VREFDQ(DC) (DQ ODT enbled) 0.49 * VDDQ 0.51*VDDQ 0.49 * VDDQ 0.51*VDDQ V 3,4 VODTR/2-0.01*VDDQ VODTR/ *VDDQ 0.5 * Vodtr * VDDQ 0.5 * Vodtr * VDDQ V 3,5,6 1. For DQ input only pins. VREF = VREFDQ(DC). 2. See the section of Overshoot nd Undershoot Specifictions. 3. The c pek noise on VREFDQ my not llow VREFDQ to devite from VREFDQ(DC) by more thn +/-1% VDDQ (for reference: pprox. +/- 12 mv). 4. For reference: pprox. VDDQ/2 +/- 12 mv. 5. For reference: pprox. VODTR/2 +/- 12 mv. 6. The nominl mode register progrmmed vlue for RODT nd the nominl controller output impednce RON re used for the clcultion of VODTR. For testing purposes controller RON vlue of 50 Ω is used. Vodtr = (2 * RON + RTT) / (RON + RTT) * VDDQ Rev 1.2 / Jul

39 VREF Tolernces The dc-tolernce limits nd c-noise limits for the reference voltges VREFCA nd VREFDQ re illustrted in Figure below. It shows vlid reference voltge VREF(t) s function of time. (VREF stnds for VREFCA nd VREFDQ likewise). VDD stnds for VDDCS for VREFCA nd VDDQ for VREFDQ. VREF(DC) is the liner verge of VREF(t) over very long period of time (e.g. 1 sec) nd is specified s frction of the liner verge of VDDCA or VDDQ lso over very long period of time (e.g. 1 sec). This verge hs to meet the min/mx requirements in Tble Electricl Chrcteristics nd Operting Conditions. Furthermore VREF(t) my temporrily devite from VREF(DC) by no more thn +/- 1% VDD. VREF(t) cnnot trck noise on VDDQ or VDDCA if this would send VREF outside these specifictions. voltge VDD V REF c-noise V REF (t) V REF(DC) V REF(DC)mx VDD/2 V REF(DC)min VSS time Figure. Illustrtion of VREF(DC) tolernce nd VREF c-noise limits The voltge levels for setup nd hold time mesurements VIH(AC), VIH(DC), VIL(AC) nd VIL(DC) re dependent on VREF. "VREF " shll be understood s VREF(DC), s defined in Figure bove. This clrifies tht dc-vritions of VRef ffect the bsolute voltge signl hs to rech to chieve vlid high or low level nd therefore the time to which setup nd hold is mesured. System timing nd voltge budgets need to ccount for VREF(DC) devitions from the optimum position within the dt-eye of the input signls. This lso clrifies tht the LPDDR3 setup/hold specifiction nd derting vlues need to include time nd voltge ssocited with VREF c-noise. Timing nd voltge effects due to c-noise on VREF up to the specified limit (+/-1% of VDD) re included in LPDDR3 timings nd their ssocited dertings. Rev 1.2 / Jul

40 Input Signl Figure. LPDDR3 Input signl 1. Numbers reflect nominl vlues. 2. For CA0-9, CK_t, CK_c nd CS_n, VDD stnds for VDDCA. For DQ, DM/DNV, DQS_t nd DQS_c, VDD stnds for VDDQ. 3. For CA0-9, CK_t, CK_c nd CS_n, VSS stnds for VSSCA. For DQ, DM/DNV, DQS_t nd DQS_c, VSS stnds for VSSQ. Rev 1.2 / Jul

41 AC nd DC Logic Input Levels for Differentil Signls Differentil Signl Definition differentil t DVAC voltge V IHDIFF(AC) MIN V IHDIFF(DC) MIN 0.0 CK_t - CK_c DQS_t - DQS_c V ILDIFF(DC) MAX V ILDIFF(AC) MAX hlf cycle t DVAC Figure. Definition of differentil c-swing nd Time bove c-level tdvac time Rev 1.2 / Jul

42 Differentil swing requirements for clock nd strobe Prmeter Symbol Min Mx Unit Note DC Differentil Input High VIHDIFF(DC) 2 x (VIH(DC) - VREF) Note 3 V 1 DC Differentil Input Low VILDIFF(DC) Note 3 2 x (VIL(DC) - VREF) V 1 AC Differentil Input High VIHDIFF(AC) 2 x (VIH(AC) - VREF) Note 3 V 2 AC Differentil Input Low VILDIFF(AC) Note 3 2 x (VIL(AC) - VREF) V 2 1. Used to define differentil signl slew-rte. For CK_t - CK_c use VIH/VIL(dc) of CA nd VREFCA; for DQS_t - DQS_c, use VIH/ VIL(dc) of DQs nd VREFDQ; if reduced dc-high or dc-low level is used for signl group, then the reduced level pplies lso here. 2. For CK_t - CK_c use VIH/VIL(c) of CA nd VREFCA; for DQS_t - DQS_c, use VIH/VIL(c) of DQs nd VREFDQ; if reduced c-high or c-low level is used for signl group, then the reduced level pplies lso here. 3. These vlues re not defined, however the single-ended signls CK_t, CK_c, DQS_t, nd DQS_c need to be within the respective limits (VIH(dc) mx, VIL(dc)min) for single-ended signls s well s the limittions for overshoot nd undershoot. Refer to the section of Overshoot nd Undershoot Specifictions. 4. For CK_t nd CK_c, Vref = VrefCA(DC). For DQS_t nd DQS_c, Vref = VrefDQ(DC). Tble. Allowed time before ringbck (tdvac) for DQS_t - DQS_c Slew Rte [V/ns] t DVAC VIH/Ldiff(c) = 270mV t DVAC VIH/Ldiff(c) = 300mV t DVAC VIH/Ldiff(c) = 300mV 1866Mbps 1600Mbps 1333Mbps MIN MIN MIN > < Tble. Allowed time before ringbck (tdvac) for CK_t - CK_c Slew Rte [V/ns] t DVAC VIH/Ldiff(c) = 270mV t DVAC VIH/Ldiff(c) = 300mV t DVAC VIH/Ldiff(c) = 300mV 1866Mbps 1600Mbps 1333Mbps MIN MIN MIN > < Rev 1.2 / Jul

43 Single-ended Requirements for Differentil Signls Ech individul component of differentil signl (CK_t, DQS_t, CK_c, or DQS_c) hs lso to comply with certin requirements for single-ended signls. CK_t nd CK_c shll meet VSEH(AC)min / VSEL(AC)mx in every hlf-cycle. DQS_t, DQS_c shll meet VSEH(AC)min / VSEL(AC)mx in every hlf-cycle proceeding nd following vlid trnsition. Note tht the pplicble c-levels for CA nd DQ's re different per speed-bin. VDDCA or VDDQ VSEH(AC)min VDDCA/2 or VDDQ/2 VSEH(AC) CK_t, CK_c DQS_t, or DQS_c VSEL(AC)mx VSSCA or VSSQ Figure. Single-ended requirement for differentil signls VSEL(AC) time Note tht while CA nd DQ signl requirements re with respect to VREF, the single-ended components of differentil signls hve requirement with respect to VDDQ/2 for DQS_t, DQS_C nd VDDCA/2 for CK_t, CK_c; this is nominlly the sme. The trnsition of single-ended signls through the c-levels is used to mesure setup time. For single-ended components of differentil signls the requirement to rech VSEL(AC)mx, VSEH(AC)min hs no bering on timing, but dds restriction on the common mode chrcteristics of these signls. Rev 1.2 / Jul

44 Tble. Single-ended Levels for Clock nd Strobe Prmeter Symbol Min Mx Unit Note Single-ended High Level for strobes (VDDQ/2) Note 3 V 1, 2 VSEH Single-ended High Level for CK_t nd (AC150) (VDDCA/2) Note 3 V 1, 2 CK_c Single-ended Low Level for strobes Single-ended Low Level for CK_t nd CK_c Single-ended High Level for strobes Single-ended High Level for CK_t nd CK_c Single-ended Low Level for strobes Single-ended Low Level for CK_t nd CK_c VSEL (AC150) VSEH (AC135) VSEL (AC135) Note 3 (VDDQ / 2) V 1, 2 Note 3 (VDDCA / 2) V 1, 2 (VDDQ/2) Note 3 V 1, 2 (VDDCA/2) Note 3 V 1, 2 Note 3 (VDDQ / 2) V 1, 2 Note 3 (VDDCA / 2) V 1, 2 1. For CK_t, CK_c use VSEH/VSEL(AC) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is bsed on VREFDQ; VSEH(AC)/VSEL(AC) for CA is bsed on VREFCA; if reduced c-high or c-low level is used for signl group, then the reduced level pplies lso here. 3. These vlues re not defined, however the single-ended signls CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c need to be within the respective limits (VIH(DC) mx, VIL(DC)min) for single-ended signls s well s the limittions for overshoot nd undershoot. Refer to the section of Overshoot nd Undershoot Specifictions. Rev 1.2 / Jul

45 Differentil Input Cross Point Voltge To gurntee tight setup nd hold times s well s output skew prmeters with respect to clock nd strobe, ech cross point voltge of differentil input signls (CK_t, CK_c nd DQS_t, DQS_c) must meet the requirements in Single-ended Levels for Clock nd Strobe. The differentil input cross point voltge VIX is mesured from the ctul cross point of true nd complement signls to the midlevel between of VDD nd VSS. VDDCA or VDDQ CK_c, DQS_c V IX VDDCA/2 or VDDQ/2 V IX V IX CK_t, DQS_t VSSCA or VSSQ Figure. VIX definition Tble. Cross Point Voltge for Differentil Input Signls (Clock nd Strobe) Prmeter Symbol Min Mx Unit Note Differentil Input Cross Point Voltge reltive to VDDCA/2 for CK_t nd CK_c VIXCA mv 1, 2 Differentil Input Cross Point Voltge reltive to VDDQ/2 for DQS_t nd DQS_c VIXDQ mv 1, 2 1. The typicl vlue of VIX(AC) is expected to be bout 0.5 x VDD of the trnsmitting device, nd VIX(AC) is expected to trck vritions in VDD. VIX(AC) indictes the voltge t which differentil input signls must cross. 2. For CK_t nd CK_c, VREF = VREFCA(DC). For DQS_t nd DQS_c, VREF = VREFDQ(DC). Rev 1.2 / Jul

46 Slew Rte Definitions for Single-ended Input Signls See "CA nd CS_n Setup, Hold nd Derting" for single-ended slew rte definitions for ddress nd commnd signls. See "Dt Setup, Hold nd Slew Rte Derting" for single-ended slew rte definitions for dt signls. Slew Rte Definitions for Differentil Input Signls Input slew rte for differentil signls (CK_t, CK_c nd DQS_t, DQS_c) re defined nd mesured s shown in the tble nd figure below. Prmeter Differentil Input Slew Rte for Rising Edge (CK_t - CK_c nd DQS_t - DQS_c) Differentil Input Slew Rte for Flling Edge (CK_t - CK_c nd DQS_t - DQS_c) Tble. Differentil Input Slew Rte Definition Mesured From To Defined by V ILdiffmx V IHdiffmin [V IHdiffmin - V ILdiffmx ] / Delt TRdiff V IHdiffmin V ILdiffmx [V IHdiffmin - V ILdiffmx ] / Delt TFdiff 1. The differentil signl (i.e. CK_t - CK_c nd DQS_t - DQS_c) must be liner between these thresholds. Differentil Input Voltge (i.e. CK_t - CK_c, DQS_t - DQS_c) Delt TRdiff V IHdiffmin 0 V ILdiffmx Delt TFdiff Figure. Differentil Input Slew Rte Definition for CK_t, CK_c nd DQS_t, DQS_c Rev 1.2 / Jul

47 AC nd DC Output Mesurement Levels Single Ended AC nd DC Output Levels Prmeter Symbol Levels Unit Note DC Output Logic High Mesurement Level (for IV curve linerity) VOH(DC) 0.9 x VDDQ V 1 VOL(DC) ODT 0.1 x VDDQ V 2 DC Output Logic Low Mesurement Level (for IV curve linerity) disbled VOL(DC) VDDQ * [ ODT * (RON/ V 3 enbled (RTT+RON))] AC Output Logic High Mesurement Level (for output slew rte) VOH(AC) VREFDQ V AC Output Logic Low Mesurement Level (for output slew rte) VOL(AC) VREFDQ V Output Lekge current (DQ, DM, DQS_t nd DQS_c) Min -5 ua I (DQ, DQS_t nd DQS_c re disbled; 0V VOUT VDDQ) OZ Mx 5 ua Delt RON between pull-up nd pull-down for DQ nd DM Min -15 % MM PUPD Mx 15 % 1. IOH = -0.1mA, 2. IOL = 0.1mA 3. The min vlue is derived when using RTT, min nd RON,mx (+/- 30% unclibrted, +/-15% clibrted). Differentil AC nd DC Output Levels (DQS_t, DQS_c) Prmeter Symbol Levels Unit Note AC Differentil Output High mesurement Level (for Output SR) VOHdiff(AC) x VDDQ V AC Differentil Output Low mesurement Level (for Output SR) VOLdiff(AC) x VDDQ V 1. IOH = -0.1mA, 2. IOL = 0.1mA Rev 1.2 / Jul

48 Single Ended Output Slew Rte With the reference lod for timing mesurements, output slew rte for flling nd rising edges is defined nd mesured between VOL(AC) nd VOH(AC) for single ended signls s shown in below Tble nd Figure. Prmeter Mesured From To Defined by Single Ended Output Slew Rte for Rising Edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)] / Delt TRse Single Ended Output Slew Rte for Flling Edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)] / Delt TFse Output slew rte is verified by design nd chrcteriztion nd my not be subject to production test. Delt TRse Single Ended Output Voltge (i.e. DQ) V OH(AC) V REF V OL(AC) Delt TFse Figure. Single Ended Output Slew Rte Definition Tble. Output Slew Rte (Single Ended) Prmeter Symbol Min Mx Unit Note Single-ended Output Slew Rte (RON = 40 +/- 30%) SRQse V/ns Output slew-rte mtching Rtio (Pull-up to Pull-down) Description: SR: Slew Rte Q: Query Output (like in DQ, which stnds for Dt-in, Query-Output) se: Single-ended Signls 1. Mesured with output reference lod. 2. The rtio of pull-up to pull-down slew rte is specified for the sme temperture nd voltge, over the entire temperture nd voltge rnge. For given output, it represents the mximum difference between pull-up nd pull-down drivers due to process vrition. 3. The output slew rte for flling nd rising edges is defined nd mesured between VOL(AC) nd VOH(AC). 4. Slew rtes re mesured under verge SSO conditions, with 50% of DQ signls per dt byte switching. Rev 1.2 / Jul

49 Differentil Output Slew Rte With the reference lod for timing mesurements, output slew rte for flling nd rising edges is defined nd mesured between VOLdiff(AC) nd VOHdiff(AC) for differentil signls s shown in below Tble nd Figure. Prmeter Mesured From To Defined by Differentil Output Slew Rte for Rising Edge V OLdiff(AC) V OHdiff(AC) [V OHdiff(AC) - V OLdiff(AC) ] / Delt TRdiff Differentil Output Slew Rte for Flling Edge V OHdiff(AC) V OLdiff(AC) [V OHdiff(AC) - V OLdiff(AC) ] / Delt TFdiff 1. Output slew rte is verified by design nd chrcteriztion, nd my not be subject to production test. Differentil Output Voltge (i.e. DQS_t - DQS_c) Delt TRdiff V OHdiff(AC) 0 V OLdiff(AC) Delt TFdiff Figure. Differentil Output Slew Rte Definition Tble. Output Slew Rte (Differentil) Prmeter Symbol Min Mx Unit Note Differentil Output Slew Rte (RON = 40 +/- 30%) SRQdiff V/ns Description: SR: Slew Rte Q: Query Output (like in DQ, which stnds for Dt-in, Query-Output) diff: Differentil Signls 1. Mesured with output reference lod. 2. The output slew rte for flling nd rising edges is defined nd mesured between VOL(AC) nd VOH(AC). 3. Slew rtes re mesured under verge SSO conditions, with 50% of DQ signls per dt byte switching. Rev 1.2 / Jul

50 Overshoot nd Undershoot Specifictions Prmeter Unit Mximum pek mplitude llowed for overshoot re 0.35 V Mximum pek mplitude llowed for undershoot re 0.35 V Mximum overshoot re bove VDD V-ns Mximum undershoot re below VSS V-ns Mximum Amplitude Overshoot Are Volts (V) VDD VSS Undershoot Are Time (ns) Figure. Overshoot nd Undershoot Definition 1. VDD stnds for VDDCA for CA0-9, CK_t, CK_c, CS_n, nd CKE. VDD stnds for VDDQ for DQ, DM, ODT, DQS_t, nd DQS_c. 2. VSS stnds for VSSCA for CA0-9, CK_t, CK_c, CS_n, nd CKE. VSS stnds for VSSQ for DQ, DM, ODT, DQS_t, nd DQS_c. 3. Absolute mximum requirements pply. 4. Mximum pek mplitude vlues re referenced from ctul VDD nd VSS vlues. 5. Mximum re vlues re referenced from mximum operting VDD nd VSS vlues. Rev 1.2 / Jul

51 Output Buffer Chrcteristics HSUL_12 Driver Output Timing Reference Lod These Timing Reference Lods re not intended s precise representtion of ny prticulr system environment or depiction of the ctul lod presented by production tester. System designers should use IBIS or other simultion tools to correlte the timing reference lod to system environment. Mnufcturers correlte to their production test conditions, generlly one or more coxil trnsmission lines terminted t the tester electronics. VREF LPDDR3 SDRAM Output 0.5 x VDDQ RTT = 50 VTT = 0.5 x VDDQ Clod = 5pF 1. All output timing prmeter vlues (like t DQSCK, t DQSQ, t QHS, t HZ, t RPRE etc.) re reported with respect to this reference lod. This reference lod is lso used to report slew rte. Figure. HSUL_12 Driver Output Reference Lod for Timing nd Slew Rte RON PU nd RON PD resistor Definition Note 1: This is under the condition tht RON PD is turned off Note 1: This is under the condition tht RON PU is turned off Chip in Drive Mode Output Driver I PU VDDQ To other circuitry like RCV,... RON PU RON PD I Out DQ V Out I PD VSSQ Figure. Output Driver: Definition of Voltges nd Currents Rev 1.2 / Jul

52 RON PU nd RON PD Chrcteristics with ZQ Clibrtion Output driver impednce RON is defined by the vlue of the externl reference resistor RZQ. Nominl RZQ is Tble - Output Driver DC Electricl Chrcteristics with ZQ Clibrtion RON NOM Resistor Vout Min Typ Mx Unit Notes Mismtch between pull-up nd pull-down RON34PD 0.5 x VDDQ RZQ/7 1,2,3,4 RON34PU 0.5 x VDDQ RZQ/7 1,2,3,4 RON40PD 0.5 x VDDQ RZQ/6 1,2,3,4 RON40PU 0.5 x VDDQ RZQ/6 1,2,3,4 RON48PD 0.5 x VDDQ RZQ/5 1,2,3,4 RON48PU 0.5 x VDDQ RZQ/5 1,2,3,4 MM PUPD % 1,2,3,4,5 1. Across entire operting temperture rnge, fter clibrtion. 2. RZQ = The tolernce limits re specified fter clibrtion with fixed voltge nd temperture. For behvior of the tolernce limits if temperture or voltge chnges fter clibrtion, see following section on voltge nd temperture sensitivity. 4. Pull-down nd pull-up output driver impednces re recommended to be clibrted t 0.5 x VDDQ. 5. Mesurement definition for mismtch between pull-up nd pull-down, MMPUPD: Mesure RON PU nd RON PD, both t 0.5 x VDDQ: For exmple, with MMPUPD(mx) = 15% nd RONPD = 0.85, RONPU must be less thn Output driver strength mesured without ODT. Rev 1.2 / Jul

53 Output Driver Temperture nd Voltge Sensitivity If temperture nd/or voltge chnge fter clibrtion, the tolernce limits widen ccording to the Tbles shown below. Tble. Output Driver Sensitivity Definition Resistor Vout Min Mx Unit Notes RONPD RONPU 0.5 x VDDQ 85 - (drondt x T ) - (drondv x V ) (drondt x T ) + (drondv x V ) % 1,2 RTT 0.5 x VDDQ 85 - (drttdt x T ) - (drttdv x V ) (drttdt x T ) + (drttdv x V ) % 1,2 Note 1. T = T - T(@ clibrtion), V = V - V(@ clibrtion) 2. drondt nd drondv re not subject to production test but re verified by design nd chrcteriztion. Tble. Output Driver Temperture nd Voltge Sensitivity Symbol Prmeter Min Mx Unit drondt RON Temperture Sensitivity % / C drondv RON Voltge Sensitivity % / mv drttdt RTT Temperture Sensitivity % / C drttdv RTT Voltge Sensitivity % / mv RON PU nd RON PD Chrcteristics without ZQ Clibrtion Output driver impednce RON is defined by design nd chrcteriztion s defult setting. Tble. Output Driver DC Electricl Chrcteristics without ZQ Clibrtion RON NOM Resistor Vout Min Nom Mx Unit Notes (optionl) 80.0 (optionl) RON40PD 0.5 x VDDQ RON40PU 0.5 x VDDQ RON40PD 0.5 x VDDQ RON40PU 0.5 x VDDQ RON48PD 0.5 x VDDQ RON48PU 0.5 x VDDQ RON60PD 0.5 x VDDQ RON60PU 0.5 x VDDQ RON80PD 0.5 x VDDQ RON80PU 0.5 x VDDQ Across entire operting temperture rnge, without clibrtion. Rev 1.2 / Jul

54 RZQ I-V Curve Tble. RZQ I-V Curve RON = 240 (RZQ) Pull-Down Pull-Up Voltge(V) defult vlue fter ZQReset Current [ma] / RON [ ] with Clibrtion defult vlue fter ZQReset Current [ma] / RON [ ] with Clibrtion Min Mx Min Mx Min Mx Min Mx [ma] [ma] [ma] [ma] [ma] [ma] [ma] [ma] n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ n/ Rev 1.2 / Jul

55 Figure. I-V Curve After ZQ Reset Figure. I-V Curve After Clibrtion Rev 1.2 / Jul