IMPLEMENTATION OF DIGITAL FILTER ON FPGA FOR ECG SIGNAL PROCESSING

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1 IMPLEMENTATION OF DIGITAL FILTER ON FPGA FOR ECG SIGNAL PROCESSING Pramod R. Bokde Department of Electronics Engg. Priyadarshini Bhagwati College of Engg. Nagpur, India Nitin K. Choudhari Department of Electronics & Communication Priyadarshini Bhagwati College of Engg. Nagpur, India ABSTRACT Electrocardiogram (ECG) plays a key role in monitoring and diagnostic of the patients. Such popularity of ECG examination is based on its simplicity and non-invasiveness. ECG offers important information about health of patients and cardiologist are able to recognize different heart diseases from the morphology and position of the ECG components. However, most of the captured ECG signal will be distorted by the noise that is caused by the measurement instrument. Sometimes, the noise will totally mask the ECG signal, hence the signal is hard to be processed for further analysis. Hence it is a need to filter the ECG signals to avoid the failure detection of the signal. FIR digital filter is used to filter the noise in ECG signal. There are some advantages that the FIR filter is chosen. Due to all zero structures of FIR filter, it is guaranteed to be stable. FIR digital filter is simple to design and it has linear phase characteristics. This research aims for implementation option that satisfies the requirement on flexibility and portability such as speed enhancement and hardware cost. The research has achieved the target to filter the noise in ECG signal using a low pass filter. The output of the filter is compared with the ECG signal before filtering by plotting the signal in time domain and frequency domain using MATLAB. FIR serial architecture technique is used for the hardware design in order to minimize the hardware resource. However, the design tradeoffs for this hardware architecture is that it will results in higher delay due to serial of data computation. Hence, a future study of FIR linear phase characteristics can be carried out. KEYWORDS FIR filter, IIR filter, FPGA, Datapath unit, Control unit, etc INTRODUCTION Electrocardiogram (ECG) test and analysis is an important means to understand the functionality of heart, diagnosis of cardiovascular diseases and asses various treatments. The ECG in body surface has a strong random and background noise which is non-linear, non-stationary weak signal [2]. Threrfore ECG signals that being captured is usually distorted by noise. The two main noise that present in ECG signal are baseline wander noise (caused by breathing, movement and electrode contact of a person) and power line interface noise (caused by muscle contraction noise and monitoring equipment). The frequency range of baseline wander noise is below 0.5 Hz. Powerline interference noise about 50 Hz or 60 Hz will also distort the ECG signals. Sometimes ECG signal is totally distorted by powerline interference noise [3]. Hence the powerline interference noise must be removed before the signals are applied for future analysis. In signal processing filters play important role to remove unwanted signals such as noise or extract important features of the signals which lies in certain frequency range. Finite impulse response filter (FIR) and infinite impulse response (IIR) filter are the two major types of filters. The main difference between the two types of filter is that FIR filter does not have feedback while the IIR filter does have the feedback. In recent years,digital filters are widely used in electronic industries as they are easy to design. To implement digital filters, MATLAB is a common software tool used. There are many types of filters such as low pass filter, high pass filter, band pass filter and band stop filter. Due to all zero structures, FIR digital filter is very stable. Figure (1) below shows a basic block diagram of a basic filter. Input signal/ Unfiltered signal Digital Filter Filtered Signal Fig.1- Basic Block Diagram of filter Digital filters are programmable, hence it helps to reduce the design cycle and minimize the risk of design. Moreover, digital filters perform noiseless mathematical operations at each intermediate steps in transforming[1]. Digital filters are 175

2 extremely stable with respect to time and temperature and performs filtering of low frequency signals accurately[6]. It is essential to minimize the hardware resources used in FPGA. Having a lot of multiply units in digital filters it is not area efficient. Therefore, it is essential to filter the noise that exist in ECG signal and implement an optimized hardware in FPGA. FIR filters have following advantages over other digital filters : FIR digital filters are simple to design. In realization of FIR filters, direct form structures can be used as it is easy. FIR filters are guaranteed to be stable due to all zero structures and have linear phase. FIR filters also have low sensitivity to filter coefficient quantization errors which will ease in hardware implementation [6]. FIR digital filters can transmit all frequencies with the same amount of delay. Hence, there will be no phase distortion and the input signal will be delayed by a constant when it is transmitted to the output. A filter with constant group delay is highly desirable in the transmission of digital signal [7]. The architecture of series FIR filter only requires an adder, a multiplier and a delay unit. The designed hardware is very slow in terms of time taken for data computation. In other workds, this hardware architecture design will result in high critical delay to obtain the output. However, it is a good choice with respect to hardware efficiency. It requires less logic elements in the hardware implementation. Parallel low pass FIR filter with Serial adder connection The scope of this paper is to design a low pass filter that can remove the noise (above 45 Hz) in ECG signal using MATLAB. ECG signal is plotted in frequency domain to identify the noise. The signal that exist above 45 Hz are treated as noise. The designed low pass filter is implemented on ALTERA FPGA DE-2 Board. Software toll such as Quartus is used to design and implement the low pass FIR digital filter. HARDWARE ARCHITECTURE There are many ways to realize the FIR filter based on the design issues, latency, filter operation and area efficiency There are several methods to implement hardware architecture of FIR low pass digital fitler such as serial input serial output and parallel input serial output. Low pass Serial FIR filter architecture Fig. 3 Block diagram for FIR filter architecture with serial adder connection This hardware architecture design can process data in parallel way instead of processing one by one. But,with respect to hardware efficiency, it is really not cost-effective. If the designed filter has 50 th order filter, it requires approximate 51 multipliers, 51 adders and 51 registers. Hence in terms of hardware use, this design will require a lot of logic elements. In figure (3), it can be observed that all the adders are connected to the output of previous adder. The output obained at the output terminal is the sum of the output of all adders. This will result in high critical delay as well [3]. Parallel Low Pass FIR filter with Branch Tree Adder Connection Fig. 2 Block diagram of serial FIR filter architecture 176

3 Fig. 4 Block diagram of FIR filter with brach tree adder connection The input data will be passed in parallel form through the registers. Each of the input data will be multiplied by the filter coefficient and the output data is to sum up all the output from multiplier. By using the Branch Tree Adder connection, each adder will compute two outputs from multipliers and gives an output for next adder computation. The process will end when all the outputs are summed up. This design will really reduce the critical delay if compared to the serial FIR filter architecture as shown in figure (4) above. However the biggest challenge in implementing filters in hardware is to achieve a specified speed of data processing at minimum hardware cost [3]. In terms of hardware efficiency, this design is not really good as it requires more resources that will increase the cost of hardware implementation. X[n] is the input data, y[n] is the output data and f[0], f[1], f[2], f[l-2], f[l-1] are the unit impulse response. Based on the equation of FIR filter, a basic block diagram can be drawn. This is to simplify in the hardware architecture design. Advantages of Hardware Implementation of FIR Digital Filters on FPGA Field Programmable Gate Array (FPGA) is a good testing platform for evaluating and implementing signal processing algorithm due to its programmability, configurability, low cost, high logic density and high reliability [12][13]. In designing FIR digital filters, it requires a lot of multipliers, adders and registers. The multipliers and adders can be formed using the logical array. Since FPGA is a structured internal logic array and rich connection resources, it is very suitable for hardware realization on FIR digital filter. DESIGN METHODOLOGY Figure(5) shows the overall workflow for the methodology. The design of a digital filter involves five steps. Firstly, the filter specification is determined which includes the type of filter (low pass, band pass filter, high pass filter), sampling frequency, word length of the input data, pass band frequency and stop band frequency. Next will be the filter coefficient calculation. However to ease the flow, the filter coefficients can be obtained through MATLAB software tool. The third step is to convert the transfer function into a suitable filter structure. The next step is to analyze the finite word length effect. Due to hardware constraints, the filter coefficients must be quantized. Hence, the effect of quantizing the filter coefficients and input data using a fixed word length of the filter performance is analyzed. Finally, the last step is to write VHDK code for the designed filter and its functionality is tested. Fig. 6 Workflow for designing low pass FIR filter Realization of Filter Structure Block diagram can be used to represent the computational algorithm of a FIR filter. Multipliers, adders and registers are used to represent the basic building block diagram. The basic block elements and their equivalent signal flow diagram are shown in figure(7). Fig. 7 Structure of FIR filter of order L. 177

4 Conversion of Coefficient to Integer To design an ideal filter, it requires an infinite word length of filter coefficients. However, it is not possible to do so. Hence, an appropriate approach to solve this problem is to round off the filter coefficients to an X-bit representation[11]. In order to minimize the hardware used in this project, the filter coefficient will be quantized to 16 bit data. The filter coefficient has a 16-bit data width whereby the most significant bit denotes the sign of the data either it is positive or negative. The remained 15-bit is used for the magnitude of fraction. Since the coefficient number is in floating point format, it has to be converted to integer. The filter coefficients are converted and rounded off using MATLAB. In this design, the filter coefficients are shifted 15 bits to the right and rounded off using MATLAB to obtain the coefficient in integer form. HARDWARE IMPLEMENTAION FIR filter can be implemented by using an adder, a multiplier and registers. To optimize the hardware resources used, the number of multipliers is reduced. It is not area-efficient if using a lot of multipliers. For hardware implementation, if a designed filter has 50 oerders, it requires 51 multipliers for the computation. Implementing 51 multipliers in FPGA board is not an appropriate wayas it is not area-efficiency. Therefore, a circular buffer technique is proposed in this work to implement the hardware of FIR digital filter. Pseudo code for the FIR filter program using circular buffering 1. Update the RAM s address for the input signal s circular buffer. 2. Zero the accumulator 3. Update the ROM s address for the coefficient s circular buffer 4. Multiply the coefficient by the sample 5. Add the product to the accumulator 6. Repeat step 1 until all the input data is processed. The above pseudo code step is similar to the hardware design. The input data and coeffieicnt are stored in RAM and ROM respectively. The address of RAM and ROM will be updated when the arithmetic operation (multiplication and addition) is done. Then the next input data and coefficient will be computed. The process will continue untill all the input data are processed. of the filter. The filter coefficients will be quantized and rounded off through MATLAB. To ease the design, a register-transfer level (RTL) design method is used. Design of digital systems can be complex. In order to manage the complexity, a modular hierarchical approach is applied. At the top level of RTL design hierarchy, a digital system is usually divided into two units that known as control unit and datapath unit. The hardware design is then followed by interface designs that related to the signal interaction in between the Avalon Bus Memory Mapped and hardware of the FIR low pass filter. The designed hardware is tested in Quartus before it is downloaded into Altera FPGA DE2 Board for further analysis. FIR Low Pass Filter Design using MATLAB In figure(8) below, the ECG signal is plotted in both time domain and frequency domain. It is easier to analyze noise region of a signal by plotting it in the frequency domain. The ECG signal is filtered using the designed low pass FIR digital filter. Fig. 8 ECG signal with noise plotted in time domain and frequency domain SYSTEM DESIGN AND IMPLEMENTATION The goal of this work is to get the FIR low pass filter running on Altera DE-2 Board. In order to achieve this objective, FIR low pass filter design is devided into two main parts. Firstly, the filter is initially designed using MATLAB. The ECG signals are filtered using MATLAB to test the functionality Fig. 9 Filtered ECG signal using MATLAB Datapath Unit Design 178

5 The main function of datapath unit is performing the data processing and computation. The hardware design of FIR filter design can be deduced from equation 1. y[n] = a 0 x[n] +a 1 x[n-1] +. + a 49 x[n-49]. (1) It can be seen from equation 1, the FIR filter is multiplying and adding all the time. In order to design the datapath unit, a multiplier, an adder and registers are used to implement the FIR filter. Figure (10) shows a functional block diagram of the FIR filter. In this research, a ROM is used to store the flter coefficients as the values are always constant. For the ECG input data, a RAM with 16k word size is used. The signed adder and signed multiplier in this design are applied from the predefined module in Altera Quartus software. The size of width size for input data and coefficient is 16-bit respectively. But the width size for multiplier and adder will be 32-bit. The ECG signal is used to be filtered only contained 10-bit. Hence, the output registers with the 32-bit width is enough to overcome the overflow issue. Initially, the input data will be stored in RAM before any data computation starts. Counter 3 is a count up counter that used to accumulate the total amount of input data and determine whether all the input ECG data are computed. Once all the input data are ready, the start signal will be given to datapath unit to begin the data computation. The increment and decrement signal are applied to the appropriate counters in order to update the address of RAM and ROM. This is to ensure the data processing for ECG signals can continue. When one point of output data is completed it will be loaded into the outer registers. A done signal will be delivered if only if all the input data are computed or when the value of counter 3 s less than zero. Fig. 10- Functional Block diagram for serial FIR filter architecture Control Unit Design In order to determine the sequence of data processing operation performed by datapath unit, a control unit is needed. The control unit functions to deliver the control signals in specified order. For the FIR filter design, a datapath unit requires other logic elements together to control the sequence of data computation. A multiplexer, three counters and three comparators are needed. There are other external control signals such as start signal and load data signal to set up the control unit. Counters are used to count the the total number of input data and point the address of ROM and RAM. Comparators are used to determine in which situation the data processing should begin, stop or continue. The overall sequence for the FIR filter is given in figure (11). Fig. 11- ASM chart for FIR low pass filter design RESULT AND DISCUSSION The captured ECG signals contain the power line interface noise that lies in the range of 50 Hz or 60 Hz. This kind of noise normally is caused by the muscle contraction noise and measurement equipment. The present of noise will lead to 179

6 failure detection of the QRS complex. It is essential to remove the unwanted noise before the ECG signals can be applied for future use like analysis. Hardware implementation of FIR filter is to accelerate the filtering process. Unfiltered ECG signals are compared with the filtered ECG signals using MATLAB. The ECG signals are plotted both in the time domain and frequency domain. The ECG signals that are filtered through hardware are compared with the ECG signals filtered through MATLAB. Fig. 14- Filtered ECG signal using MATLAB Fig. 12- Raw ECG Signal Fig. 13 Filtered ECG signal using Altera DE-2 Board From figure (12) to (14) above, it is very obvious that the ECG signals are filtered successfully. The ECG signals that are filtered using Altera FPGA DE2 board are plotted both in the time domain and frequency domain using MATLAB. To ensure the filtered ECG signals from hardware are correct, the same raw ECG signals are filtered again using MATLAB. Both filtered ECG signal using hardware and MATLAB are plotted. It can be summarized that the FIR low pass filter is functioning well. It can filter the noise in the raw ECG signal and gives a similar output if compared to MATLAB s output. If we look into the filtered ECG data, there are slight differences between the filtered ECG signals using Altera FPGA DE2 board and MATLAB. This is due to quantization of filter coefficients from infinite word length to finite word length. The filter coefficients are converted and rounded off because of hardware constraints. However, from the plotting of ECG signals in time domain, it shows that the filter works as expected through the quantization effect. REFERENCES [1] Y. S. Wang, "Implementation of digital filter by using FPGA," Bachelor of Engineering, Curtin University of Technology, [2] J. S. Wang, et al., "Research on Denoising Algorithm for ECG Signals," in Proceedings of the 29th Chinese Control Conference, Beijing, China, July 29-31, 2010, pp [3] R. Chand, et al., "FPGA Implementation of Fast FIR Low Pass Filter for EMG Removal from ECG Signal," IEEE, vol , [4] Z. D. Zhao and Y. Q. Chen, "A NEW METHOD FOR REMOVAL OF BASELINE WANDER AND POWER LINE INTERFERENCE IN ECG SIGNALS," in Proceedings of the Fifth International Conference on Machine Learning and Cybernetics Dalian, August

7 16, 2006, pp [5] A. K. Ziarani and A. Konrad, "A Nonlinear Adaptive Method of Elimination of Power Line Interference in ECG Signals," IEEE Transactions on Biomedical Engineering, vol. 49(6), pp , [6] P. Ranjan, "Implementation of FIR Filters on FPGA," Master Thesis, Department of Electronics and Communication Engineering, Thapar University, Punjab, India, [7] B. A. Shenoi, Introduction to Digital Signal Processing and Filter Design: John Wiley & Sons, Inc, [8] M. H. Hayes, Schaum's Outlines Digital Signal Processing: The McGraw-Hill Companies, [9] U. Meyer-Basese, Digital Signal Processing with Field Programmable Gate Array. New York: Springer-Verlag Berlin Heidelberg, [10] V. K. Madisetti, Digital Signal Processing undamentals, Second ed.: Taylor and Francis Group, LLC, [11] G. L. Richard, Understanding Digital Signal Processing: New Jersey Prentice Hall [12] S. Joshi and B. Ainapure, "FPGA Based FIR filter," International Journal of Engineering Science and Technology, vol. 2(12), pp , [13] S. Shanthala and S. Y. Kulkarni, "High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications," European Journal of Scientific Research, vol. 31 No.1, pp ,

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